diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/se | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/se')
19 files changed, 12321 insertions, 12847 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 8c91cbc4e..7e42f0dae 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026912 # Number of seconds simulated -sim_ticks 26911921000 # Number of ticks simulated -final_tick 26911921000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026923 # Number of seconds simulated +sim_ticks 26922512500 # Number of ticks simulated +final_tick 26922512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176190 # Simulator instruction rate (inst/s) -host_op_rate 177456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52341651 # Simulator tick rate (ticks/s) -host_mem_usage 402844 # Number of bytes of host memory used -host_seconds 514.16 # Real time elapsed on the host +host_inst_rate 143955 # Simulator instruction rate (inst/s) +host_op_rate 144989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42782119 # Simulator tick rate (ticks/s) +host_mem_usage 446112 # Number of bytes of host memory used +host_seconds 629.29 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 45504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947776 # Number of bytes read from this memory -system.physmem.bytes_read::total 993280 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14809 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15520 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1690849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35217701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36908551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1690849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1690849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1690849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35217701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 36908551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15520 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 45248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 992896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45248 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 707 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1680675 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35199092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36879767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1680675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1680675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1680675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35199092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36879767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15514 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15520 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15514 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 993280 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 992896 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 993280 # Total read bytes from the system interface side +system.physmem.bytesReadSys 992896 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 989 # Per bank write bursts +system.physmem.perBankRdBursts::0 988 # Per bank write bursts system.physmem.perBankRdBursts::1 886 # Per bank write bursts system.physmem.perBankRdBursts::2 942 # Per bank write bursts -system.physmem.perBankRdBursts::3 1029 # Per bank write bursts -system.physmem.perBankRdBursts::4 1049 # Per bank write bursts +system.physmem.perBankRdBursts::3 1028 # Per bank write bursts +system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1105 # Per bank write bursts -system.physmem.perBankRdBursts::6 1079 # Per bank write bursts -system.physmem.perBankRdBursts::7 1079 # Per bank write bursts +system.physmem.perBankRdBursts::6 1078 # Per bank write bursts +system.physmem.perBankRdBursts::7 1078 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 959 # Per bank write bursts +system.physmem.perBankRdBursts::9 956 # Per bank write bursts system.physmem.perBankRdBursts::10 938 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts system.physmem.perBankRdBursts::12 904 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26911727500 # Total gap between requests +system.physmem.totGap 26922312500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15520 # Read request sizes (log2) +system.physmem.readPktSize::6 15514 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 11175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4158 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,167 +154,104 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1591.562701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 476.433802 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 2197.906875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 160 25.72% 25.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 68 10.93% 36.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 41 6.59% 43.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 21 3.38% 46.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 13 2.09% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 6 0.96% 49.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 27 4.34% 54.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 12 1.93% 55.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 5 0.80% 56.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 10 1.61% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3 0.48% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 4 0.64% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 5 0.80% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.29% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.48% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.48% 62.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 6 0.96% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 2 0.32% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.32% 64.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.48% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.32% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.64% 65.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6 0.96% 66.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 19 3.05% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 6 0.96% 70.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 6 0.96% 71.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 3 0.48% 72.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.48% 72.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.16% 72.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 6 0.96% 73.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.32% 73.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 6 0.96% 74.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.32% 75.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.16% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 3 0.48% 75.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.16% 76.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 2 0.32% 76.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.16% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 5 0.80% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 4 0.64% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 2 0.32% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 3 0.48% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 4 0.64% 79.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.32% 79.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 2 0.32% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.32% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.48% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.16% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.32% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.16% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 3 0.48% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.48% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.32% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.16% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.16% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.16% 83.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.48% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 2 0.32% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.16% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 3 0.48% 84.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.64% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 4 0.64% 86.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.16% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.48% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.32% 86.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.32% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.16% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.32% 87.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.16% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.32% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.80% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 3 0.48% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.64% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.32% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.96% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 3 0.48% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.16% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.16% 92.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 1 0.16% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.16% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.48% 93.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.16% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.32% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 1 0.16% 93.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.32% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.48% 94.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.16% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 2 0.32% 95.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.16% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.48% 95.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.16% 95.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.16% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.16% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.16% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.16% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.32% 96.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.16% 96.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.16% 97.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.16% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.16% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.16% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.16% 97.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.32% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 12 1.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 622 # Bytes accessed per row activation -system.physmem.totQLat 103005000 # Total ticks spent queuing -system.physmem.totMemAccLat 356453750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77600000 # Total ticks spent in databus transfers -system.physmem.totBankLat 175848750 # Total ticks spent accessing banks -system.physmem.avgQLat 6636.92 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 11330.46 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 880 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 935.927273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 827.602742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.440032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 4.66% 4.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 26 2.95% 7.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 1.48% 9.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 0.45% 9.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 0.57% 10.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 0.23% 10.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 0.23% 10.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.11% 10.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 786 89.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 880 # Bytes accessed per row activation +system.physmem.totQLat 108095000 # Total ticks spent queuing +system.physmem.totMemAccLat 369557500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77570000 # Total ticks spent in databus transfers +system.physmem.totBankLat 183892500 # Total ticks spent accessing banks +system.physmem.avgQLat 6967.58 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 11853.33 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22967.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23820.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 36.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 36.88 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14898 # Number of row buffer hits during reads +system.physmem.readRowHits 14141 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1734003.06 # Average gap between requests -system.physmem.pageHitRate 95.99 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.99 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 36908551 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 982 # Transaction distribution -system.membus.trans_dist::ReadResp 982 # Transaction distribution +system.physmem.avgGap 1735355.97 # Average gap between requests +system.physmem.pageHitRate 91.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.09 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 36879767 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 976 # Transaction distribution +system.membus.trans_dist::ReadResp 976 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 14538 # Transaction distribution system.membus.trans_dist::ReadExResp 14538 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31042 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 993280 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 993280 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 993280 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31030 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 992896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 19254500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 19225500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 145212249 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 144897999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 26683530 # Number of BP lookups -system.cpu.branchPred.condPredicted 22001633 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843091 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11366562 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11283436 # Number of BTB hits +system.cpu.branchPred.lookups 26688187 # Number of BP lookups +system.cpu.branchPred.condPredicted 22005801 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 842567 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11378681 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11285656 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.268679 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 69998 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 165 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.182462 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 176 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -400,133 +337,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53823843 # number of cpu cycles simulated +system.cpu.numCycles 53845026 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14173676 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127895760 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26683530 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11353434 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24037387 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765940 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11314746 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 14173388 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127901014 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26688187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11355616 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24038968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4766662 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11320590 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 8 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13845039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 329540 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53432137 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.410093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.214797 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 13845523 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 330018 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53440501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214653 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29433098 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3389468 6.34% 61.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2029496 3.80% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1553729 2.91% 68.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1668795 3.12% 71.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919650 5.46% 76.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1509735 2.83% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1090422 2.04% 81.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9837744 18.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29439765 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3390250 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2029247 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1554755 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1667292 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2920236 5.46% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1512043 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1089860 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9837053 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53432137 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.495757 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.376192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937041 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9161066 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22405812 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1030640 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897578 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4444113 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8703 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126077551 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42669 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18718868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3591285 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 186478 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21552610 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5485318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123153621 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 426233 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4596906 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1480 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143604331 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536493258 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499981919 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 760 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53440501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.495648 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.375354 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16937222 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9166719 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22408314 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1029433 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3898813 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4444354 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8681 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126084070 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42675 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3898813 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18718559 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3593311 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 188330 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21554671 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5486817 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123168222 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 424808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4599857 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1460 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143625263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536555031 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 500037832 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 718 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36190145 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4605 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4603 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12541075 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29476574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5520683 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2151148 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1293650 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118168195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8471 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105168426 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79356 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26740210 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65568590 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53432137 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.968262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.908954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36211077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4609 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4607 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12545622 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29481569 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5520172 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2131780 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1278964 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118183319 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105169429 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79348 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26754797 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65616265 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53440501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.967972 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909350 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15374181 28.77% 28.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11650585 21.80% 50.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8250698 15.44% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6826591 12.78% 78.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4953996 9.27% 88.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2948586 5.52% 93.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2456814 4.60% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528614 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 442072 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15384800 28.79% 28.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11651642 21.80% 50.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8259769 15.46% 66.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6813523 12.75% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4933870 9.23% 88.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2968386 5.55% 93.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2461371 4.61% 98.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 525076 0.98% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442064 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53432137 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53440501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45737 6.91% 6.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340297 51.45% 58.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275411 41.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 46222 6.98% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 26 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 339934 51.34% 58.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275932 41.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74430007 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74431142 70.77% 70.77% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10980 0.01% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued @@ -549,90 +486,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 130 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 132 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 172 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25613380 24.35% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5113753 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25611933 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5115067 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105168426 # Type of FU issued -system.cpu.iq.rate 1.953938 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661472 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264509133 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144921601 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102693545 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 684 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 985 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 281 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105829562 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 441614 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105169429 # Type of FU issued +system.cpu.iq.rate 1.953187 # Inst issue rate +system.cpu.iq.fu_busy_cnt 662114 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006296 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264520145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144951370 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102696867 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 287 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105831206 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 441415 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6902608 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6756 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6465 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 775839 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6907603 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6432 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6446 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 775328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31615 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31602 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 958412 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126923 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118189357 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 310100 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29476574 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5520683 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4583 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 65855 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6705 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6465 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 447219 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445977 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 893196 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104191790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25292626 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 976636 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3898813 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 959371 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127029 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118204490 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 309594 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29481569 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5520172 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66074 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6711 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6446 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 446623 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445838 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 892461 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104194994 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25292197 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 974435 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12691 # number of nop insts executed -system.cpu.iew.exec_refs 30349836 # number of memory reference insts executed -system.cpu.iew.exec_branches 21326689 # Number of branches executed -system.cpu.iew.exec_stores 5057210 # Number of stores executed -system.cpu.iew.exec_rate 1.935792 # Inst execution rate -system.cpu.iew.wb_sent 102971901 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102693826 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62250392 # num instructions producing a value -system.cpu.iew.wb_consumers 104309215 # num instructions consuming a value +system.cpu.iew.exec_nop 12694 # number of nop insts executed +system.cpu.iew.exec_refs 30350924 # number of memory reference insts executed +system.cpu.iew.exec_branches 21328461 # Number of branches executed +system.cpu.iew.exec_stores 5058727 # Number of stores executed +system.cpu.iew.exec_rate 1.935090 # Inst execution rate +system.cpu.iew.wb_sent 102975092 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102697154 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62242577 # num instructions producing a value +system.cpu.iew.wb_consumers 104291686 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.907962 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596787 # average fanout of values written-back +system.cpu.iew.wb_rate 1.907273 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596812 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26939334 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26954537 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834485 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49534559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.842208 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.540547 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 833969 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49541688 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.841943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.539958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20043988 40.46% 40.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13146531 26.54% 67.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4167490 8.41% 75.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3431351 6.93% 82.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1535298 3.10% 85.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 726633 1.47% 86.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 954931 1.93% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 253243 0.51% 89.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5275094 10.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20036957 40.44% 40.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13159597 26.56% 67.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4169965 8.42% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431804 6.93% 82.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1536139 3.10% 85.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 734203 1.48% 86.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 944467 1.91% 88.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 252800 0.51% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275756 10.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49534559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49541688 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -643,239 +580,237 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5275094 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275756 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162446025 # The number of ROB reads -system.cpu.rob.rob_writes 240301749 # The number of ROB writes -system.cpu.timesIdled 46102 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 391706 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162467695 # The number of ROB reads +system.cpu.rob.rob_writes 240333520 # The number of ROB writes +system.cpu.timesIdled 46195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 404525 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.594149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.594149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.683079 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.683079 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495606364 # number of integer regfile reads -system.cpu.int_regfile_writes 120553547 # number of integer regfile writes -system.cpu.fp_regfile_reads 143 # number of floating regfile reads -system.cpu.fp_regfile_writes 349 # number of floating regfile writes -system.cpu.misc_regfile_reads 29209842 # number of misc regfile reads +system.cpu.cpi 0.594383 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.594383 # CPI: Total CPI of All Threads +system.cpu.ipc 1.682417 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.682417 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495621667 # number of integer regfile reads +system.cpu.int_regfile_writes 120557380 # number of integer regfile writes +system.cpu.fp_regfile_reads 149 # number of floating regfile reads +system.cpu.fp_regfile_writes 361 # number of floating regfile writes +system.cpu.misc_regfile_reads 29211256 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4497544713 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 904632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 904632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 942884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43696 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1476 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838066 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2839542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 47168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120990272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 121037440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 121037440 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 1888491000 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 4495994050 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43718 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2838210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2839677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120996480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 121043392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121043392 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888584500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1225749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1216499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1424096491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1423941741 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 632.652083 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13844045 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 737 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18784.321574 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 632.458088 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13844537 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18887.499318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 632.652083 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.308912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.308912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 734 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 632.458088 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308817 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308817 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.358398 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27690815 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27690815 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13844045 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13844045 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13844045 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13844045 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13844045 # number of overall hits -system.cpu.icache.overall_hits::total 13844045 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 993 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 993 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 993 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 993 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 993 # number of overall misses -system.cpu.icache.overall_misses::total 993 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 66969998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 66969998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 66969998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 66969998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 66969998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 66969998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13845038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13845038 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13845038 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13845038 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13845038 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13845038 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000072 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000072 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000072 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000072 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000072 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67442.092649 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67442.092649 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67442.092649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67442.092649 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67442.092649 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 594 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.356445 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27691778 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27691778 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13844537 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13844537 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13844537 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13844537 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13844537 # number of overall hits +system.cpu.icache.overall_hits::total 13844537 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 985 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 985 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 985 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 985 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 985 # number of overall misses +system.cpu.icache.overall_misses::total 985 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 65965748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 65965748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 65965748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 65965748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 65965748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 65965748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13845522 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13845522 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13845522 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13845522 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13845522 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13845522 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66970.302538 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66970.302538 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66970.302538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66970.302538 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66970.302538 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 596 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 254 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 254 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 739 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 739 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 739 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 739 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 739 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50789000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50789000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50789000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50789000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50789000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50789000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51030750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51030750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51030750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51030750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51030750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51030750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68726.657645 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68726.657645 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68726.657645 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68726.657645 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68726.657645 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68726.657645 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69524.182561 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69524.182561 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69524.182561 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69524.182561 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10731.098995 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831378 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15503 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 118.130555 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10726.796939 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831454 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 118.181196 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9880.580291 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.669492 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 231.849212 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.301531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.327487 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15503 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 515 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13618 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.473114 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15188896 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15188896 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 9879.688406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 618.475949 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.632584 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.301504 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018874 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006977 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.327356 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13616 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58175.035361 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54785.557507 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54940.021916 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 943493 # number of replacements -system.cpu.dcache.tags.tagsinuse 3671.741279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28144387 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 947589 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.701049 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8006035000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3671.741279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.896421 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.896421 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 943542 # number of replacements +system.cpu.dcache.tags.tagsinuse 3671.682953 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28143982 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 947638 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.699086 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8008531250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3671.682953 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.896407 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.896407 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 511 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 464 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 503 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 59988391 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 59988391 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23603738 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23603738 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4532850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4532850 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3905 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3905 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 59988388 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 59988388 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23603660 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23603660 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532519 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532519 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3912 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3912 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28136588 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28136588 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28136588 # number of overall hits -system.cpu.dcache.overall_hits::total 28136588 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1173883 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1173883 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 202131 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 202131 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28136179 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28136179 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28136179 # number of overall hits +system.cpu.dcache.overall_hits::total 28136179 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173928 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173928 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202462 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202462 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1376014 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1376014 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1376014 # number of overall misses -system.cpu.dcache.overall_misses::total 1376014 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893935229 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13893935229 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8459874583 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8459874583 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1376390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1376390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1376390 # number of overall misses +system.cpu.dcache.overall_misses::total 1376390 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13893768230 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13893768230 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8571552365 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8571552365 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 251500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 251500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22353809812 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22353809812 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22353809812 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22353809812 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24777621 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24777621 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 22465320595 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22465320595 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22465320595 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22465320595 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24777588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24777588 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3912 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29512602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29512602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29512602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29512602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047377 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047377 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042689 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.042689 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046625 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046625 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046625 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046625 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.877365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.877365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41853.424675 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41853.424675 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 29512569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29512569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29512569 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29512569 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047379 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047379 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042759 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001786 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046637 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046637 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046637 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046637 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11835.281406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11835.281406 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42336.598300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42336.598300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35928.571429 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35928.571429 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16245.336030 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16245.336030 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16245.336030 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 154233 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16321.915006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16321.915006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16321.915006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 154484 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23951 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23933 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.439522 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.454853 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942884 # number of writebacks -system.cpu.dcache.writebacks::total 942884 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269973 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 269973 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158450 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158450 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942932 # number of writebacks +system.cpu.dcache.writebacks::total 942932 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269988 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269988 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158763 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158763 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 428423 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 428423 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 428423 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 428423 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43681 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43681 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947591 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947591 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947591 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947591 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994274260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994274260 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1319346668 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1319346668 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11313620928 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11313620928 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11313620928 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11313620928 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009225 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032108 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032108 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.713899 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.713899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30204.131499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30204.131499 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11939.350340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11939.350340 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 428751 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428751 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428751 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428751 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903940 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903940 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43699 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43699 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947639 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947639 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947639 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947639 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9994791010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9994791010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1332397702 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1332397702 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11327188712 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11327188712 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11327188712 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11327188712 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009229 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009229 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032110 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11056.918612 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11056.918612 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30490.347651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30490.347651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11953.063046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11953.063046 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 167e49074..1b324ac26 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065614 # Number of seconds simulated -sim_ticks 65613727000 # Number of ticks simulated -final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065578 # Number of seconds simulated +sim_ticks 65578127500 # Number of ticks simulated +final_tick 65578127500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111661 # Simulator instruction rate (inst/s) -host_op_rate 196618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46373693 # Simulator tick rate (ticks/s) -host_mem_usage 390932 # Number of bytes of host memory used -host_seconds 1414.89 # Real time elapsed on the host +host_inst_rate 88175 # Simulator instruction rate (inst/s) +host_op_rate 155262 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36599742 # Simulator tick rate (ticks/s) +host_mem_usage 427692 # Number of bytes of host memory used +host_seconds 1791.76 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10688 # Number of bytes written to this memory -system.physmem.bytes_written::total 10688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 167 # Number of write requests responded to by this memory -system.physmem.num_writes::total 167 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 969553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28700336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29669889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 969553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 969553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 162893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 162893 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 162893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 969553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28700336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29832782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30419 # Number of read requests accepted -system.physmem.writeReqs 167 # Number of write requests accepted -system.physmem.readBursts 30419 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2880 # Total number of bytes read from write queue -system.physmem.bytesWritten 9856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1946816 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 45 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 63744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882880 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10368 # Number of bytes written to this memory +system.physmem.bytes_written::total 10368 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 996 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29420 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30416 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 162 # Number of write requests responded to by this memory +system.physmem.num_writes::total 162 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 972031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28712012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29684044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 972031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 972031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158101 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 972031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28712012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29842145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30418 # Number of read requests accepted +system.physmem.writeReqs 162 # Number of write requests accepted +system.physmem.readBursts 30418 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1942912 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3840 # Total number of bytes read from write queue +system.physmem.bytesWritten 8384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1946752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10368 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 60 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2077 # Per bank write bursts -system.physmem.perBankRdBursts::2 2029 # Per bank write bursts -system.physmem.perBankRdBursts::3 1927 # Per bank write bursts +system.physmem.perBankRdBursts::0 1927 # Per bank write bursts +system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::2 2026 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts -system.physmem.perBankRdBursts::5 1899 # Per bank write bursts -system.physmem.perBankRdBursts::6 1963 # Per bank write bursts +system.physmem.perBankRdBursts::5 1900 # Per bank write bursts +system.physmem.perBankRdBursts::6 1961 # Per bank write bursts system.physmem.perBankRdBursts::7 1862 # Per bank write bursts -system.physmem.perBankRdBursts::8 1939 # Per bank write bursts +system.physmem.perBankRdBursts::8 1940 # Per bank write bursts system.physmem.perBankRdBursts::9 1933 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1795 # Per bank write bursts +system.physmem.perBankRdBursts::11 1796 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1821 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 15 # Per bank write bursts -system.physmem.perBankWrBursts::1 95 # Per bank write bursts -system.physmem.perBankWrBursts::2 7 # Per bank write bursts -system.physmem.perBankWrBursts::3 11 # Per bank write bursts -system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 1818 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 71 # Per bank write bursts +system.physmem.perBankWrBursts::2 3 # Per bank write bursts +system.physmem.perBankWrBursts::3 17 # Per bank write bursts +system.physmem.perBankWrBursts::4 12 # Per bank write bursts system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::6 10 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65613689500 # Total gap between requests +system.physmem.totGap 65578111000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30419 # Read request sizes (log2) +system.physmem.readPktSize::6 30418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29918 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29902 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,280 +129,243 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1527.767843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 562.023414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1657.823974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 326 25.57% 25.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 105 8.24% 33.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 43 3.37% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 28 2.20% 39.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 22 1.73% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 22 1.73% 42.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 19 1.49% 44.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 15 1.18% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 17 1.33% 46.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 13 1.02% 47.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 46 3.61% 51.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 12 0.94% 52.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 8 0.63% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 7 0.55% 53.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 12 0.94% 54.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 11 0.86% 55.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 8 0.63% 56.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 16 1.25% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 7 0.55% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 9 0.71% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 9 0.71% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 7 0.55% 59.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 11 0.86% 60.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 6 0.47% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 14 1.10% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 4 0.31% 62.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 9 0.71% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 6 0.47% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 3 0.24% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 12 0.94% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 12 0.94% 65.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 8 0.63% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 32 2.51% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 7 0.55% 69.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 7 0.55% 70.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 5 0.39% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 6 0.47% 70.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 10 0.78% 71.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 5 0.39% 72.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 7 0.55% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 3 0.24% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 9 0.71% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.55% 74.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.47% 74.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 5 0.39% 74.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 11 0.86% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 9 0.71% 76.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 7 0.55% 77.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 5 0.39% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 5 0.39% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 8 0.63% 78.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 11 0.86% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 9 0.71% 80.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 10 0.78% 80.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 12 0.94% 81.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 15 1.18% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 10 0.78% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 14 1.10% 84.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 9 0.71% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 8 0.63% 86.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 8 0.63% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 15 1.18% 88.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 13 1.02% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 11 0.86% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 21 1.65% 91.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 10 0.78% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 6 0.47% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 7 0.55% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 4 0.31% 93.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 5 0.39% 94.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 4 0.31% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 4 0.31% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 6 0.47% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 7 0.55% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 5 0.39% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 6 0.47% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 5 0.39% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 6 0.47% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 5 0.39% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 6 0.47% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.31% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 2 0.16% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 2 0.16% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 2 0.16% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 2 0.16% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 1 0.08% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 1 0.08% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.08% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 1 0.08% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 1 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592 1 0.08% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656 3 0.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1275 # Bytes accessed per row activation -system.physmem.totQLat 92483500 # Total ticks spent queuing -system.physmem.totMemAccLat 678771000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151870000 # Total ticks spent in databus transfers -system.physmem.totBankLat 434417500 # Total ticks spent accessing banks -system.physmem.avgQLat 3044.82 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14302.28 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 934.162679 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.717230 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 264.349754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 77 4.61% 4.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 54 3.23% 7.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 1.14% 8.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 0.60% 9.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 0.66% 10.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 0.30% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 0.36% 10.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 0.24% 11.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1486 88.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1672 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 4327.142857 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 47.742498 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 11404.448466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6 85.71% 85.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 14.29% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.714286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.459831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.545621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3 42.86% 42.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 42.86% 85.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 14.29% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.physmem.totQLat 98355750 # Total ticks spent queuing +system.physmem.totMemAccLat 704267000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151790000 # Total ticks spent in databus transfers +system.physmem.totBankLat 454121250 # Total ticks spent accessing banks +system.physmem.avgQLat 3239.86 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14958.87 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 22347.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23198.73 # Average memory access latency per DRAM burst system.physmem.avgRdBW 29.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 0.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.96 # Average write queue length when enqueuing -system.physmem.readRowHits 29156 # Number of row buffer hits during reads -system.physmem.writeRowHits 97 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes -system.physmem.avgGap 2145219.69 # Average gap between requests -system.physmem.pageHitRate 95.78 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.92 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 29832782 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1416 # Transaction distribution -system.membus.trans_dist::ReadResp 1415 # Transaction distribution -system.membus.trans_dist::Writeback 167 # Transaction distribution +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.72 # Average write queue length when enqueuing +system.physmem.readRowHits 27690 # Number of row buffer hits during reads +system.physmem.writeRowHits 93 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes +system.physmem.avgGap 2144477.14 # Average gap between requests +system.physmem.pageHitRate 91.03 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.03 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 29841169 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1415 # Transaction distribution +system.membus.trans_dist::ReadResp 1412 # Transaction distribution +system.membus.trans_dist::Writeback 162 # Transaction distribution system.membus.trans_dist::ReadExReq 29003 # Transaction distribution system.membus.trans_dist::ReadExResp 29003 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61004 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61004 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61004 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1957440 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1957440 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60995 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956928 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 34950500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 34882000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284250750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 33859770 # Number of BP lookups -system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19306649 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19202709 # Number of BTB hits +system.cpu.branchPred.lookups 33848859 # Number of BP lookups +system.cpu.branchPred.condPredicted 33848859 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 773675 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19289255 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19197917 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.526482 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5013789 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5382 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131227460 # number of cpu cycles simulated +system.cpu.numCycles 131156258 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26135230 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182265293 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33859770 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24219454 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55459629 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5354571 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44982751 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26124618 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182201449 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33848859 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24211706 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55441130 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5339784 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44953696 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25575393 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166244 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 131122211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.450609 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.313707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25565447 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166050 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 131050652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.451103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.313857 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 78139546 59.59% 59.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1960111 1.49% 61.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2942175 2.24% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3833696 2.92% 66.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7767416 5.92% 72.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757872 3.63% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2665225 2.03% 77.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316047 1.00% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27740123 21.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 78085477 59.58% 59.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1960121 1.50% 61.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941365 2.24% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3832581 2.92% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7765611 5.93% 72.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4754905 3.63% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2663892 2.03% 77.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1315906 1.00% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27730794 21.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131122211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258024 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.388926 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36831320 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 37195756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43906245 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8644656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4544234 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318852911 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4544234 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42322552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9742718 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7418 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46754999 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27750290 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 315016174 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 215 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26317 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25895473 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 317188133 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836523485 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 515056961 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 484 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131050652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258080 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.389194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36811004 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 37176024 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43889002 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8643749 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4530873 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318736109 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4530873 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42298555 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9762867 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46737142 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27713810 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314904511 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 214 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26056 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25855633 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317074927 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836235433 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 514870937 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 492 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37975386 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 483 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62628696 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101555761 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34778058 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39627069 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5861390 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311484166 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1638 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300275524 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89306 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32714418 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46115217 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1193 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131122211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.290043 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.698539 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37862180 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 484 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 482 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62586078 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101522320 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34765778 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39602927 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5818030 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311370743 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1646 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300208382 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 88815 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32598997 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 45935189 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1201 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131050652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.700647 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24369701 18.59% 18.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23163237 17.67% 36.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25526976 19.47% 55.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25864200 19.73% 75.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18882898 14.40% 89.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8250397 6.29% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3948647 3.01% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 938964 0.72% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 177191 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24364795 18.59% 18.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23214690 17.71% 36.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25426307 19.40% 55.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25814267 19.70% 75.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18862103 14.39% 89.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8277108 6.32% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3959654 3.02% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 947423 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 184305 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131122211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131050652 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31436 1.53% 1.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31474 1.53% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available @@ -431,118 +394,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1917677 93.05% 94.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111849 5.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1916835 93.04% 94.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111878 5.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169841029 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11216 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 34 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97301451 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33090186 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169792966 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11226 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 332 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97287204 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33085346 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300275524 # Type of FU issued -system.cpu.iq.rate 2.288206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2060962 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733823004 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344232038 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298020704 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 523 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302304968 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54149706 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300208382 # Type of FU issued +system.cpu.iq.rate 2.288937 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2060187 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006863 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733615929 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344003056 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 297961989 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 489 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 706 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 149 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302237064 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 228 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54184589 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10776376 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 31265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3338306 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10742935 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32064 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33208 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3326026 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3224 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8563 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 8575 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4544234 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2798212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162335 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311485804 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 196342 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101555761 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34778058 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 4530873 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2837927 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162034 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311372389 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196090 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101522320 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34765778 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 470 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2616 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393170 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 428306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821476 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298872684 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891554 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1402840 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 2524 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73590 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33208 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427924 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 820434 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298810960 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96874788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1397422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129817497 # number of memory reference insts executed -system.cpu.iew.exec_branches 30820824 # Number of branches executed -system.cpu.iew.exec_stores 32925943 # Number of stores executed -system.cpu.iew.exec_rate 2.277516 # Inst execution rate -system.cpu.iew.wb_sent 298390596 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298020860 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218260006 # num instructions producing a value -system.cpu.iew.wb_consumers 296755223 # num instructions consuming a value +system.cpu.iew.exec_refs 129797042 # number of memory reference insts executed +system.cpu.iew.exec_branches 30816203 # Number of branches executed +system.cpu.iew.exec_stores 32922254 # Number of stores executed +system.cpu.iew.exec_rate 2.278282 # Inst execution rate +system.cpu.iew.wb_sent 298329085 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 297962138 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218205948 # num instructions producing a value +system.cpu.iew.wb_consumers 296684532 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.271025 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735488 # average fanout of values written-back +system.cpu.iew.wb_rate 2.271810 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33306189 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33192838 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774954 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126577977 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.197795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.970921 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 773712 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126519779 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.198806 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.971927 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58251121 46.02% 46.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19170530 15.15% 61.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11719383 9.26% 70.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9409192 7.43% 77.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1839491 1.45% 79.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2078967 1.64% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1287907 1.02% 81.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 695737 0.55% 82.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22125649 17.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58265880 46.05% 46.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19155859 15.14% 61.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11581370 9.15% 70.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445264 7.47% 77.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880302 1.49% 79.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2071430 1.64% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1302334 1.03% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 693009 0.55% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22124331 17.49% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126577977 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126519779 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -553,100 +516,100 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22125649 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22124331 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415950981 # The number of ROB reads -system.cpu.rob.rob_writes 627545399 # The number of ROB writes -system.cpu.timesIdled 13719 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 105249 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415780750 # The number of ROB reads +system.cpu.rob.rob_writes 627305222 # The number of ROB writes +system.cpu.timesIdled 13712 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 105606 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.830614 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.830614 # CPI: Total CPI of All Threads -system.cpu.ipc 1.203929 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.203929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 483744129 # number of integer regfile reads -system.cpu.int_regfile_writes 234595251 # number of integer regfile writes -system.cpu.fp_regfile_reads 141 # number of floating regfile reads -system.cpu.fp_regfile_writes 77 # number of floating regfile writes -system.cpu.cc_regfile_reads 107058970 # number of cc regfile reads -system.cpu.cc_regfile_writes 64002830 # number of cc regfile writes -system.cpu.misc_regfile_reads 191827908 # number of misc regfile reads +system.cpu.cpi 0.830163 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.830163 # CPI: Total CPI of All Threads +system.cpu.ipc 1.204583 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.204583 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483659759 # number of integer regfile reads +system.cpu.int_regfile_writes 234542237 # number of integer regfile writes +system.cpu.fp_regfile_reads 137 # number of floating regfile reads +system.cpu.fp_regfile_writes 71 # number of floating regfile writes +system.cpu.cc_regfile_reads 107049810 # number of cc regfile reads +system.cpu.cc_regfile_writes 63997871 # number of cc regfile writes +system.cpu.misc_regfile_reads 191792946 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4042576518 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066887 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82323 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2022 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6220108 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6222130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265183808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265248512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265248512 # Total data (bytes) +system.cpu.toL2Bus.throughput 4044284064 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995292 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82322 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221626 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265151808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265216576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265216576 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4139141500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138401000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1689999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1688749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122002000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121628749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 819.642194 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25574088 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1011 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25295.833828 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 55 # number of replacements +system.cpu.icache.tags.tagsinuse 821.703802 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25564150 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1012 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25261.017787 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 821.703802 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.401223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.401223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 957 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 867 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51151797 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51151797 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25574088 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25574088 # number of overall hits -system.cpu.icache.overall_hits::total 25574088 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1305 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1305 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1305 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1305 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1305 # number of overall misses -system.cpu.icache.overall_misses::total 1305 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88661748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88661748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88661748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88661748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88661748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88661748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25575393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25575393 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25575393 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25575393 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25575393 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25575393 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.467285 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51131906 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51131906 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25564150 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25564150 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25564150 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25564150 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25564150 # number of overall hits +system.cpu.icache.overall_hits::total 25564150 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses +system.cpu.icache.overall_misses::total 1297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 90379749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 90379749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 90379749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90379749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 90379749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90379749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25565447 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25565447 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25565447 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25565447 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25565447 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25565447 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67940.036782 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67940.036782 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67940.036782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67940.036782 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67940.036782 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69683.692367 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69683.692367 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69683.692367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69683.692367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69683.692367 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -655,129 +618,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 38 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 294 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 294 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 294 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 294 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 294 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 294 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69226501 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69226501 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69226501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69226501 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69226501 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69226501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 285 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 285 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 285 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 285 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1012 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1012 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1012 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1012 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1012 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1012 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 70911751 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 70911751 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 70911751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 70911751 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 70911751 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 70911751 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68473.294758 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68473.294758 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68473.294758 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68473.294758 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70070.900198 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70070.900198 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70070.900198 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70070.900198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70070.900198 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70070.900198 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 479 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20806.493932 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029616 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30401 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.548798 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014168 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55909.959759 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58704.976303 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56742.937853 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52124.142330 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52124.142330 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55909.959759 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52218.521665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52339.146586 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57478.162651 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61440.930788 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58651.590106 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52910.345482 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52910.345482 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57478.162651 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53031.829923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53177.419620 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072514 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.513707 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71413623 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.389521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20690834250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072506 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.429006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71361494 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076602 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.364550 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20660759250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.429006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993513 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993513 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 593 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 573 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3367 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150351466 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150351466 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341693 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71413623 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71413623 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71413623 # number of overall hits -system.cpu.dcache.overall_hits::total 71413623 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2625746 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2625746 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98059 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98059 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2723805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2723805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2723805 # number of overall misses -system.cpu.dcache.overall_misses::total 2723805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31399016250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31399016250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2779679498 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2779679498 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34178695748 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34178695748 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34178695748 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34178695748 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42697676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42697676 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150248380 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150248380 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 40019790 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40019790 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71361494 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71361494 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71361494 # number of overall hits +system.cpu.dcache.overall_hits::total 71361494 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626347 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626347 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98048 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98048 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724395 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724395 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724395 # number of overall misses +system.cpu.dcache.overall_misses::total 2724395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31407355250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31407355250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801736997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2801736997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34209092247 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34209092247 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34209092247 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34209092247 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42646137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42646137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74137428 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74137428 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74137428 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74137428 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061496 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061496 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74085889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74085889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74085889 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74085889 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061585 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061585 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036740 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036740 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036740 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036740 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.131613 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.131613 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28347.010453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28347.010453 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12548.143405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12548.143405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12548.143405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32707 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036773 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036773 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036773 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036773 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11958.570307 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11958.570307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28575.157035 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28575.157035 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12556.583112 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12556.583112 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12556.583112 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32689 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9492 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443930 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.443847 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066887 # number of writebacks -system.cpu.dcache.writebacks::total 2066887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631351 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 631351 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15843 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15843 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647194 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647194 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647194 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647194 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994395 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994395 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2066395 # number of writebacks +system.cpu.dcache.writebacks::total 2066395 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15832 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15832 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647790 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647790 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647790 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647790 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994389 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994389 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82216 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 82216 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076611 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076611 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076611 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076611 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21996462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21996462750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2491650748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2491650748 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488113498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24488113498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488113498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24488113498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046710 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046710 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076605 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076605 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076605 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076605 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21997400000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21997400000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514181749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514181749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24511581749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24511581749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24511581749 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24511581749 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046766 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046766 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028010 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028010 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.140541 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.140541 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30306.153887 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30306.153887 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11792.345075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11792.345075 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028030 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028030 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028030 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11029.643665 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11029.643665 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30580.200314 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30580.200314 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11803.680406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11803.680406 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4ea8f08d5..50a810bbd 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202697 # Number of seconds simulated -sim_ticks 202696649500 # Number of ticks simulated -final_tick 202696649500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202387 # Number of seconds simulated +sim_ticks 202386636500 # Number of ticks simulated +final_tick 202386636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142513 # Simulator instruction rate (inst/s) -host_op_rate 160675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57175030 # Simulator tick rate (ticks/s) -host_mem_usage 274024 # Number of bytes of host memory used -host_seconds 3545.20 # Real time elapsed on the host +host_inst_rate 118405 # Simulator instruction rate (inst/s) +host_op_rate 133495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47430504 # Simulator tick rate (ticks/s) +host_mem_usage 317288 # Number of bytes of host memory used +host_seconds 4267.01 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 215936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9269696 # Number of bytes read from this memory -system.physmem.bytes_read::total 9485632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 215936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 215936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249792 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3374 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148213 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97653 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97653 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1065316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45731866 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46797182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1065316 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1065316 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30833228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30833228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30833228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1065316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45731866 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77630410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148213 # Number of read requests accepted -system.physmem.writeReqs 97653 # Number of write requests accepted -system.physmem.readBursts 148213 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97653 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9481152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue -system.physmem.bytesWritten 6249152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9485632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6249792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 215296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9261568 # Number of bytes read from this memory +system.physmem.bytes_read::total 9476864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 215296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 215296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6245824 # Number of bytes written to this memory +system.physmem.bytes_written::total 6245824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3364 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144712 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148076 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97591 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97591 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1063786 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45761757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46825542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1063786 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1063786 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30860852 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30860852 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30860852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1063786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45761757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77686394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148077 # Number of read requests accepted +system.physmem.writeReqs 97591 # Number of write requests accepted +system.physmem.readBursts 148077 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97591 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9467712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 6243712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9476928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6245824 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9594 # Per bank write bursts -system.physmem.perBankRdBursts::1 9237 # Per bank write bursts -system.physmem.perBankRdBursts::2 9258 # Per bank write bursts -system.physmem.perBankRdBursts::3 8983 # Per bank write bursts -system.physmem.perBankRdBursts::4 9776 # Per bank write bursts -system.physmem.perBankRdBursts::5 9641 # Per bank write bursts -system.physmem.perBankRdBursts::6 9120 # Per bank write bursts -system.physmem.perBankRdBursts::7 8318 # Per bank write bursts -system.physmem.perBankRdBursts::8 8799 # Per bank write bursts -system.physmem.perBankRdBursts::9 8914 # Per bank write bursts -system.physmem.perBankRdBursts::10 8952 # Per bank write bursts -system.physmem.perBankRdBursts::11 9727 # Per bank write bursts -system.physmem.perBankRdBursts::12 9657 # Per bank write bursts -system.physmem.perBankRdBursts::13 9778 # Per bank write bursts -system.physmem.perBankRdBursts::14 8939 # Per bank write bursts -system.physmem.perBankRdBursts::15 9450 # Per bank write bursts -system.physmem.perBankWrBursts::0 6271 # Per bank write bursts -system.physmem.perBankWrBursts::1 6158 # Per bank write bursts -system.physmem.perBankWrBursts::2 6091 # Per bank write bursts -system.physmem.perBankWrBursts::3 5883 # Per bank write bursts -system.physmem.perBankWrBursts::4 6254 # Per bank write bursts -system.physmem.perBankWrBursts::5 6272 # Per bank write bursts -system.physmem.perBankWrBursts::6 6041 # Per bank write bursts -system.physmem.perBankWrBursts::7 5553 # Per bank write bursts -system.physmem.perBankWrBursts::8 5808 # Per bank write bursts -system.physmem.perBankWrBursts::9 5908 # Per bank write bursts -system.physmem.perBankWrBursts::10 5990 # Per bank write bursts -system.physmem.perBankWrBursts::11 6516 # Per bank write bursts -system.physmem.perBankWrBursts::12 6373 # Per bank write bursts -system.physmem.perBankWrBursts::13 6333 # Per bank write bursts -system.physmem.perBankWrBursts::14 6051 # Per bank write bursts -system.physmem.perBankWrBursts::15 6141 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 9 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9595 # Per bank write bursts +system.physmem.perBankRdBursts::1 9241 # Per bank write bursts +system.physmem.perBankRdBursts::2 9230 # Per bank write bursts +system.physmem.perBankRdBursts::3 8948 # Per bank write bursts +system.physmem.perBankRdBursts::4 9774 # Per bank write bursts +system.physmem.perBankRdBursts::5 9652 # Per bank write bursts +system.physmem.perBankRdBursts::6 9107 # Per bank write bursts +system.physmem.perBankRdBursts::7 8317 # Per bank write bursts +system.physmem.perBankRdBursts::8 8793 # Per bank write bursts +system.physmem.perBankRdBursts::9 8911 # Per bank write bursts +system.physmem.perBankRdBursts::10 8931 # Per bank write bursts +system.physmem.perBankRdBursts::11 9713 # Per bank write bursts +system.physmem.perBankRdBursts::12 9649 # Per bank write bursts +system.physmem.perBankRdBursts::13 9746 # Per bank write bursts +system.physmem.perBankRdBursts::14 8931 # Per bank write bursts +system.physmem.perBankRdBursts::15 9395 # Per bank write bursts +system.physmem.perBankWrBursts::0 6267 # Per bank write bursts +system.physmem.perBankWrBursts::1 6152 # Per bank write bursts +system.physmem.perBankWrBursts::2 6088 # Per bank write bursts +system.physmem.perBankWrBursts::3 5869 # Per bank write bursts +system.physmem.perBankWrBursts::4 6257 # Per bank write bursts +system.physmem.perBankWrBursts::5 6287 # Per bank write bursts +system.physmem.perBankWrBursts::6 6043 # Per bank write bursts +system.physmem.perBankWrBursts::7 5545 # Per bank write bursts +system.physmem.perBankWrBursts::8 5805 # Per bank write bursts +system.physmem.perBankWrBursts::9 5895 # Per bank write bursts +system.physmem.perBankWrBursts::10 5984 # Per bank write bursts +system.physmem.perBankWrBursts::11 6504 # Per bank write bursts +system.physmem.perBankWrBursts::12 6370 # Per bank write bursts +system.physmem.perBankWrBursts::13 6330 # Per bank write bursts +system.physmem.perBankWrBursts::14 6044 # Per bank write bursts +system.physmem.perBankWrBursts::15 6118 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 202696525000 # Total gap between requests +system.physmem.totGap 202386616500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 148213 # Read request sizes (log2) +system.physmem.readPktSize::6 148077 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97653 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97591 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -129,177 +129,177 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.469277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.950297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.311281 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 32073 46.38% 46.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 12750 18.44% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 5391 7.80% 72.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 3340 4.83% 77.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 2388 3.45% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 2364 3.42% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 3443 4.98% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 1961 2.84% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 807 1.17% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 577 0.83% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 471 0.68% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 358 0.52% 95.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 272 0.39% 95.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 260 0.38% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 188 0.27% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 160 0.23% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 170 0.25% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 142 0.21% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 124 0.18% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 152 0.22% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 134 0.19% 97.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 815 1.18% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 105 0.15% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 136 0.20% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 73 0.11% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 89 0.13% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 48 0.07% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 64 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 20 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 34 0.05% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 22 0.03% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 21 0.03% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 9 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 15 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 7 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 10 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 7 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 7 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 10 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 8 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 7 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 4 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 2 0.00% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 4 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 2 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 3 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 4 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 5 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 2 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 1 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 4 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 4 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 2 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 4 0.01% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 4 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 1 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 6 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 8 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 4 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69151 # Bytes accessed per row activation -system.physmem.totQLat 1733842500 # Total ticks spent queuing -system.physmem.totMemAccLat 4938805000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 740715000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2464247500 # Total ticks spent accessing banks -system.physmem.avgQLat 11703.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16634.25 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 257.573029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.018208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.256707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15558 39.26% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11171 28.19% 67.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4346 10.97% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2186 5.52% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1365 3.44% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 780 1.97% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 563 1.42% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 515 1.30% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3144 7.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39628 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5484 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.971554 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 384.653172 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5482 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5484 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5484 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.789570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.450739 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 4.762634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 3346 61.01% 61.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1810 33.01% 94.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 182 3.32% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 11 0.20% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 3 0.05% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 4 0.07% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 3 0.05% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 1 0.02% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.02% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 12 0.22% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 29 0.53% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 19 0.35% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 8 0.15% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 7 0.13% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 7 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 8 0.15% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 9 0.16% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 6 0.11% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 2 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5484 # Writes before turning the bus around for reads +system.physmem.totQLat 1351646500 # Total ticks spent queuing +system.physmem.totMemAccLat 4559189000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 739665000 # Total ticks spent in databus transfers +system.physmem.totBankLat 2467877500 # Total ticks spent accessing banks +system.physmem.avgQLat 9136.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16682.40 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33338.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30819.28 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 30.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 46.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 30.83 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 30.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.83 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 30.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.busUtilRead 0.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.24 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.92 # Average write queue length when enqueuing -system.physmem.readRowHits 118670 # Number of row buffer hits during reads -system.physmem.writeRowHits 57965 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes -system.physmem.avgGap 824418.69 # Average gap between requests -system.physmem.pageHitRate 71.86 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.58 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 77630410 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46935 # Transaction distribution -system.membus.trans_dist::ReadResp 46935 # Transaction distribution -system.membus.trans_dist::Writeback 97653 # Transaction distribution -system.membus.trans_dist::UpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 101278 # Transaction distribution -system.membus.trans_dist::ReadExResp 101278 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394093 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 394093 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15735424 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15735424 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15735424 # Total data (bytes) +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.36 # Average write queue length when enqueuing +system.physmem.readRowHits 116029 # Number of row buffer hits during reads +system.physmem.writeRowHits 64903 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.51 # Row buffer hit rate for writes +system.physmem.avgGap 823821.65 # Average gap between requests +system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 4.51 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 77686394 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46784 # Transaction distribution +system.membus.trans_dist::ReadResp 46783 # Transaction distribution +system.membus.trans_dist::Writeback 97591 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101293 # Transaction distribution +system.membus.trans_dist::ReadExResp 101293 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 393762 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15722688 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 15722688 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15722688 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1083458000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1083423500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1398218993 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1396187241 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 182767812 # Number of BP lookups -system.cpu.branchPred.condPredicted 143090812 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7262422 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93142512 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87193307 # Number of BTB hits +system.cpu.branchPred.lookups 182802497 # Number of BP lookups +system.cpu.branchPred.condPredicted 143128799 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92710665 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87222146 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.612793 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12680291 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116092 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.079949 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678300 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116271 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -385,134 +385,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 405393300 # number of cpu cycles simulated +system.cpu.numCycles 404773274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119358761 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761461935 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182767812 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99873598 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170116443 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35667741 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77537943 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 427 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 119371431 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761670050 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182802497 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99900446 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170159805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35695191 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77489066 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 40 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 409 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114511433 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2436940 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394614975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.164245 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.986660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 114520254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2435167 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394646362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164609 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.986746 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224511182 56.89% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14185619 3.59% 60.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22882928 5.80% 66.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22735959 5.76% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20902964 5.30% 77.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599090 2.94% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13052635 3.31% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11995684 3.04% 86.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52748914 13.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224499175 56.89% 56.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14180048 3.59% 60.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22900330 5.80% 66.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22746018 5.76% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20904181 5.30% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11597078 2.94% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13062660 3.31% 83.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996924 3.04% 86.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52759948 13.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394614975 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.450841 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.878329 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129045860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 73029235 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158776788 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6235766 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27527326 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26113836 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825433505 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27527326 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135634392 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10115343 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47882338 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158241210 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15214366 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800503248 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1357 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3055222 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8963577 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 323 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954180101 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3518022066 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3236814887 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 394646362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451617 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.881720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129065441 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72977589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158843318 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6208520 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27551494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26113840 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76933 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825615862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 295408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27551494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135663599 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10124037 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47858907 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158270703 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15177622 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800676203 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1362 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3041401 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8927839 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 380 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954380743 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3518821037 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3237543722 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287927810 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293035 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293033 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41823481 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170244853 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73468690 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28584671 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15947575 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 754970143 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665247715 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1368678 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187299729 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479807189 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797814 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394614975 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.685815 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.734907 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288128452 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2293069 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2293066 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41767697 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170285712 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73492930 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28608200 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15804502 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755130380 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775454 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665331830 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1375167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187454297 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 480174835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394646362 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.685894 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 139112608 35.25% 35.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69963718 17.73% 52.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71480339 18.11% 71.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53412881 13.54% 84.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31169155 7.90% 92.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15993671 4.05% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8759011 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2903101 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820491 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 139160941 35.26% 35.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69972049 17.73% 52.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71433490 18.10% 71.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53381143 13.53% 84.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31203736 7.91% 92.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16006372 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8742132 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2922216 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1824283 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394614975 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394646362 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480625 5.03% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6529255 68.28% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2553152 26.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481604 5.01% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6543314 68.07% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2587932 26.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447743251 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383309 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447808389 67.31% 67.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383403 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued @@ -540,84 +540,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153363071 23.05% 90.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63757987 9.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153377795 23.05% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63762146 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665247715 # Type of FU issued -system.cpu.iq.rate 1.640993 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9563032 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014375 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1736041890 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946851577 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 645982069 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 225 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665331830 # Type of FU issued +system.cpu.iq.rate 1.643715 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9612850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014448 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1736297816 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947166381 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646062448 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674810634 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 674944567 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8546846 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 8567764 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44215298 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41270 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810207 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16608213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44256157 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42344 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16632453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8279 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19504 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27527326 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5271033 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 384981 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760303523 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1119045 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170244853 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73468690 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286904 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219731 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810207 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335544 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001823 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8337367 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655831134 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150081839 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9416581 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27551494 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5275843 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386509 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760464256 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1125230 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170285712 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73492930 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286912 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 220350 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11309 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4338774 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002387 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341161 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655913475 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150097155 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9418355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1557934 # number of nop insts executed -system.cpu.iew.exec_refs 212547196 # number of memory reference insts executed -system.cpu.iew.exec_branches 138487054 # Number of branches executed -system.cpu.iew.exec_stores 62465357 # Number of stores executed -system.cpu.iew.exec_rate 1.617765 # Inst execution rate -system.cpu.iew.wb_sent 650951989 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 645982085 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374676308 # num instructions producing a value -system.cpu.iew.wb_consumers 646230138 # num instructions consuming a value +system.cpu.iew.exec_nop 1558422 # number of nop insts executed +system.cpu.iew.exec_refs 212571042 # number of memory reference insts executed +system.cpu.iew.exec_branches 138499517 # Number of branches executed +system.cpu.iew.exec_stores 62473887 # Number of stores executed +system.cpu.iew.exec_rate 1.620447 # Inst execution rate +system.cpu.iew.wb_sent 651035258 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646062464 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374747617 # num instructions producing a value +system.cpu.iew.wb_consumers 646369396 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.593470 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579788 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596109 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579773 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189364408 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189524475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7188399 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 367087649 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.555400 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230509 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191502 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 367094868 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.555370 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.229648 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159393543 43.42% 43.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98511772 26.84% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33830447 9.22% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18783252 5.12% 84.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16176645 4.41% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7442765 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6952611 1.89% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3163238 0.86% 93.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22833376 6.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159372239 43.41% 43.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98509322 26.83% 70.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33822268 9.21% 79.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18793314 5.12% 84.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16194287 4.41% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7448885 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7004810 1.91% 92.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3214010 0.88% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22735733 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 367087649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 367094868 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -628,239 +628,243 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22833376 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22735733 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104579710 # The number of ROB reads -system.cpu.rob.rob_writes 1548313166 # The number of ROB writes -system.cpu.timesIdled 328667 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10778325 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104844639 # The number of ROB reads +system.cpu.rob.rob_writes 1548657613 # The number of ROB writes +system.cpu.timesIdled 329536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10126912 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.802381 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.802381 # CPI: Total CPI of All Threads -system.cpu.ipc 1.246290 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.246290 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058357965 # number of integer regfile reads -system.cpu.int_regfile_writes 751931601 # number of integer regfile writes +system.cpu.cpi 0.801154 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.801154 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248199 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248199 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058738251 # number of integer regfile reads +system.cpu.int_regfile_writes 752038270 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 237823379 # number of misc regfile reads +system.cpu.misc_regfile_reads 237846973 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 733902057 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110906 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 71 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 71 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348829 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348829 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3537891 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1073600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147680832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148754432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148754432 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2273126497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735012008 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348779 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33728 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3504101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3537829 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1076352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 147674432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148750784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148750784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 5824 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2273084998 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25848480 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25918735 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1823961981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1823048732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 14927 # number of replacements -system.cpu.icache.tags.tagsinuse 1097.546967 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 114490465 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16785 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6820.998808 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 14973 # number of replacements +system.cpu.icache.tags.tagsinuse 1095.994633 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 114499162 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 16828 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6804.086166 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1097.546967 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.535912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.535912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 229039718 # Number of tag accesses -system.cpu.icache.tags.data_accesses 229039718 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 114490465 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114490465 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114490465 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114490465 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114490465 # number of overall hits -system.cpu.icache.overall_hits::total 114490465 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20967 # number of overall misses -system.cpu.icache.overall_misses::total 20967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 566965977 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 566965977 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 566965977 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 566965977 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 566965977 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 566965977 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114511432 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114511432 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114511432 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114511432 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114511432 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114511432 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000183 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000183 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000183 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000183 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000183 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000183 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27040.872657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27040.872657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27040.872657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27040.872657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27040.872657 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1029 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1095.994633 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.535154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.535154 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1855 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.905762 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 229057415 # Number of tag accesses +system.cpu.icache.tags.data_accesses 229057415 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 114499162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114499162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114499162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114499162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114499162 # number of overall hits +system.cpu.icache.overall_hits::total 114499162 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21091 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21091 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21091 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21091 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21091 # number of overall misses +system.cpu.icache.overall_misses::total 21091 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 555853234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 555853234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 555853234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 555853234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 555853234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 555853234 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114520253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114520253 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114520253 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114520253 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114520253 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114520253 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26354.996634 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26354.996634 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26354.996634 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26354.996634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26354.996634 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26354.996634 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 663 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60.272727 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2348 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1681 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 391455847 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 391455847 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 136212044 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136212044 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988351 # 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number of overall misses -system.cpu.dcache.overall_misses::total 4951844 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29691567711 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29691567711 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 72513714730 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 72513714730 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 595500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 595500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102205282441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102205282441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102205282441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102205282441 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137912933 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137912933 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187191304 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187191304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187191304 # number of overall hits +system.cpu.dcache.overall_hits::total 187191304 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1703703 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1703703 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251087 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251087 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 39 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 39 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4954790 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4954790 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4954790 # number of overall misses +system.cpu.dcache.overall_misses::total 4954790 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29263316713 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29263316713 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 70545580472 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70545580472 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99808897185 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99808897185 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99808897185 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99808897185 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137906788 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137906788 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488840 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488876 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488876 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192152239 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192152239 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192152239 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192152239 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012333 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059937 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059937 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000024 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025770 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025770 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025770 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025770 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17456.499343 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17456.499343 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 22305.357881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 22305.357881 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16541.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16541.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20639.842944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20639.842944 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20639.842944 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17574 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52604 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1663 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.567649 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.582451 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192146094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192146094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192146094 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192146094 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012354 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012354 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059940 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059940 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025787 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025787 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025787 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025787 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17176.301687 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17176.301687 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21699.074947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21699.074947 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16294.871795 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16294.871795 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20143.920769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20143.920769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20143.920769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20143.920769 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17635 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 54424 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1686 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 666 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.459668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 81.717718 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110906 # number of writebacks -system.cpu.dcache.writebacks::total 1110906 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 852565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 852565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902601 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902601 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 36 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3755166 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3755166 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3755166 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3755166 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848324 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848324 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348354 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348354 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196678 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196678 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196678 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196678 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12420423026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12420423026 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10423297989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10423297989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22843721015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22843721015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22843721015 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22843721015 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1110883 # number of writebacks +system.cpu.dcache.writebacks::total 1110883 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 855409 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 855409 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902772 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902772 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 39 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3758181 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3758181 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3758181 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3758181 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848294 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848294 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348315 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348315 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196609 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196609 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196609 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196609 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12295329526 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12295329526 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10170217738 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10170217738 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22465547264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22465547264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22465547264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22465547264 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14641.131249 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14641.131249 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29921.568258 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29921.568258 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19089.279668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19089.279668 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14494.184240 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14494.184240 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29198.334088 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29198.334088 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18774.342550 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18774.342550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18774.342550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18774.342550 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 7553b7709..a5895db0e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459119 # Number of seconds simulated -sim_ticks 459118646000 # Number of ticks simulated -final_tick 459118646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458346 # Number of seconds simulated +sim_ticks 458345683000 # Number of ticks simulated +final_tick 458345683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66655 # Simulator instruction rate (inst/s) -host_op_rate 123253 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37009979 # Simulator tick rate (ticks/s) -host_mem_usage 397004 # Number of bytes of host memory used -host_seconds 12405.27 # Real time elapsed on the host +host_inst_rate 77949 # Simulator instruction rate (inst/s) +host_op_rate 144137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43207948 # Simulator tick rate (ticks/s) +host_mem_usage 382980 # Number of bytes of host memory used +host_seconds 10607.90 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24472064 # Number of bytes read from this memory -system.physmem.bytes_read::total 24674112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18787264 # Number of bytes written to this memory -system.physmem.bytes_written::total 18787264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382376 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293551 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293551 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 440078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53302266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53742344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 440078 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440078 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40920281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40920281 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40920281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 440078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53302266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94662625 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385533 # Number of read requests accepted -system.physmem.writeReqs 293551 # Number of write requests accepted -system.physmem.readBursts 385533 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293551 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24663104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11008 # Total number of bytes read from write queue -system.physmem.bytesWritten 18787008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24674112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18787264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 172 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 201344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476224 # Number of bytes read from this memory +system.physmem.bytes_read::total 24677568 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 201344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 201344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790080 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790080 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3146 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382441 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385587 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293595 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293595 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 439284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53401232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53840516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 439284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40995434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40995434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40995434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 439284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53401232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94835949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385587 # Number of read requests accepted +system.physmem.writeReqs 293595 # Number of write requests accepted +system.physmem.readBursts 385587 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293595 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24655680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18787904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24677568 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790080 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 134286 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24058 # Per bank write bursts -system.physmem.perBankRdBursts::1 26419 # Per bank write bursts -system.physmem.perBankRdBursts::2 24669 # Per bank write bursts -system.physmem.perBankRdBursts::3 24489 # Per bank write bursts -system.physmem.perBankRdBursts::4 23234 # Per bank write bursts -system.physmem.perBankRdBursts::5 23657 # Per bank write bursts -system.physmem.perBankRdBursts::6 24395 # Per bank write bursts -system.physmem.perBankRdBursts::7 24194 # Per bank write bursts -system.physmem.perBankRdBursts::8 23609 # Per bank write bursts -system.physmem.perBankRdBursts::9 23827 # Per bank write bursts -system.physmem.perBankRdBursts::10 24795 # Per bank write bursts -system.physmem.perBankRdBursts::11 24049 # Per bank write bursts -system.physmem.perBankRdBursts::12 23230 # Per bank write bursts -system.physmem.perBankRdBursts::13 22964 # Per bank write bursts -system.physmem.perBankRdBursts::14 23781 # Per bank write bursts -system.physmem.perBankRdBursts::15 23991 # Per bank write bursts -system.physmem.perBankWrBursts::0 18530 # Per bank write bursts -system.physmem.perBankWrBursts::1 19817 # Per bank write bursts -system.physmem.perBankWrBursts::2 18937 # Per bank write bursts -system.physmem.perBankWrBursts::3 18901 # Per bank write bursts -system.physmem.perBankWrBursts::4 18031 # Per bank write bursts -system.physmem.perBankWrBursts::5 18405 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 137451 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 23999 # Per bank write bursts +system.physmem.perBankRdBursts::1 26321 # Per bank write bursts +system.physmem.perBankRdBursts::2 24635 # Per bank write bursts +system.physmem.perBankRdBursts::3 24488 # Per bank write bursts +system.physmem.perBankRdBursts::4 23208 # Per bank write bursts +system.physmem.perBankRdBursts::5 23662 # Per bank write bursts +system.physmem.perBankRdBursts::6 24431 # Per bank write bursts +system.physmem.perBankRdBursts::7 24245 # Per bank write bursts +system.physmem.perBankRdBursts::8 23683 # Per bank write bursts +system.physmem.perBankRdBursts::9 23822 # Per bank write bursts +system.physmem.perBankRdBursts::10 24823 # Per bank write bursts +system.physmem.perBankRdBursts::11 24044 # Per bank write bursts +system.physmem.perBankRdBursts::12 23228 # Per bank write bursts +system.physmem.perBankRdBursts::13 22920 # Per bank write bursts +system.physmem.perBankRdBursts::14 23793 # Per bank write bursts +system.physmem.perBankRdBursts::15 23943 # Per bank write bursts +system.physmem.perBankWrBursts::0 18539 # Per bank write bursts +system.physmem.perBankWrBursts::1 19811 # Per bank write bursts +system.physmem.perBankWrBursts::2 18919 # Per bank write bursts +system.physmem.perBankWrBursts::3 18907 # Per bank write bursts +system.physmem.perBankWrBursts::4 18016 # Per bank write bursts +system.physmem.perBankWrBursts::5 18404 # Per bank write bursts system.physmem.perBankWrBursts::6 18977 # Per bank write bursts -system.physmem.perBankWrBursts::7 18937 # Per bank write bursts -system.physmem.perBankWrBursts::8 18537 # Per bank write bursts -system.physmem.perBankWrBursts::9 18113 # Per bank write bursts -system.physmem.perBankWrBursts::10 18820 # Per bank write bursts -system.physmem.perBankWrBursts::11 17706 # Per bank write bursts +system.physmem.perBankWrBursts::7 18938 # Per bank write bursts +system.physmem.perBankWrBursts::8 18573 # Per bank write bursts +system.physmem.perBankWrBursts::9 18106 # Per bank write bursts +system.physmem.perBankWrBursts::10 18839 # Per bank write bursts +system.physmem.perBankWrBursts::11 17716 # Per bank write bursts system.physmem.perBankWrBursts::12 17343 # Per bank write bursts -system.physmem.perBankWrBursts::13 16958 # Per bank write bursts -system.physmem.perBankWrBursts::14 17714 # Per bank write bursts -system.physmem.perBankWrBursts::15 17821 # Per bank write bursts +system.physmem.perBankWrBursts::13 16932 # Per bank write bursts +system.physmem.perBankWrBursts::14 17725 # Per bank write bursts +system.physmem.perBankWrBursts::15 17816 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 459118532000 # Total gap between requests +system.physmem.totGap 458345657000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385533 # Read request sizes (log2) +system.physmem.readPktSize::6 385587 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293551 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293595 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,327 +129,303 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 13202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 13419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.463932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.686360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 443.719039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63845 43.27% 43.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27907 18.91% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12368 8.38% 70.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7167 4.86% 75.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4813 3.26% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3571 2.42% 81.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2697 1.83% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2226 1.51% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1892 1.28% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1575 1.07% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 1962 1.33% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1193 0.81% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1191 0.81% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1073 0.73% 90.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 940 0.64% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 929 0.63% 91.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1014 0.69% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1122 0.76% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1123 0.76% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 892 0.60% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 768 0.52% 95.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5249 3.56% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 304 0.21% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 220 0.15% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 176 0.12% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 127 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 88 0.06% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 94 0.06% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 86 0.06% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 56 0.04% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 55 0.04% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 48 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 43 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 26 0.02% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 35 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 32 0.02% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 24 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 27 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 18 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 20 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 23 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 18 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 20 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 16 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 19 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 14 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 17 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 12 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 19 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 5 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 18 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 8 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 14 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 10 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 15 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 9 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 11 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 10 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 12 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 14 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 20 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 31 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 4 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 10 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 3 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 2 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 6 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 6 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 4 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 4 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 4 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 1 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 2 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 9 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 11 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147556 # Bytes accessed per row activation -system.physmem.totQLat 3828283250 # Total ticks spent queuing -system.physmem.totMemAccLat 12084928250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1926805000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6329840000 # Total ticks spent accessing banks -system.physmem.avgQLat 9934.28 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16425.74 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 16912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 21550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 16827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 96485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.073856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.339683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 360.153261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30862 31.99% 31.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 25245 26.16% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9104 9.44% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4981 5.16% 72.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3508 3.64% 76.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2549 2.64% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1904 1.97% 81.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1721 1.78% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16611 17.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96485 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 16638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.153564 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 214.001392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 16625 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 16638 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 16638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.644008 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.412925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.984420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 15809 95.02% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 568 3.41% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 13 0.08% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.03% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 61 0.37% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 106 0.64% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.16% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 20 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 16638 # Writes before turning the bus around for reads +system.physmem.totQLat 2817376000 # Total ticks spent queuing +system.physmem.totMemAccLat 11128592250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1926225000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6384991250 # Total ticks spent accessing banks +system.physmem.avgQLat 7313.21 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16573.85 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31360.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 40.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.74 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 40.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28887.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.64 # Average write queue length when enqueuing -system.physmem.readRowHits 326971 # Number of row buffer hits during reads -system.physmem.writeRowHits 204381 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.62 # Row buffer hit rate for writes -system.physmem.avgGap 676085.04 # Average gap between requests -system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.79 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94662625 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178699 # Transaction distribution -system.membus.trans_dist::ReadResp 178699 # Transaction distribution -system.membus.trans_dist::Writeback 293551 # Transaction distribution -system.membus.trans_dist::UpgradeReq 134286 # Transaction distribution -system.membus.trans_dist::UpgradeResp 134286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206834 # Transaction distribution -system.membus.trans_dist::ReadExResp 206834 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1333189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1333189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1333189 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43461376 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43461376 # Total data (bytes) +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.28 # Average write queue length when enqueuing +system.physmem.readRowHits 317177 # Number of row buffer hits during reads +system.physmem.writeRowHits 216322 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes +system.physmem.avgGap 674849.54 # Average gap between requests +system.physmem.pageHitRate 78.59 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.94 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 94835949 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178789 # Transaction distribution +system.membus.trans_dist::ReadResp 178789 # Transaction distribution +system.membus.trans_dist::Writeback 293595 # Transaction distribution +system.membus.trans_dist::UpgradeReq 137451 # Transaction distribution +system.membus.trans_dist::UpgradeResp 137451 # Transaction distribution +system.membus.trans_dist::ReadExReq 206798 # Transaction distribution +system.membus.trans_dist::ReadExResp 206798 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1339671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1339671 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1339671 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43467648 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43467648 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3389612000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3393086500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3899599974 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3901807065 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 205593718 # Number of BP lookups -system.cpu.branchPred.condPredicted 205593718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9903647 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117157105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114691543 # Number of BTB hits +system.cpu.branchPred.lookups 205603387 # Number of BP lookups +system.cpu.branchPred.condPredicted 205603387 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9902113 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117080162 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114702381 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.895508 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25059747 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1804675 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.969100 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25060949 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1802781 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918398587 # number of cpu cycles simulated +system.cpu.numCycles 916852867 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167393029 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131661435 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205593718 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139751290 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352253008 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71076779 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305103735 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255424 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162015300 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2531137 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 885975121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.376486 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167425421 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131697501 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205603387 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139763330 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352285469 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71105811 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 304521969 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 48109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 252946 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162022121 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2522560 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 885484431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.378017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324314 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 537792455 60.70% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23395629 2.64% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25258320 2.85% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27887801 3.15% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17745441 2.00% 71.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22910084 2.59% 73.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29420868 3.32% 77.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26641357 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174923166 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 537271116 60.68% 60.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23397088 2.64% 63.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25262126 2.85% 66.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27864383 3.15% 69.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17763945 2.01% 71.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22926561 2.59% 73.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29429676 3.32% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26640012 3.01% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174929524 19.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 885975121 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223861 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.232212 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222542151 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260234378 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295346908 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46930608 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60921076 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071264981 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 885484431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224249 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234328 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222585266 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 259638923 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295357907 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46951879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60950456 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071410922 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60921076 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256051169 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115707666 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18212 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306637897 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146639101 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035099231 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19841 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24966361 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106369922 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138037437 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150524594 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273371991 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 41733 # Number of floating rename lookups +system.cpu.rename.SquashCycles 60950456 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256114538 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114960463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17780 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306643544 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146797650 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035254884 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19108 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24985336 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106570240 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138126742 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150804980 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273565222 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40421 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523996583 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1255 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1189 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346554163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495859665 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194411587 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195293101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54696349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975355646 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13955 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772015968 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 483793 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441457587 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 735091170 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13403 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 885975121 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.000074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882925 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524085888 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1238 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346813798 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495843290 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194454992 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195400842 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54863800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975546158 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13200 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772179882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 484148 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441719386 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735183548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 885484431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.001368 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.882860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269258289 30.39% 30.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151881714 17.14% 47.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137407528 15.51% 63.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131753954 14.87% 77.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91677002 10.35% 88.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55986071 6.32% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34414851 3.88% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11835829 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1759883 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 268514596 30.32% 30.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 152316057 17.20% 47.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137257157 15.50% 63.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131678995 14.87% 77.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91673992 10.35% 88.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 56016548 6.33% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34412328 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11858214 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1756544 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 885975121 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 885484431 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4932504 32.46% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7653540 50.37% 82.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2609071 17.17% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4914226 32.32% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7684512 50.55% 82.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2604414 17.13% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2623104 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165669250 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353281 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880805 0.22% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 50 0.00% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2627261 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165804408 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352994 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880826 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 67 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.17% # Type of FU issued @@ -475,84 +451,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429265174 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170224304 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429279214 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170235112 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772015968 # Type of FU issued -system.cpu.iq.rate 1.929463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15195115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008575 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4445670799 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417030484 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744778187 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15166 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 51932 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3516 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784580890 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7089 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172585161 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772179882 # Type of FU issued +system.cpu.iq.rate 1.932895 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15203152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008579 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4445517936 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417485915 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744947174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 13559 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 50440 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3261 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784749273 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 6500 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172700004 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111758592 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 386790 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 327293 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45251401 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111742246 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 386565 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 329489 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45294806 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14735 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 596 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 14850 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 595 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60921076 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68026001 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7165661 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975369601 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 781836 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495860749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194411587 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4462926 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83952 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 327293 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5902213 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4423139 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10325352 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752891418 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424133385 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19124550 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60950456 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66921774 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7152270 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975559358 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 792714 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495844403 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194454992 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3102 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4466928 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83631 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 329489 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5907148 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4425214 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10332362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753055321 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424140880 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19124561 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590919865 # number of memory reference insts executed -system.cpu.iew.exec_branches 167459905 # Number of branches executed -system.cpu.iew.exec_stores 166786480 # Number of stores executed -system.cpu.iew.exec_rate 1.908639 # Inst execution rate -system.cpu.iew.wb_sent 1749637243 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744781703 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1324895228 # num instructions producing a value -system.cpu.iew.wb_consumers 1945542332 # num instructions consuming a value +system.cpu.iew.exec_refs 590933103 # number of memory reference insts executed +system.cpu.iew.exec_branches 167483673 # Number of branches executed +system.cpu.iew.exec_stores 166792223 # Number of stores executed +system.cpu.iew.exec_rate 1.912036 # Inst execution rate +system.cpu.iew.wb_sent 1749807321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744950435 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1324909698 # num instructions producing a value +system.cpu.iew.wb_consumers 1945755632 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899809 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680990 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903196 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680923 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446410033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446599399 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9933076 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825054045 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.853198 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435700 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9930890 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 824533975 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.854367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435928 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333030107 40.36% 40.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193187610 23.42% 63.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63292581 7.67% 71.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92556987 11.22% 82.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24936073 3.02% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27503514 3.33% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9360719 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11372840 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69813614 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 332362619 40.31% 40.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193345604 23.45% 63.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63386723 7.69% 71.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92493757 11.22% 82.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24926721 3.02% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27481357 3.33% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9323499 1.13% 90.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11375843 1.38% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69837852 8.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825054045 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 824533975 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -563,245 +539,245 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69813614 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69837852 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2730639165 # The number of ROB reads -system.cpu.rob.rob_writes 4011880242 # The number of ROB writes -system.cpu.timesIdled 3355901 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32423466 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2730284223 # The number of ROB reads +system.cpu.rob.rob_writes 4012285085 # The number of ROB writes +system.cpu.timesIdled 3361589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31368436 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.110683 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.110683 # CPI: Total CPI of All Threads -system.cpu.ipc 0.900347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.900347 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716194969 # number of integer regfile reads -system.cpu.int_regfile_writes 1420370160 # number of integer regfile writes -system.cpu.fp_regfile_reads 3538 # number of floating regfile reads -system.cpu.fp_regfile_writes 76 # number of floating regfile writes -system.cpu.cc_regfile_reads 597194910 # number of cc regfile reads -system.cpu.cc_regfile_writes 405402169 # number of cc regfile writes -system.cpu.misc_regfile_reads 964642327 # number of misc regfile reads +system.cpu.cpi 1.108814 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108814 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901865 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901865 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716343034 # number of integer regfile reads +system.cpu.int_regfile_writes 1420512883 # number of integer regfile writes +system.cpu.fp_regfile_reads 3304 # number of floating regfile reads +system.cpu.fp_regfile_writes 92 # number of floating regfile writes +system.cpu.cc_regfile_reads 597249207 # number of cc regfile reads +system.cpu.cc_regfile_writes 405429285 # number of cc regfile writes +system.cpu.misc_regfile_reads 964722506 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698022201 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1904986 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1904985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330749 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 135709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 135709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771688 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 149463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7670245 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7819708 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 436992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311346432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311783424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311783424 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8691584 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4905579957 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 699635153 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1908088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1908087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 138856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 138856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771730 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771730 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7676496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7829115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311344320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311781440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311781440 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8893312 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4908984370 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 214416742 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 219136241 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3952860716 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3952027365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5299 # number of replacements -system.cpu.icache.tags.tagsinuse 1035.961197 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161868793 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6888 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23500.115128 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5320 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.745275 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161872406 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6896 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23473.376740 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1035.961197 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.505840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.505840 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1589 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.745275 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1576 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1238 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.775879 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 324173234 # Number of tag accesses -system.cpu.icache.tags.data_accesses 324173234 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 161870665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161870665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161870665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161870665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161870665 # number of overall hits -system.cpu.icache.overall_hits::total 161870665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 144635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 144635 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 144635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 144635 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 144635 # number of overall misses -system.cpu.icache.overall_misses::total 144635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 939845985 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 939845985 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 939845985 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 939845985 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 939845985 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 939845985 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162015300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162015300 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162015300 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162015300 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162015300 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162015300 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000893 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000893 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000893 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000893 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000893 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000893 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6498.053618 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6498.053618 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6498.053618 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6498.053618 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6498.053618 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 238 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1228 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 324190030 # Number of tag accesses +system.cpu.icache.tags.data_accesses 324190030 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 161874355 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161874355 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161874355 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161874355 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161874355 # number of overall hits +system.cpu.icache.overall_hits::total 161874355 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 147766 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 147766 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 147766 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 147766 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 147766 # number of overall misses +system.cpu.icache.overall_misses::total 147766 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 941588486 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 941588486 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 941588486 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 941588486 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 941588486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 941588486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162022121 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162022121 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162022121 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162022121 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162022121 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162022121 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000912 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000912 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000912 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6372.159265 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6372.159265 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6372.159265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6372.159265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6372.159265 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.833333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 119.125000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2000 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2000 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2000 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2000 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2000 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2000 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 142635 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 142635 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 142635 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 142635 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 142635 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 142635 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558603007 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 558603007 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558603007 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 558603007 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558603007 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 558603007 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000880 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000880 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000880 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000880 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3916.310912 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3916.310912 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3916.310912 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3916.310912 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1977 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1977 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1977 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1977 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1977 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63548.844205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61384.997040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61402.720565 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293595 # number of writebacks +system.cpu.l2cache.writebacks::total 293595 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3147 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175643 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178790 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 137429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 137429 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206820 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1378003511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12022304022 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12022304022 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196679500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22520552977 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22717232477 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196679500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22520552977 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22717232477 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.460694 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101061 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989723 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989723 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.267995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.267995 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460694 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150931 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151764 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460694 # 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Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.243531 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998106 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998106 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2529933 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.224261 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395924693 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534029 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.243158 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1796857250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.224261 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998102 # 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number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 84885602977 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250160952 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250160952 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 800965525 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 800965525 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 247184750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247184750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148232864 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148232864 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395417614 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395417614 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395417614 # number of overall hits +system.cpu.dcache.overall_hits::total 395417614 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2870796 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2870796 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 927338 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 927338 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3798134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3798134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3798134 # number of overall misses +system.cpu.dcache.overall_misses::total 3798134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57044971459 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57044971459 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26405527365 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26405527365 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29037.108109 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22301.331575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22301.331575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22301.331575 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7238 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399215748 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399215748 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399215748 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399215748 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011481 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011481 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006217 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006217 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009514 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009514 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009514 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009514 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19870.785475 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19870.785475 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28474.544734 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28474.544734 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21971.446722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21971.446722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21971.446722 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6569 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 664 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 666 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.900602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.863363 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330749 # number of writebacks -system.cpu.dcache.writebacks::total 2330749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1119535 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1119535 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17020 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 17020 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136555 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136555 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136555 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136555 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762610 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762610 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 907137 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 907137 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2669747 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2669747 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2669747 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2669747 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30854243503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30854243503 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24711423781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 24711423781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55565667284 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 55565667284 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55565667284 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 55565667284 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007046 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006082 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006686 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006686 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.861259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.861259 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27241.115489 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27241.115489 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20813.083518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20813.083518 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330726 # number of writebacks +system.cpu.dcache.writebacks::total 2330726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1108238 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1108238 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17013 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17013 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1125251 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1125251 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1125251 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1125251 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 910325 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 910325 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2672883 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2672883 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2672883 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2672883 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30399879250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30399879250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24280652885 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24280652885 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54680532135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54680532135 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54680532135 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54680532135 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007049 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006103 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006103 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006695 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006695 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006695 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17247.590859 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17247.590859 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26672.510241 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26672.510241 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20457.510536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20457.510536 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index eb5995295..4b6099b52 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.139926 # Nu sim_ticks 139926186500 # Number of ticks simulated final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138827 # Simulator instruction rate (inst/s) -host_op_rate 138827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48726388 # Simulator tick rate (ticks/s) -host_mem_usage 236592 # Number of bytes of host memory used -host_seconds 2871.67 # Real time elapsed on the host +host_inst_rate 124689 # Simulator instruction rate (inst/s) +host_op_rate 124689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43764124 # Simulator tick rate (ticks/s) +host_mem_usage 271420 # Number of bytes of host memory used +host_seconds 3197.28 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,79 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.899833 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.568922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 772.018563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 419 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201 16.78% 51.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 128 10.68% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 91 7.60% 70.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 61 5.09% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 40 3.34% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 30 2.50% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 22 1.84% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 25 2.09% 84.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 18 1.50% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 20 1.67% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 8 0.67% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 17 1.42% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 10 0.83% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 8 0.67% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 6 0.50% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 10 0.83% 92.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.58% 93.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 7 0.58% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1 0.08% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 4 0.33% 94.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.33% 94.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 2 0.17% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 5 0.42% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 5 0.42% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.33% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.08% 96.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.17% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.08% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.17% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.08% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 96.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.08% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.17% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.08% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.08% 97.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 4 0.33% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 2 0.17% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 2 0.17% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.08% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.17% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.08% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.08% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.08% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.08% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 1 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 1 0.08% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.08% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.08% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.08% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1198 # Bytes accessed per row activation -system.physmem.totQLat 59880500 # Total ticks spent queuing -system.physmem.totMemAccLat 197624250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 480.917563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 280.270360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.877438 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 147 26.34% 26.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107 19.18% 45.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50 8.96% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28 5.02% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 2.69% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.69% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.25% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 0.90% 67.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 32.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 558 # Bytes accessed per row activation +system.physmem.totQLat 59527000 # Total ticks spent queuing +system.physmem.totMemAccLat 199924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers -system.physmem.totBankLat 101103750 # Total ticks spent accessing banks -system.physmem.avgQLat 8171.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13796.91 # Average bank access latency per DRAM burst +system.physmem.totBankLat 103757500 # Total ticks spent accessing banks +system.physmem.avgQLat 8123.23 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14159.05 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26968.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27282.27 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s @@ -235,15 +216,15 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6130 # Number of row buffer hits during reads +system.physmem.readRowHits 5962 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 19094720.66 # Average gap between requests -system.physmem.pageHitRate 83.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.42 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.43 # Percentage of time for which DRAM has all the banks in precharge state system.membus.throughput 3351710 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 4183 # Transaction distribution system.membus.trans_dist::ReadResp 4183 # Transaction distribution @@ -257,7 +238,7 @@ system.membus.data_through_bus 468992 # To system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 8743500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 68133000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 53489673 # Number of BP lookups @@ -273,22 +254,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754637 # DTB read hits +system.cpu.dtb.read_hits 94754639 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754658 # DTB read accesses -system.cpu.dtb.write_hits 73521124 # DTB write hits +system.cpu.dtb.read_accesses 94754660 # DTB read accesses +system.cpu.dtb.write_hits 73521131 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521159 # DTB write accesses -system.cpu.dtb.data_hits 168275761 # DTB hits +system.cpu.dtb.write_accesses 73521166 # DTB write accesses +system.cpu.dtb.data_hits 168275770 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275817 # DTB accesses -system.cpu.itb.fetch_hits 48611324 # ITB hits +system.cpu.dtb.data_accesses 168275826 # DTB accesses +system.cpu.itb.fetch_hits 48611322 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655844 # ITB accesses +system.cpu.itb.fetch_accesses 48655842 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -307,13 +288,13 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 24259168 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386579 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 280386572 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722438 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631950 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722431 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828431 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484574 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484576 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -324,12 +305,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400617 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279400810 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13545708 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306666 # Number of cycles cpu stages are processed. -system.cpu.activity 95.159695 # Percentage of cycles cpu is active +system.cpu.timesIdled 7266 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13545705 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306669 # Number of cycles cpu stages are processed. +system.cpu.activity 95.159696 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -350,27 +331,27 @@ system.cpu.ipc_total 1.424553 # IP system.cpu.stage0.idleCycles 78104700 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 201747674 # Number of cycles 1+ instructions are processed. system.cpu.stage0.utilization 72.090750 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107200641 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651733 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.693860 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107200637 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651737 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.693862 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 102637143 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 177215231 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 63.324541 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 181107759 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744615 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.284537 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90384394 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467980 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.702831 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181107747 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744627 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.284541 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90384400 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467974 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.702829 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1975 # number of replacements -system.cpu.icache.tags.tagsinuse 1830.939408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 48606790 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1830.934233 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 48606787 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12453.699718 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12453.698950 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1830.934233 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894011 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894011 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id @@ -378,44 +359,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 322 system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606790 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606790 # number of overall hits -system.cpu.icache.overall_hits::total 48606790 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4534 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4534 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4534 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4534 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4534 # number of overall misses -system.cpu.icache.overall_misses::total 4534 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 280061250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 280061250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 280061250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 280061250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 280061250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611324 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611324 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611324 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611324 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611324 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 97226547 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226547 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 48606787 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606787 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606787 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606787 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606787 # number of overall hits +system.cpu.icache.overall_hits::total 48606787 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4535 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4535 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4535 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4535 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4535 # number of overall misses +system.cpu.icache.overall_misses::total 4535 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 279787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 279787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 279787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 279787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 279787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611322 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611322 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611322 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611322 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611322 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61769.133216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61769.133216 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61769.133216 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61769.133216 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61695.093716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61695.093716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61695.093716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61695.093716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -424,36 +405,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 110 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 631 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 631 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 631 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 631 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 631 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 632 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 632 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 632 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 632 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 632 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 632 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 244179750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 244179750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 244179750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 244179750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 243875500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 243875500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243875500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 243875500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62562.067640 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62562.067640 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62562.067640 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62484.114783 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62484.114783 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62484.114783 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.throughput 3981070 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution @@ -471,21 +452,21 @@ system.cpu.toL2Bus.data_through_bus 557056 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6459750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6445500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6671999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6649999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3906.845611 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3906.832917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 370.534640 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.739390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571581 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 370.533355 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.730052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 627.569510 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088767 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id @@ -520,17 +501,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234790750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 62080250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 296871000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 227075250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234790750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 289155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 523946250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234790750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 289155500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 523946250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 234486500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61133000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 295619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 230289500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 234486500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 291422500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 525909000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 234486500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 291422500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 525909000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -555,17 +536,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69899.002679 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75340.109223 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70970.834329 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72201.987281 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71499.215338 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69899.002679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72853.489544 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71499.215338 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69808.425127 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74190.533981 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70671.647143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73224.006359 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71767.057860 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69808.425127 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73424.666163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71767.057860 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -585,17 +566,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192686250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51812250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 244498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 188269250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192686250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 240081500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 432767750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192686250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 240081500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 432767750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 192420000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50867000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 243287000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 191492500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192420000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 242359500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 434779500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192420000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 242359500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 434779500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -607,27 +588,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57364.170884 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62878.944175 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58450.513985 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59863.036566 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57364.170884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60489.166037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59056.734443 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57284.906222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61731.796117 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58160.889314 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60887.917329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57284.906222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61063.114135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59331.263646 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3284.890275 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168254255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3284.879976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168254239 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40523.664499 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40523.660645 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3284.879976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.801973 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.801973 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -639,28 +620,28 @@ system.cpu.dcache.tags.tag_accesses 336554588 # Nu system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501074 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254255 # number of overall hits -system.cpu.dcache.overall_hits::total 168254255 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254239 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254239 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254239 # number of overall hits +system.cpu.dcache.overall_hits::total 168254239 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19655 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19655 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20963 # number of overall misses -system.cpu.dcache.overall_misses::total 20963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88453749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88453749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1129220750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1217674499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1217674499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1217674499 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20979 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20979 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20979 # number of overall misses +system.cpu.dcache.overall_misses::total 20979 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87087749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87087749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1166784250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1253871999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1253871999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1253871999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -671,25 +652,25 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67625.190367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67625.190367 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57452.085983 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57452.085983 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 58086.843438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 58086.843438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33688 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66580.847859 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66580.847859 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59314.943318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59314.943318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59767.958387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59767.958387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33117 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 584 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 591 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.684932 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.035533 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -697,12 +678,12 @@ system.cpu.dcache.writebacks::writebacks 649 # nu system.cpu.dcache.writebacks::total 649 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16453 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16453 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16811 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16811 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16811 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16469 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16469 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16827 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16827 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16827 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -711,14 +692,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64535001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 230815000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 295350001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 295350001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 295350001 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63587751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 234030250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 297618001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 297618001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 297618001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -727,14 +708,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67931.580000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72084.634603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71134.393304 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71134.393304 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66934.474737 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73088.772642 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71680.636079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71680.636079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 39e558e65..8d6cbc006 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077516 # Number of seconds simulated -sim_ticks 77516381000 # Number of ticks simulated -final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077418 # Number of seconds simulated +sim_ticks 77417500000 # Number of ticks simulated +final_tick 77417500000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222910 # Simulator instruction rate (inst/s) -host_op_rate 222910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46007212 # Simulator tick rate (ticks/s) -host_mem_usage 236600 # Number of bytes of host memory used -host_seconds 1684.87 # Real time elapsed on the host +host_inst_rate 187521 # Simulator instruction rate (inst/s) +host_op_rate 187521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38653802 # Simulator tick rate (ticks/s) +host_mem_usage 273448 # Number of bytes of host memory used +host_seconds 2002.84 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory -system.physmem.bytes_read::total 476608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221184 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3991 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7447 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2853384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3295097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6148481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2853384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2853384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3295097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6148481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7447 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255488 # Number of bytes read from this memory +system.physmem.bytes_read::total 476480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2854548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3300132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6154681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2854548 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2854548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3300132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6154681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7447 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476608 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 476480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476608 # Total read bytes from the system interface side +system.physmem.bytesReadSys 476480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::1 654 # Per bank write bursts system.physmem.perBankRdBursts::2 449 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 447 # Per bank write bursts system.physmem.perBankRdBursts::5 455 # Per bank write bursts -system.physmem.perBankRdBursts::6 515 # Per bank write bursts +system.physmem.perBankRdBursts::6 518 # Per bank write bursts system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 407 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::8 436 # Per bank write bursts +system.physmem.perBankRdBursts::9 405 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 306 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 453 # Per bank write bursts +system.physmem.perBankRdBursts::13 541 # Per bank write bursts +system.physmem.perBankRdBursts::14 454 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 77516291500 # Total gap between requests +system.physmem.totGap 77417410500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7447 # Read request sizes (log2) +system.physmem.readPktSize::6 7445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 735 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,72 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.618557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.969320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 801.678722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 417 35.82% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 184 15.81% 51.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 111 9.54% 61.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 97 8.33% 69.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 49 4.21% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 3.26% 76.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 28 2.41% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 28 2.41% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 22 1.89% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 22 1.89% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 9 0.77% 86.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.12% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 15 1.29% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 15 1.29% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.52% 90.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.60% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 16 1.37% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 3 0.26% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.43% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.17% 93.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 3 0.26% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 11 0.95% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.34% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.52% 95.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.26% 95.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 4 0.34% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.26% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 3 0.26% 96.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.26% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 3 0.26% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 2 0.17% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 5 0.43% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.09% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.09% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 2 0.17% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.09% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.09% 98.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.09% 98.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 2 0.17% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 2 0.17% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.09% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.09% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.09% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.17% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.09% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.09% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.09% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.09% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.09% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.09% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.09% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.09% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 3 0.26% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1164 # Bytes accessed per row activation -system.physmem.totQLat 59914250 # Total ticks spent queuing -system.physmem.totMemAccLat 199861750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37235000 # Total ticks spent in databus transfers -system.physmem.totBankLat 102712500 # Total ticks spent accessing banks -system.physmem.avgQLat 8045.42 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13792.47 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 457.157393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 257.861215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.549348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 187 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 122 19.40% 49.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53 8.43% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24 3.82% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18 2.86% 64.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 2.38% 66.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 1.11% 67.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.48% 68.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 200 31.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 629 # Bytes accessed per row activation +system.physmem.totQLat 62316500 # Total ticks spent queuing +system.physmem.totMemAccLat 205595250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37225000 # Total ticks spent in databus transfers +system.physmem.totBankLat 106053750 # Total ticks spent accessing banks +system.physmem.avgQLat 8370.25 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14244.96 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26837.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27615.21 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.15 # Average system read bandwidth in MiByte/s @@ -228,60 +216,60 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6283 # Number of row buffer hits during reads +system.physmem.readRowHits 6071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.37 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10409062.91 # Average gap between requests -system.physmem.pageHitRate 84.37 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.56 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6148481 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4317 # Transaction distribution -system.membus.trans_dist::ReadResp 4317 # Transaction distribution -system.membus.trans_dist::ReadExReq 3130 # Transaction distribution -system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14894 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 476608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 476608 # Total data (bytes) +system.physmem.avgGap 10398577.64 # Average gap between requests +system.physmem.pageHitRate 81.54 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6154681 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4313 # Transaction distribution +system.membus.trans_dist::ReadResp 4313 # Transaction distribution +system.membus.trans_dist::ReadExReq 3132 # Transaction distribution +system.membus.trans_dist::ReadExResp 3132 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14890 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14890 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 476480 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476480 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 9290500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9329500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 69519750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 50307155 # Number of BP lookups -system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26317352 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23268236 # Number of BTB hits +system.cpu.branchPred.lookups 50246060 # Number of BP lookups +system.cpu.branchPred.condPredicted 29233966 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1199560 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25853120 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23225371 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.414047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9019862 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1049 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.835853 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9012456 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1102 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101828804 # DTB read hits -system.cpu.dtb.read_misses 77910 # DTB read misses -system.cpu.dtb.read_acv 48604 # DTB read access violations -system.cpu.dtb.read_accesses 101906714 # DTB read accesses -system.cpu.dtb.write_hits 78465960 # DTB write hits -system.cpu.dtb.write_misses 1494 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 78467454 # DTB write accesses -system.cpu.dtb.data_hits 180294764 # DTB hits -system.cpu.dtb.data_misses 79404 # DTB misses -system.cpu.dtb.data_acv 48608 # DTB access violations -system.cpu.dtb.data_accesses 180374168 # DTB accesses -system.cpu.itb.fetch_hits 50297233 # ITB hits -system.cpu.itb.fetch_misses 369 # ITB misses +system.cpu.dtb.read_hits 101798719 # DTB read hits +system.cpu.dtb.read_misses 78049 # DTB read misses +system.cpu.dtb.read_acv 48607 # DTB read access violations +system.cpu.dtb.read_accesses 101876768 # DTB read accesses +system.cpu.dtb.write_hits 78433341 # DTB write hits +system.cpu.dtb.write_misses 1499 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 78434840 # DTB write accesses +system.cpu.dtb.data_hits 180232060 # DTB hits +system.cpu.dtb.data_misses 79548 # DTB misses +system.cpu.dtb.data_acv 48609 # DTB access violations +system.cpu.dtb.data_accesses 180311608 # DTB accesses +system.cpu.itb.fetch_hits 50221171 # ITB hits +system.cpu.itb.fetch_misses 373 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50297602 # ITB accesses +system.cpu.itb.fetch_accesses 50221544 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -295,105 +283,105 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 155032764 # number of cpu cycles simulated +system.cpu.numCycles 154835002 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51194259 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 449183474 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50307155 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32288098 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78871433 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6172161 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19742008 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 181 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 10560 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 51111974 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448661331 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50246060 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32237827 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78769244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6113875 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19767092 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10735 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50297233 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 412894 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.902843 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324835 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 50221171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 406319 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.903307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325117 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75867718 49.03% 49.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4287409 2.77% 51.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6889018 4.45% 56.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5374428 3.47% 59.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11763624 7.60% 67.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7816659 5.05% 72.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5616009 3.63% 76.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1833388 1.18% 77.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35290898 22.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75765354 49.03% 49.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4278797 2.77% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6878880 4.45% 56.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5365294 3.47% 59.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11742013 7.60% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7808130 5.05% 72.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5610858 3.63% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1827134 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258138 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154739151 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324494 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.897345 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56553436 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15088868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74238964 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3941383 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4916500 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9487386 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4275 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 445247195 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12161 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4916500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59699528 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4890372 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 419538 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75126102 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9687111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440708166 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 170 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18989 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8005915 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287519835 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579387338 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 414037453 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 165349884 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154534598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324514 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.897674 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56469798 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15107857 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74141890 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3943911 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4871142 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9469846 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4291 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444777840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4871142 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59608441 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4896661 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 418311 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75037002 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9703041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440308504 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 162 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18256 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8013879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287257669 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578877349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 413693152 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165184196 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27987506 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36934 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 290 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27862892 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104720393 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80633883 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8938676 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6410471 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408405086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401961016 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 974295 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32695397 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15321612 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154739151 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.597668 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996651 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27725340 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36879 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 302 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27905569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104673865 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80579462 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8919028 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6395315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408114726 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401714158 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 971094 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32406044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15222181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154534598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.599510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995704 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28425455 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25900888 16.74% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25580333 16.53% 51.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24228882 15.66% 67.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21279905 13.75% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15505585 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8490760 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3998033 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1329310 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28287072 18.30% 18.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25862273 16.74% 35.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25616970 16.58% 51.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24199972 15.66% 67.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21258651 13.76% 81.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15520360 10.04% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8472156 5.48% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3988463 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1328681 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154739151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154534598 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 33873 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 33844 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 57850 0.49% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5381 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1948507 16.46% 17.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748153 14.77% 32.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57389 0.49% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 4757 0.04% 0.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5293 0.04% 0.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1937864 16.39% 17.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1755771 14.85% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.09% # attempts to use FU when none available @@ -415,118 +403,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.09% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5077908 42.90% 74.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2960216 25.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5068587 42.87% 74.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960872 25.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155836212 38.77% 38.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126206 0.53% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32826139 8.17% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7503461 1.87% 49.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2792900 0.69% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16557877 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1579224 0.39% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103415841 25.73% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79289575 19.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155710180 38.76% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126250 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32800446 8.17% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7495713 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793863 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555604 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1576822 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103379318 25.73% 80.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79242381 19.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401961016 # Type of FU issued -system.cpu.iq.rate 2.592749 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11837271 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029449 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 634505774 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260497209 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234812479 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336966975 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180652533 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161419314 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241576222 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172188484 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15052407 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401714158 # Type of FU issued +system.cpu.iq.rate 2.594466 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11824377 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029435 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633974130 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260128925 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234699525 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336784255 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180440959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161353653 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241409796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172095158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15058802 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9965906 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 111384 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 48996 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7113154 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9919378 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112340 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 48844 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7058733 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260897 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3921 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260875 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3830 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4916500 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2514816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370985 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 433209224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104720393 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80633883 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 279 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 76 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 48996 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 956631 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 408580 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1365211 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398393230 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101955347 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3567786 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4871142 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2518143 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 371002 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432897365 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 126094 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104673865 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80579462 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 87 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 80 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 48844 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 943634 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 406077 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1349711 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398212292 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101925424 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3501866 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24803859 # number of nop insts executed -system.cpu.iew.exec_refs 180422830 # number of memory reference insts executed -system.cpu.iew.exec_branches 46575028 # Number of branches executed -system.cpu.iew.exec_stores 78467483 # Number of stores executed -system.cpu.iew.exec_rate 2.569736 # Inst execution rate -system.cpu.iew.wb_sent 396861814 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396231793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193564452 # num instructions producing a value -system.cpu.iew.wb_consumers 271143010 # num instructions consuming a value +system.cpu.iew.exec_nop 24782349 # number of nop insts executed +system.cpu.iew.exec_refs 180360292 # number of memory reference insts executed +system.cpu.iew.exec_branches 46546611 # Number of branches executed +system.cpu.iew.exec_stores 78434868 # Number of stores executed +system.cpu.iew.exec_rate 2.571849 # Inst execution rate +system.cpu.iew.wb_sent 396683492 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396053178 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193508627 # num instructions producing a value +system.cpu.iew.wb_consumers 271030051 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.555794 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713883 # average fanout of values written-back +system.cpu.iew.wb_rate 2.557905 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713975 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34575269 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34263124 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149822651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.660910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.995203 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1195351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149663456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.663740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.995900 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55444795 37.01% 37.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22572345 15.07% 52.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13039783 8.70% 60.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11474023 7.66% 68.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8200661 5.47% 73.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5438800 3.63% 77.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5171862 3.45% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3280269 2.19% 83.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25200113 16.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55327244 36.97% 36.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22535122 15.06% 52.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13022576 8.70% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11475094 7.67% 68.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8197799 5.48% 73.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5452875 3.64% 77.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5172237 3.46% 80.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3274038 2.19% 83.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25206471 16.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149822651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149663456 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,228 +525,228 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25200113 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25206471 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557859413 # The number of ROB reads -system.cpu.rob.rob_writes 871404727 # The number of ROB writes -system.cpu.timesIdled 3579 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293613 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557381715 # The number of ROB reads +system.cpu.rob.rob_writes 870735186 # The number of ROB writes +system.cpu.timesIdled 3600 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 300404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.412788 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.412788 # CPI: Total CPI of All Threads -system.cpu.ipc 2.422551 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.422551 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398219851 # number of integer regfile reads -system.cpu.int_regfile_writes 170183531 # number of integer regfile writes -system.cpu.fp_regfile_reads 156589680 # number of floating regfile reads -system.cpu.fp_regfile_writes 104065109 # number of floating regfile writes +system.cpu.cpi 0.412261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.412261 # CPI: Total CPI of All Threads +system.cpu.ipc 2.425645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.425645 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 398046268 # number of integer regfile reads +system.cpu.int_regfile_writes 170097469 # number of integer regfile writes +system.cpu.fp_regfile_reads 156518592 # number of floating regfile reads +system.cpu.fp_regfile_writes 104028166 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 7356381 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 659 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3190 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17161 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 570240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 570240 # Total data (bytes) +system.cpu.toL2Bus.throughput 7364950 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 661 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3193 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8124 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9033 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 570176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 570176 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5114000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 5115500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6775000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6740250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6675000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6663250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2141 # number of replacements -system.cpu.icache.tags.tagsinuse 1831.580097 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 50291612 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4069 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12359.698206 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2135 # number of replacements +system.cpu.icache.tags.tagsinuse 1832.551439 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 50215552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4062 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12362.272772 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 336 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1334 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 100598535 # Number of tag accesses -system.cpu.icache.tags.data_accesses 100598535 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50291612 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50291612 # number of overall hits -system.cpu.icache.overall_hits::total 50291612 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses -system.cpu.icache.overall_misses::total 5621 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 330634250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 330634250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 330634250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 330634250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 330634250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 330634250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50297233 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50297233 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50297233 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50297233 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50297233 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50297233 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1832.551439 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894801 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894801 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1346 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 100446404 # Number of tag accesses +system.cpu.icache.tags.data_accesses 100446404 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 50215552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50215552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50215552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50215552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50215552 # number of overall hits +system.cpu.icache.overall_hits::total 50215552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5619 # number of overall misses +system.cpu.icache.overall_misses::total 5619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 332785750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 332785750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 332785750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 332785750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 332785750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 332785750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50221171 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50221171 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50221171 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50221171 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50221171 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58821.250667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58821.250667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58821.250667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58821.250667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58821.250667 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 892 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59225.084535 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59225.084535 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59225.084535 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59225.084535 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 251 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 148.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 83.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1552 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1552 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1552 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1552 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1552 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1552 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4069 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4069 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4069 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4069 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4069 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4069 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 249126500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 249126500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249126500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 249126500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1557 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1557 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1557 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1557 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1557 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4062 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4062 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4062 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4062 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4062 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 250275250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 250275250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250275250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 250275250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61225.485377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61225.485377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61225.485377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61225.485377 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61613.798621 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61613.798621 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61613.798621 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61613.798621 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61613.798621 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61613.798621 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4006.698259 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 830 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4855 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.170958 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4014.912123 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 831 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4850 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.171340 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.850074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866062 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.853215 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980896 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980896 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953655 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.902643 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850074 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953655 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.902643 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56866.058500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65395.058140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58566.716902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61083.014049 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61083.014049 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56866.058500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62011.961423 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59625.285426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56866.058500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62011.961423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59625.285426 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 780 # number of replacements -system.cpu.dcache.tags.tagsinuse 3295.992263 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 160011153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4182 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38261.873027 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 784 # number of replacements +system.cpu.dcache.tags.tagsinuse 3296.614513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 159974752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4186 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38216.615385 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3295.992263 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804686 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3296.614513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804838 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804838 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3118 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 320069754 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 320069754 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86510267 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86510267 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500882 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500882 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 160011149 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 160011149 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 160011149 # number of overall hits -system.cpu.dcache.overall_hits::total 160011149 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1786 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1786 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19847 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19847 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21633 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21633 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21633 # number of overall misses -system.cpu.dcache.overall_misses::total 21633 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114228250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114228250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1085833087 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1085833087 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1200061337 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1200061337 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1200061337 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1200061337 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86512053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86512053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 319997054 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 319997054 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86473896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86473896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73500850 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73500850 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 159974746 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159974746 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159974746 # number of overall hits +system.cpu.dcache.overall_hits::total 159974746 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1803 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1803 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19879 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19879 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21682 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21682 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21682 # number of overall misses +system.cpu.dcache.overall_misses::total 21682 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 116178750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 116178750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1100405079 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1216583829 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1216583829 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1216583829 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86475699 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86475699 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 160032782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 160032782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 160032782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 160032782 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 159996428 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159996428 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159996428 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159996428 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000270 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63957.586786 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63957.586786 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54710.187283 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54710.187283 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55473.643831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55473.643831 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 40366 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64436.356073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64436.356073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55355.152623 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55355.152623 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56110.314039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56110.314039 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 40445 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 653 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.816233 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60.365672 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 659 # number of writebacks -system.cpu.dcache.writebacks::total 659 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 794 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16657 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16657 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 992 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 992 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3190 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 68767000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 229720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298487000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298487000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298487000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 661 # number of writebacks +system.cpu.dcache.writebacks::total 661 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 810 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 810 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16686 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16686 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17496 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17496 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17496 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 993 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 993 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3193 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3193 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4186 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4186 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4186 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 69211250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 233753500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 302964750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 302964750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 302964750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -924,14 +912,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69321.572581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72012.539185 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71374.222860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71374.222860 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69699.144008 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73208.111494 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72375.716675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72375.716675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 634fe5f9a..648c5ea6f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068504 # Number of seconds simulated -sim_ticks 68503867000 # Number of ticks simulated -final_tick 68503867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068245 # Number of seconds simulated +sim_ticks 68245472000 # Number of ticks simulated +final_tick 68245472000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147835 # Simulator instruction rate (inst/s) -host_op_rate 189000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37091215 # Simulator tick rate (ticks/s) -host_mem_usage 278164 # Number of bytes of host memory used -host_seconds 1846.90 # Real time elapsed on the host +host_inst_rate 123424 # Simulator instruction rate (inst/s) +host_op_rate 157791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30849723 # Simulator tick rate (ticks/s) +host_mem_usage 321440 # Number of bytes of host memory used +host_seconds 2212.19 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 193984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272256 # Number of bytes read from this memory -system.physmem.bytes_read::total 466240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193984 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4254 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7285 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2831723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3974316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6806039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2831723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2831723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3974316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6806039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7286 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory +system.physmem.bytes_read::total 466368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7287 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2839632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3994053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6833684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2839632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2839632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3994053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6833684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7288 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7286 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7288 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 466304 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 466432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 466304 # Total read bytes from the system interface side +system.physmem.bytesReadSys 466432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 606 # Per bank write bursts -system.physmem.perBankRdBursts::1 800 # Per bank write bursts +system.physmem.perBankRdBursts::1 802 # Per bank write bursts system.physmem.perBankRdBursts::2 608 # Per bank write bursts system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 443 # Per bank write bursts -system.physmem.perBankRdBursts::5 354 # Per bank write bursts -system.physmem.perBankRdBursts::6 164 # Per bank write bursts -system.physmem.perBankRdBursts::7 219 # Per bank write bursts -system.physmem.perBankRdBursts::8 207 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 322 # Per bank write bursts -system.physmem.perBankRdBursts::11 415 # Per bank write bursts -system.physmem.perBankRdBursts::12 529 # Per bank write bursts +system.physmem.perBankRdBursts::4 441 # Per bank write bursts +system.physmem.perBankRdBursts::5 356 # Per bank write bursts +system.physmem.perBankRdBursts::6 162 # Per bank write bursts +system.physmem.perBankRdBursts::7 220 # Per bank write bursts +system.physmem.perBankRdBursts::8 205 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 324 # Per bank write bursts +system.physmem.perBankRdBursts::11 417 # Per bank write bursts +system.physmem.perBankRdBursts::12 531 # Per bank write bursts system.physmem.perBankRdBursts::13 687 # Per bank write bursts system.physmem.perBankRdBursts::14 611 # Per bank write bursts -system.physmem.perBankRdBursts::15 504 # Per bank write bursts +system.physmem.perBankRdBursts::15 502 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 68503846500 # Total gap between requests +system.physmem.totGap 68245446000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7286 # Read request sizes (log2) +system.physmem.readPktSize::6 7288 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -154,124 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 361.604977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.647663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 753.981601 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 537 41.76% 41.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 220 17.11% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 131 10.19% 69.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 77 5.99% 75.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 39 3.03% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 38 2.95% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 26 2.02% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 31 2.41% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 1.32% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 23 1.79% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 6 0.47% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 1.24% 90.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 3 0.23% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 0.62% 91.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 7 0.54% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 7 0.54% 92.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 5 0.39% 92.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 8 0.62% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 5 0.39% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.47% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.08% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 4 0.31% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 4 0.31% 94.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 6 0.47% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 3 0.23% 95.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 3 0.23% 95.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 3 0.23% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 4 0.31% 96.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 2 0.16% 96.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.23% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 2 0.16% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 4 0.31% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 2 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.08% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 1 0.08% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 2 0.16% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 1 0.08% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 1 0.08% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.08% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.08% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.08% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.16% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.08% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 2 0.16% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 1 0.08% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 1 0.08% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.08% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.08% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 2 0.16% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.08% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 1 0.08% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.08% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.08% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.08% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.23% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 1 0.08% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.08% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.08% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.08% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.08% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 2 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1286 # Bytes accessed per row activation -system.physmem.totQLat 62980000 # Total ticks spent queuing -system.physmem.totMemAccLat 198080000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36430000 # Total ticks spent in databus transfers -system.physmem.totBankLat 98670000 # Total ticks spent accessing banks -system.physmem.avgQLat 8643.97 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13542.41 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 479.779310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.986956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 421.744260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 159 27.41% 27.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 117 20.17% 47.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45 7.76% 55.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23 3.97% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14 2.41% 61.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13 2.24% 63.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 1.03% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.34% 65.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 201 34.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 580 # Bytes accessed per row activation +system.physmem.totQLat 57907000 # Total ticks spent queuing +system.physmem.totMemAccLat 195684500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36440000 # Total ticks spent in databus transfers +system.physmem.totBankLat 101337500 # Total ticks spent accessing banks +system.physmem.avgQLat 7945.53 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13904.71 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27186.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26850.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.83 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6000 # Number of row buffer hits during reads +system.physmem.readRowHits 5839 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9402120.02 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.05 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 6806039 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 4462 # Transaction distribution -system.membus.trans_dist::ReadResp 4461 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 2824 # Transaction distribution -system.membus.trans_dist::ReadExResp 2824 # Transaction distribution +system.physmem.avgGap 9364084.25 # Average gap between requests +system.physmem.pageHitRate 80.12 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.16 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 6833684 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4468 # Transaction distribution +system.membus.trans_dist::ReadResp 4467 # Transaction distribution +system.membus.trans_dist::ReadExReq 2820 # Transaction distribution +system.membus.trans_dist::ReadExResp 2820 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14575 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 14575 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 466240 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 466240 # Total data (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 466368 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466368 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 8931500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8915000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 67747998 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 67732500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 35407535 # Number of BP lookups -system.cpu.branchPred.condPredicted 21210003 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1658535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19582924 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16814113 # Number of BTB hits +system.cpu.branchPred.lookups 35342667 # Number of BP lookups +system.cpu.branchPred.condPredicted 21189046 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1621967 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18355176 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16729462 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.861095 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6780652 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8453 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.143021 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6774978 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8404 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -357,100 +335,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 137007735 # number of cpu cycles simulated +system.cpu.numCycles 136490945 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38995510 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317974758 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35407535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23594765 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70934448 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6878177 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21511393 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 109 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1738 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 61 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37596145 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 512137 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.983546 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38825213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317051968 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35342667 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23504440 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70679896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6716000 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21545367 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 106 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37451719 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 502899 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.985255 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66349844 48.55% 48.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6791529 4.97% 53.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5702360 4.17% 57.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6103499 4.47% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4918940 3.60% 65.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4085838 2.99% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3180821 2.33% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4138782 3.03% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35379651 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66077496 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6747770 4.96% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5691244 4.18% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6070617 4.46% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4899295 3.60% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4080163 3.00% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3177720 2.33% 71.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4131471 3.03% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35258659 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136651264 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258435 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.320853 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513422 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16662187 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66798256 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2538078 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5139321 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7340905 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69056 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401756741 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 208904 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5139321 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 51060721 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1905439 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 332675 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63727748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14485360 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 394162913 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1657895 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10187119 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 22377 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432668253 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2737675688 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1575239963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 200387111 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136134435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258938 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.322879 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45319095 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16701200 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66547822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2552537 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5013781 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7320658 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69067 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400437341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 211449 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5013781 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50843684 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1928767 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 335631 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63516277 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14496295 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 392925979 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 32 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1658279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10203172 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 22306 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431444746 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2730832248 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1570013245 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200164445 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 48102060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11946 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11945 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36528458 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103595819 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91394334 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4295156 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5297473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384542604 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22919 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374214780 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1210476 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34753044 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 100302329 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136651264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.738466 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.024544 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 46878553 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11940 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11939 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36493417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103352368 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91160183 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4261604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5303451 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383671023 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22900 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373754233 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1199031 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33881433 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 97712598 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 780 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136134435 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.745479 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022556 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 25105050 18.37% 18.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19938594 14.59% 32.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20566375 15.05% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18171632 13.30% 61.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028761 17.58% 78.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15737538 11.52% 90.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8814188 6.45% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3372330 2.47% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 916796 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24740289 18.17% 18.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19905513 14.62% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20515084 15.07% 47.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18158642 13.34% 61.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24030824 17.65% 78.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15691878 11.53% 90.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8802431 6.47% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3372838 2.48% 99.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 916936 0.67% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136651264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136134435 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8713 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8938 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4692 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -469,127 +447,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46317 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46049 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 3518 0.02% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 440 0.00% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 3482 0.02% 0.36% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.36% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 186929 1.05% 1.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4248 0.02% 1.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241299 1.36% 2.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 186470 1.05% 1.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3938 0.02% 1.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241178 1.36% 2.80% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9275439 52.33% 55.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7953254 44.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9277159 52.37% 55.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7942822 44.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126461637 33.79% 33.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175765 0.58% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6779975 1.81% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8474577 2.26% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3430301 0.92% 39.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595259 0.43% 39.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20865413 5.58% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7172902 1.92% 47.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7130224 1.91% 49.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101650995 27.16% 76.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88302442 23.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126226981 33.77% 33.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175715 0.58% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 4 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6775957 1.81% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8464752 2.26% 38.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3426733 0.92% 39.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595441 0.43% 39.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20845390 5.58% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7170609 1.92% 47.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125607 1.91% 49.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101514689 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88257068 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374214780 # Type of FU issued -system.cpu.iq.rate 2.731341 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17724852 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654627146 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288999508 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250114053 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249389006 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130333197 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118063719 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263337797 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128601835 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11086522 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373754233 # Type of FU issued +system.cpu.iq.rate 2.738308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17715164 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047398 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653197592 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287339977 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249810515 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249359504 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130249499 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118015221 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 262881293 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128588104 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11104968 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8947071 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 108758 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14277 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9018751 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8703620 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109542 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14223 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8784600 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 174712 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1900 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184473 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1790 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5139321 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 272764 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 35129 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384567184 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 874047 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103595819 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91394334 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11885 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 280 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14277 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1299093 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 369514 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1668607 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370257441 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100364532 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3957339 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5013781 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 291002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36408 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383695470 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 852736 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103352368 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91160183 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11866 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 327 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 282 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14223 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1256888 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 362770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1619658 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369836414 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100211998 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3917819 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1661 # number of nop insts executed -system.cpu.iew.exec_refs 187583075 # number of memory reference insts executed -system.cpu.iew.exec_branches 32009347 # Number of branches executed -system.cpu.iew.exec_stores 87218543 # Number of stores executed -system.cpu.iew.exec_rate 2.702456 # Inst execution rate -system.cpu.iew.wb_sent 368846220 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368177772 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183055174 # num instructions producing a value -system.cpu.iew.wb_consumers 363803620 # num instructions consuming a value +system.cpu.iew.exec_nop 1547 # number of nop insts executed +system.cpu.iew.exec_refs 187429987 # number of memory reference insts executed +system.cpu.iew.exec_branches 31988466 # Number of branches executed +system.cpu.iew.exec_stores 87217989 # Number of stores executed +system.cpu.iew.exec_rate 2.709604 # Inst execution rate +system.cpu.iew.wb_sent 368475660 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367825736 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182824140 # num instructions producing a value +system.cpu.iew.wb_consumers 363330392 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.687277 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503170 # average fanout of values written-back +system.cpu.iew.wb_rate 2.694873 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503190 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35502239 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34630475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1589851 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131511943 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.654246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.658719 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1553283 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131120654 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.662167 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659302 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34696225 26.38% 26.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28452590 21.63% 48.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13345612 10.15% 58.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11442919 8.70% 66.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13780020 10.48% 77.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7417113 5.64% 82.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3869989 2.94% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3892889 2.96% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14614586 11.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34358811 26.20% 26.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28410916 21.67% 47.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13299289 10.14% 58.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11469684 8.75% 66.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13783827 10.51% 77.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7406623 5.65% 82.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3875247 2.96% 85.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3903446 2.98% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14612811 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131511943 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131120654 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,238 +578,230 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14614586 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14612811 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501462134 # The number of ROB reads -system.cpu.rob.rob_writes 774278104 # The number of ROB writes -system.cpu.timesIdled 6640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 356471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500200856 # The number of ROB reads +system.cpu.rob.rob_writes 772408679 # The number of ROB writes +system.cpu.timesIdled 6691 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 356510 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.501792 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.501792 # CPI: Total CPI of All Threads -system.cpu.ipc 1.992856 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.992856 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769894079 # number of integer regfile reads -system.cpu.int_regfile_writes 233026497 # number of integer regfile writes -system.cpu.fp_regfile_reads 188140638 # number of floating regfile reads -system.cpu.fp_regfile_writes 132514898 # number of floating regfile writes -system.cpu.misc_regfile_reads 1201076625 # number of misc regfile reads +system.cpu.cpi 0.499900 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.499900 # CPI: Total CPI of All Threads +system.cpu.ipc 2.000402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.000402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768035388 # number of integer regfile reads +system.cpu.int_regfile_writes 232615737 # number of integer regfile writes +system.cpu.fp_regfile_reads 188041949 # number of floating regfile reads +system.cpu.fp_regfile_writes 132439422 # number of floating regfile writes +system.cpu.misc_regfile_reads 1200568638 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.toL2Bus.throughput 20069641 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 17607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 17606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1035 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2841 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 41930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1013312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1374592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 1374592 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 11777500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 20175639 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2838 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31713 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 41990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1014784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 362112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1376896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1376896 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11796500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24288488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24305488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7388212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7381711 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 13947 # number of replacements -system.cpu.icache.tags.tagsinuse 1848.346697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 37578823 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15836 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2372.999684 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13966 # number of replacements +system.cpu.icache.tags.tagsinuse 1849.581585 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 37434387 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15856 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 2360.897263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1848.346697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.902513 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1889 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1849.581585 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.903116 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 205 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1530 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.922363 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 75208123 # Number of tag accesses -system.cpu.icache.tags.data_accesses 75208123 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 37578823 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37578823 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37578823 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37578823 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37578823 # number of overall hits -system.cpu.icache.overall_hits::total 37578823 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17320 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17320 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17320 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17320 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17320 # number of overall misses -system.cpu.icache.overall_misses::total 17320 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 450229234 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 450229234 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 450229234 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 450229234 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 450229234 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37596143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37596143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37596143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37596143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37596143 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25994.759469 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25994.759469 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25994.759469 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25994.759469 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2351 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 1531 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 74919290 # Number of tag accesses +system.cpu.icache.tags.data_accesses 74919290 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 37434387 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37434387 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37434387 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37434387 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37434387 # number of overall hits +system.cpu.icache.overall_hits::total 37434387 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17330 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17330 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17330 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17330 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17330 # number of overall misses +system.cpu.icache.overall_misses::total 17330 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 451723484 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 451723484 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 451723484 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 451723484 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 451723484 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37451717 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37451717 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37451717 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37451717 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37451717 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26065.982920 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 26065.982920 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 26065.982920 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 26065.982920 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1035 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.040000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 39.807692 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1482 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1482 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1482 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1482 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1482 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15838 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15838 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15838 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15838 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15838 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15838 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359653509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 359653509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359653509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 359653509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359653509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 359653509 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000421 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000421 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000421 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22708.265501 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22708.265501 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22708.265501 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22708.265501 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1473 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1473 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1473 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1473 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1473 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1473 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15857 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15857 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15857 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15857 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15857 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15857 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 359348009 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 359348009 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 359348009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 359348009 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 359348009 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 359348009 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000423 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000423 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000423 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22661.790313 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22661.790313 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22661.790313 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22661.790313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22661.790313 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22661.790313 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3937.367139 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13183 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5383 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449006 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3939.930856 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13213 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5393 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.450028 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 378.211483 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2780.743240 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 778.412416 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011542 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084862 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.023755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.120159 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5383 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1236 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4007 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164276 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180072 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180072 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 12790 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 299 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 13089 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1035 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1035 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 17 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 17 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12790 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 316 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13106 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12790 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 316 # number of overall hits -system.cpu.l2cache.overall_hits::total 13106 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3044 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.355929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922061 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.355929 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58311.819082 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60104.412787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58889.156222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58611.968085 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58311.819082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59116.224466 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58781.901756 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1413 # number of replacements -system.cpu.dcache.tags.tagsinuse 3103.986618 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170973728 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37087.576573 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1416 # number of replacements +system.cpu.dcache.tags.tagsinuse 3111.494128 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170791722 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4619 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 36975.908638 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3103.986618 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.757809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 682 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2449 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 342002086 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 342002086 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88920204 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88920204 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11020 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 3111.494128 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.759642 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2450 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.781982 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 341638239 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 341638239 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88738255 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88738255 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031563 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11009 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11009 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170951801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170951801 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170951801 # number of overall hits -system.cpu.dcache.overall_hits::total 170951801 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3952 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3952 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21068 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21068 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170769818 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170769818 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170769818 # number of overall hits +system.cpu.dcache.overall_hits::total 170769818 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3984 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21102 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25020 # number of overall misses -system.cpu.dcache.overall_misses::total 25020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 237491705 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 237491705 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1258064893 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1258064893 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25086 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25086 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25086 # number of overall misses +system.cpu.dcache.overall_misses::total 25086 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 232475203 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 232475203 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1255700879 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1255700879 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 170250 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 170250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1495556598 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1495556598 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1495556598 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88924156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88924156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1488176082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1488176082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1488176082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88742239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88742239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11011 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11011 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170976821 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170976821 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170976821 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170976821 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000044 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000044 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170794904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170794904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170794904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170794904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000257 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000257 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60094.054909 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60094.054909 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59714.490839 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59714.490839 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58352.209588 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58352.209588 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59506.249597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59506.249597 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59774.444365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59774.444365 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 27944 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1224 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 406 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.827586 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 102 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59322.972255 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59322.972255 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 26768 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1267 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 424 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.132075 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 97.461538 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1035 # number of writebacks -system.cpu.dcache.writebacks::total 1035 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2181 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18227 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18227 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1039 # number of writebacks +system.cpu.dcache.writebacks::total 1039 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2202 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2202 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18265 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18265 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20408 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20408 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20408 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1771 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1771 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2841 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2841 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 115481540 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 201937248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 317418788 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 317418788 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 317418788 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20467 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20467 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20467 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1782 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1782 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2837 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2837 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4619 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4619 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4619 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111706789 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 203137000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 314843789 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 314843789 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 314843789 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -1028,14 +990,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65206.967815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71079.636748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68824.542064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68824.542064 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62686.189113 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71602.749383 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68162.760121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68162.760121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 130b22828..55140cd28 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.631518 # Number of seconds simulated -sim_ticks 631518097500 # Number of ticks simulated -final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629599 # Number of seconds simulated +sim_ticks 629599373500 # Number of ticks simulated +final_tick 629599373500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171044 # Simulator instruction rate (inst/s) -host_op_rate 171044 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59250964 # Simulator tick rate (ticks/s) -host_mem_usage 240608 # Number of bytes of host memory used -host_seconds 10658.36 # Real time elapsed on the host +host_inst_rate 142688 # Simulator instruction rate (inst/s) +host_op_rate 142688 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49278187 # Simulator tick rate (ticks/s) +host_mem_usage 277460 # Number of bytes of host memory used +host_seconds 12776.43 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176128 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295936 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176768 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2752 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473367 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476119 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2762 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476136 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 278896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47972478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48251374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 278896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6780664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6780664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 278896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47972478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55032038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476119 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 280763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48119387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48400150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280763 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6801328 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6801328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48119387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55201478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476136 # Number of read requests accepted system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.readBursts 476119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 476136 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30465984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4281664 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30471616 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30452800 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30472704 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 88 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29449 # Per bank write bursts -system.physmem.perBankRdBursts::1 29798 # Per bank write bursts -system.physmem.perBankRdBursts::2 29850 # Per bank write bursts -system.physmem.perBankRdBursts::3 29793 # Per bank write bursts -system.physmem.perBankRdBursts::4 29695 # Per bank write bursts -system.physmem.perBankRdBursts::5 29771 # Per bank write bursts -system.physmem.perBankRdBursts::6 29867 # Per bank write bursts -system.physmem.perBankRdBursts::7 29856 # Per bank write bursts -system.physmem.perBankRdBursts::8 29771 # Per bank write bursts -system.physmem.perBankRdBursts::9 29894 # Per bank write bursts -system.physmem.perBankRdBursts::10 29844 # Per bank write bursts -system.physmem.perBankRdBursts::11 29915 # Per bank write bursts -system.physmem.perBankRdBursts::12 29793 # Per bank write bursts -system.physmem.perBankRdBursts::13 29587 # Per bank write bursts -system.physmem.perBankRdBursts::14 29511 # Per bank write bursts -system.physmem.perBankRdBursts::15 29637 # Per bank write bursts +system.physmem.perBankRdBursts::0 29443 # Per bank write bursts +system.physmem.perBankRdBursts::1 29785 # Per bank write bursts +system.physmem.perBankRdBursts::2 29834 # Per bank write bursts +system.physmem.perBankRdBursts::3 29781 # Per bank write bursts +system.physmem.perBankRdBursts::4 29679 # Per bank write bursts +system.physmem.perBankRdBursts::5 29744 # Per bank write bursts +system.physmem.perBankRdBursts::6 29853 # Per bank write bursts +system.physmem.perBankRdBursts::7 29847 # Per bank write bursts +system.physmem.perBankRdBursts::8 29759 # Per bank write bursts +system.physmem.perBankRdBursts::9 29871 # Per bank write bursts +system.physmem.perBankRdBursts::10 29836 # Per bank write bursts +system.physmem.perBankRdBursts::11 29910 # Per bank write bursts +system.physmem.perBankRdBursts::12 29783 # Per bank write bursts +system.physmem.perBankRdBursts::13 29571 # Per bank write bursts +system.physmem.perBankRdBursts::14 29499 # Per bank write bursts +system.physmem.perBankRdBursts::15 29630 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4241 # Per bank write bursts +system.physmem.perBankWrBursts::10 4219 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 631518039500 # Total gap between requests +system.physmem.totGap 629599315500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476119 # Read request sizes (log2) +system.physmem.readPktSize::6 476136 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,223 +129,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 182335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 190.554573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 126.681752 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 408.631079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 68422 37.53% 37.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 48844 26.79% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37964 20.82% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 20159 11.06% 96.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 264 0.14% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 246 0.13% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 141 0.08% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 184 0.10% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 113 0.06% 96.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 137 0.08% 96.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 96 0.05% 96.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 186 0.10% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 81 0.04% 96.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 159 0.09% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 151 0.08% 97.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 133 0.07% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 108 0.06% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 148 0.08% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 143 0.08% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 80 0.04% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 131 0.07% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 1760 0.97% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 1531 0.84% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 10 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 19 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 18 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 8 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 14 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 14 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 13 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 14 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 6 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 10 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 20 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 12 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 11 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 18 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 13 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 17 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 12 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 11 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 14 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 18 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 12 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 10 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 14 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 17 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 14 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 13 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 12 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 9 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 8 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 11 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 18 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 9 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 16 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 12 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 17 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 14 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 15 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 5 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 16 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 14 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 13 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 15 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 11 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 18 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 12 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 8 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 9 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 12 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 6 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 11 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 11 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 15 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 12 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 11 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 16 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 11 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 13 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 16 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 12 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 12 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 17 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 10 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 11 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 22 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 11 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 8 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 12 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 26 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 26 0.01% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 39 0.02% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400 37 0.02% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464 7 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656 3 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720 7 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848 54 0.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 182335 # Bytes accessed per row activation -system.physmem.totQLat 2888040000 # Total ticks spent queuing -system.physmem.totMemAccLat 14116017500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2380155000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8847822500 # Total ticks spent accessing banks -system.physmem.avgQLat 6066.92 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 18586.65 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 530.927244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.070424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 451.227629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7470 34.53% 34.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2793 12.91% 47.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 292 1.35% 48.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 662 3.06% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 618 2.86% 54.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 184 0.85% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 105 0.49% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 0.31% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9443 43.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21634 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 114.953218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.941709 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1121.982719 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4021 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-12287 1 0.02% 99.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 11 0.27% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554208 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.524474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.020237 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3080 76.24% 76.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 645 15.97% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 312 7.72% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4040 # Writes before turning the bus around for reads +system.physmem.totQLat 3865744500 # Total ticks spent queuing +system.physmem.totMemAccLat 15098494500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2379125000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8853625000 # Total ticks spent accessing banks +system.physmem.avgQLat 8124.30 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 18606.89 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29653.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31731.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 6.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.40 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.28 # Average write queue length when enqueuing -system.physmem.readRowHits 310714 # Number of row buffer hits during reads -system.physmem.writeRowHits 49883 # Number of row buffer hits during writes -system.physmem.readRowHitRate 65.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.55 # Row buffer hit rate for writes -system.physmem.avgGap 1162958.82 # Average gap between requests -system.physmem.pageHitRate 66.42 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 25.73 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 55031937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 409266 # Transaction distribution -system.membus.trans_dist::ReadResp 409265 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 304858 # Number of row buffer hits during reads +system.physmem.writeRowHits 50638 # Number of row buffer hits during writes +system.physmem.readRowHitRate 64.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes +system.physmem.avgGap 1159389.14 # Average gap between requests +system.physmem.pageHitRate 65.50 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 25.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55201376 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409283 # Transaction distribution +system.membus.trans_dist::ReadResp 409282 # Transaction distribution system.membus.trans_dist::Writeback 66908 # Transaction distribution system.membus.trans_dist::ReadExReq 66853 # Transaction distribution system.membus.trans_dist::ReadExResp 66853 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019145 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019145 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34753664 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34753664 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019179 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34754752 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34754752 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1230652000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1216217500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4476344750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 388926557 # Number of BP lookups -system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 317451636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 258383726 # Number of BTB hits +system.cpu.branchPred.lookups 388794194 # Number of BP lookups +system.cpu.branchPred.condPredicted 256437181 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25515612 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 316966671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 257889505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.393100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 57269217 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6785 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.361710 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 56977055 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6765 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 522276153 # DTB read hits -system.cpu.dtb.read_misses 591029 # DTB read misses +system.cpu.dtb.read_hits 520530320 # DTB read hits +system.cpu.dtb.read_misses 596868 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 522867182 # DTB read accesses -system.cpu.dtb.write_hits 283024283 # DTB write hits -system.cpu.dtb.write_misses 50282 # DTB write misses +system.cpu.dtb.read_accesses 521127188 # DTB read accesses +system.cpu.dtb.write_hits 282735636 # DTB write hits +system.cpu.dtb.write_misses 50248 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 283074565 # DTB write accesses -system.cpu.dtb.data_hits 805300436 # DTB hits -system.cpu.dtb.data_misses 641311 # DTB misses +system.cpu.dtb.write_accesses 282785884 # DTB write accesses +system.cpu.dtb.data_hits 803265956 # DTB hits +system.cpu.dtb.data_misses 647116 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 805941747 # DTB accesses -system.cpu.itb.fetch_hits 394923336 # ITB hits -system.cpu.itb.fetch_misses 673 # ITB misses +system.cpu.dtb.data_accesses 803913072 # DTB accesses +system.cpu.itb.fetch_hits 392575649 # ITB hits +system.cpu.itb.fetch_misses 637 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 394924009 # ITB accesses +system.cpu.itb.fetch_accesses 392576286 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -359,238 +311,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1263036196 # number of cpu cycles simulated +system.cpu.numCycles 1259198748 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 410109214 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3275361918 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388926557 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 315652943 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 630278695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157942220 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 76359250 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 149 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7183 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 394923336 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11250823 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.623652 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.139094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 407695740 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3264617465 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388794194 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 314866560 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 628012855 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156754099 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 76226521 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6801 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 392575649 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11023705 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.627055 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.139887 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 618119324 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 57470502 4.60% 54.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43321703 3.47% 57.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71848580 5.76% 63.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129169735 10.35% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46220345 3.70% 77.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41223036 3.30% 80.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7614963 0.61% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 233409831 18.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614678294 49.46% 49.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57194010 4.60% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43037577 3.46% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71548664 5.76% 63.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 128942698 10.38% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45555972 3.67% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41222741 3.32% 80.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8274333 0.67% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232236860 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1248398019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307930 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.593245 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438388192 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 62722156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 606598506 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9057712 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 131631453 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31714965 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12425 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3194311917 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 131631453 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 467678494 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 27888696 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 586017174 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35154967 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3095577926 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 28853292 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2054701913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3579840200 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3494452830 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 85387369 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1242691149 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308763 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.592615 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 436055809 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62292865 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 604244409 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9361042 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 130737024 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31725769 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12419 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3186787270 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46304 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 130737024 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 465340122 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27154826 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 583972819 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35459361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3088232608 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 174 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15483 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 29158265 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2049406757 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3572462908 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3487065334 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85397573 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 669732843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4230 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 109697167 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 743928173 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 351370571 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 69056444 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8824928 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2623617019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2160251371 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17943532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 800506398 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 726504541 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1248398019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.730419 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.803325 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 664437687 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110031896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 740965992 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 350476523 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68460641 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8808840 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2617422170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 92 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2156741664 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17943359 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 794308745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 722892982 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1242691149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.735541 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.803084 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 451794387 36.19% 36.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 196881068 15.77% 51.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 251357257 20.13% 72.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120660419 9.67% 81.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 104720933 8.39% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79314003 6.35% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 24236778 1.94% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17665275 1.42% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767899 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 447799861 36.03% 36.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 195733301 15.75% 51.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 250780419 20.18% 71.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120973704 9.73% 81.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105324665 8.48% 90.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 78133504 6.29% 96.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24822476 2.00% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17360375 1.40% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1762844 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1248398019 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1242691149 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146213 3.11% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25664248 69.68% 72.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10022787 27.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146236 3.14% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25360136 69.42% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022546 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1234386709 57.14% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17098 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851280 1.29% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589426190 27.29% 86.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 293107997 13.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1232941102 57.17% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17091 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851332 1.29% 58.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204650 0.33% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587650943 27.25% 86.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 292819094 13.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2160251371 # Type of FU issued -system.cpu.iq.rate 1.710364 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36833248 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017050 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5472576321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3336085108 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1990052081 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101220 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88112403 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73609796 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2119632115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449752 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62130294 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2156741664 # Type of FU issued +system.cpu.iq.rate 1.712789 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36528918 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5459545573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3323652243 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1987168817 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151101181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88152162 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609871 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2115818130 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449700 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62140575 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 232858147 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12904 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76517 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 140575675 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229895966 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17367 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75928 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 139681627 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4420 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2986 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2851 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 131631453 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13854870 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540713 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2987064964 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 734565 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 743928173 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 351370571 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 134613 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 130737024 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13158740 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 531547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2980853453 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 734148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 740965992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 350476523 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 92 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 133073 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1496 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76517 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25801220 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 30372 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25831592 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2066130188 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 522867337 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 94121183 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 75928 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25509079 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 28871 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25537950 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2062960594 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 521127327 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 93781070 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363447857 # number of nop insts executed -system.cpu.iew.exec_refs 805942372 # number of memory reference insts executed -system.cpu.iew.exec_branches 277625839 # Number of branches executed -system.cpu.iew.exec_stores 283075035 # Number of stores executed -system.cpu.iew.exec_rate 1.635844 # Inst execution rate -system.cpu.iew.wb_sent 2066015513 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2063661877 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1180966911 # num instructions producing a value -system.cpu.iew.wb_consumers 1753315239 # num instructions consuming a value +system.cpu.iew.exec_nop 363431191 # number of nop insts executed +system.cpu.iew.exec_refs 803913709 # number of memory reference insts executed +system.cpu.iew.exec_branches 277349504 # Number of branches executed +system.cpu.iew.exec_stores 282786382 # Number of stores executed +system.cpu.iew.exec_rate 1.638312 # Inst execution rate +system.cpu.iew.wb_sent 2062843616 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2060778688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180081311 # num instructions producing a value +system.cpu.iew.wb_consumers 1751769057 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.633890 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673562 # average fanout of values written-back +system.cpu.iew.wb_rate 1.636579 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673651 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 961121274 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 954910834 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25796748 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1116766566 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.798932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.506928 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25503576 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1111954125 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.806718 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.513025 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497624741 44.56% 44.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 228755331 20.48% 65.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119853188 10.73% 75.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 58815833 5.27% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50567042 4.53% 85.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24161277 2.16% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19140455 1.71% 89.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16628477 1.49% 90.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101220222 9.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 493953799 44.42% 44.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227598258 20.47% 64.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120157352 10.81% 75.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 59117436 5.32% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 49692095 4.47% 85.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24169379 2.17% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18838880 1.69% 89.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16341629 1.47% 90.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102085297 9.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1116766566 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1111954125 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -601,229 +553,229 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101220222 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102085297 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3980018812 # The number of ROB reads -system.cpu.rob.rob_writes 6071851301 # The number of ROB writes -system.cpu.timesIdled 346634 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14638177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3968130856 # The number of ROB reads +system.cpu.rob.rob_writes 6058536012 # The number of ROB writes +system.cpu.timesIdled 350219 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16507599 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.692817 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.692817 # CPI: Total CPI of All Threads -system.cpu.ipc 1.443382 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.443382 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2627972093 # number of integer regfile reads -system.cpu.int_regfile_writes 1496658985 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811105 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661052 # number of floating regfile writes +system.cpu.cpi 0.690712 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.690712 # CPI: Total CPI of All Threads +system.cpu.ipc 1.447780 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.447780 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2624503768 # number of integer regfile reads +system.cpu.int_regfile_writes 1494046892 # number of integer regfile writes +system.cpu.fp_regfile_reads 78811207 # number of floating regfile reads +system.cpu.fp_regfile_writes 52661075 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 165988542 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1470277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1470276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.throughput 166495312 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95977 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 71640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 71640 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159755 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3179804 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 641536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104183232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 104824768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 104824768 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3159707 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3179816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 643456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104181888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 104825344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104825344 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 914915000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 914925500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15531000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 15572000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2359590250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2358250250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 8311 # number of replacements -system.cpu.icache.tags.tagsinuse 1658.001589 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 394910393 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 39396.487729 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 8345 # number of replacements +system.cpu.icache.tags.tagsinuse 1652.999012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 392562699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10054 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 39045.424607 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1652.999012 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.807128 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1567 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 789856696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 789856696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 394910393 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 394910393 # number of overall hits -system.cpu.icache.overall_hits::total 394910393 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12943 # number of overall misses -system.cpu.icache.overall_misses::total 12943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 383664999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 383664999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 383664999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 383664999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 383664999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 394923336 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 394923336 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 394923336 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 394923336 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 392575649 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 392575649 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 392575649 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 392575649 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29642.663911 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 29642.663911 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 29642.663911 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 29642.663911 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 29642.663911 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 707 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29711.428494 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29711.428494 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29711.428494 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29711.428494 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29711.428494 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281678249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281678249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281678249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281678249 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28222.351964 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28222.351964 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 443340 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32689.012035 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1090033 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 476076 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.289620 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 443357 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 505 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5021 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26866 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13650820 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13650820 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 7273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053738 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1061011 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95971 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278371 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933180 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.933180 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274514 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309008 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.308784 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274514 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.309008 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.308784 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72279.160610 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72133.122106 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72134.104103 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78187.549549 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78187.549549 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72984.082761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72279.160610 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72988.180946 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72984.082761 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.274689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309018 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308794 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.274689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309018 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308794 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72695.510500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73430.274820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73425.316346 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84901.806950 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84901.806950 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75050.360286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75036.700123 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72695.510500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75050.360286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75036.700123 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -834,187 +786,181 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2752 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406514 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409266 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24893429250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4868551500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4868551500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165956500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 29596024250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29761980750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165956500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 29596024250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29761980750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278396 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278371 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933180 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308784 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274514 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309008 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308784 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59664.335029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59490.858863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59492.025358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66151.560139 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59664.335029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60431.540961 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60427.106459 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308794 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.274689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309018 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308794 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60085.626358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60827.048910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60822.045504 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72824.727387 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60085.626358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62521.440235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62507.310411 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1527796 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.588575 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 667945835 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1531892 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 436.026714 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 408904250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1527769 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.584887 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 666211737 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1531865 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 434.902382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 409920250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.584887 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2365 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 390 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1343398986 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1343398986 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209732941 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667945812 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667945812 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667945812 # number of overall hits -system.cpu.dcache.overall_hits::total 667945812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925756 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 77391157750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 46191876602 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 46191876602 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 123583034352 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 123583034352 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 123583034352 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 460138627 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 460138627 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2965805 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2965805 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2965805 # number of overall misses +system.cpu.dcache.overall_misses::total 2965805 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 77884724250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 77884724250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53548786128 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53548786128 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 73000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 73000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 131433510378 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 131433510378 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 131433510378 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 131433510378 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 458382618 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 458382618 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 670933523 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 670933523 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 670933523 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 670933523 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004185 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.041667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004453 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004453 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004453 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004453 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40187.416137 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40187.416137 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43497.018802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43497.018802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41363.784634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41363.784634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17901 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 132 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 338 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 29 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 669177514 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 669177514 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 669177514 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 669177514 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004201 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004934 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40442.978625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40442.978625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51488.524316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51488.524316 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 73000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 73000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44316.302110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44316.302110 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18203 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 374 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.961538 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.671123 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 134 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks -system.cpu.dcache.writebacks::total 95971 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990315 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990315 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455820 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455820 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455820 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460251 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460251 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 95977 # number of writebacks +system.cpu.dcache.writebacks::total 95977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465566 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465566 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 968374 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 968374 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1433940 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1433940 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1433940 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460225 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460225 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71640 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 71640 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531891 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531891 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531891 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41321289000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5347166250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 76000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46668455250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46668455250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41848820250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5798224000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47647044250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47647044250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003186 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003186 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002283 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002283 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28297.387915 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74639.394891 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 76000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30464.605674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30464.605674 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002289 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28659.158863 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80935.566723 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31103.944701 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31103.944701 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index b6f8c26dc..067d517cb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.629535 # Number of seconds simulated -sim_ticks 629535413500 # Number of ticks simulated -final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629657 # Number of seconds simulated +sim_ticks 629657386500 # Number of ticks simulated +final_tick 629657386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106173 # Simulator instruction rate (inst/s) -host_op_rate 144593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48281629 # Simulator tick rate (ticks/s) -host_mem_usage 278772 # Number of bytes of host memory used -host_seconds 13038.82 # Real time elapsed on the host +host_inst_rate 85982 # Simulator instruction rate (inst/s) +host_op_rate 117096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39107572 # Simulator tick rate (ticks/s) +host_mem_usage 322024 # Number of bytes of host memory used +host_seconds 16100.65 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155136 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory +system.physmem.bytes_read::total 30398272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155392 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472539 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2428 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474973 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48039388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48285817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6719673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6719673 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6719673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48039388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55005490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474963 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 246788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48030692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48277480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246788 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6718371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6718371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6718371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48030692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54995851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474973 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 474963 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 474973 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30390400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30397632 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 30370688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30398272 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4262 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 29871 # Per bank write bursts -system.physmem.perBankRdBursts::1 29675 # Per bank write bursts -system.physmem.perBankRdBursts::2 29749 # Per bank write bursts -system.physmem.perBankRdBursts::3 29712 # Per bank write bursts -system.physmem.perBankRdBursts::4 29816 # Per bank write bursts -system.physmem.perBankRdBursts::5 29834 # Per bank write bursts -system.physmem.perBankRdBursts::6 29642 # Per bank write bursts -system.physmem.perBankRdBursts::7 29444 # Per bank write bursts -system.physmem.perBankRdBursts::8 29480 # Per bank write bursts -system.physmem.perBankRdBursts::9 29489 # Per bank write bursts -system.physmem.perBankRdBursts::10 29547 # Per bank write bursts -system.physmem.perBankRdBursts::11 29649 # Per bank write bursts -system.physmem.perBankRdBursts::12 29701 # Per bank write bursts -system.physmem.perBankRdBursts::13 29813 # Per bank write bursts -system.physmem.perBankRdBursts::14 29629 # Per bank write bursts -system.physmem.perBankRdBursts::15 29799 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4296 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29858 # Per bank write bursts +system.physmem.perBankRdBursts::1 29659 # Per bank write bursts +system.physmem.perBankRdBursts::2 29728 # Per bank write bursts +system.physmem.perBankRdBursts::3 29690 # Per bank write bursts +system.physmem.perBankRdBursts::4 29781 # Per bank write bursts +system.physmem.perBankRdBursts::5 29808 # Per bank write bursts +system.physmem.perBankRdBursts::6 29619 # Per bank write bursts +system.physmem.perBankRdBursts::7 29428 # Per bank write bursts +system.physmem.perBankRdBursts::8 29461 # Per bank write bursts +system.physmem.perBankRdBursts::9 29473 # Per bank write bursts +system.physmem.perBankRdBursts::10 29524 # Per bank write bursts +system.physmem.perBankRdBursts::11 29641 # Per bank write bursts +system.physmem.perBankRdBursts::12 29683 # Per bank write bursts +system.physmem.perBankRdBursts::13 29785 # Per bank write bursts +system.physmem.perBankRdBursts::14 29611 # Per bank write bursts +system.physmem.perBankRdBursts::15 29793 # Per bank write bursts system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4102 # Per bank write bursts -system.physmem.perBankWrBursts::2 4138 # Per bank write bursts -system.physmem.perBankWrBursts::3 4148 # Per bank write bursts -system.physmem.perBankWrBursts::4 4226 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::1 4100 # Per bank write bursts +system.physmem.perBankWrBursts::2 4137 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::5 4223 # Per bank write bursts +system.physmem.perBankWrBursts::6 4171 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 629535350500 # Total gap between requests +system.physmem.totGap 629657309500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 474963 # Read request sizes (log2) +system.physmem.readPktSize::6 474973 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,194 +129,157 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 190822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.419082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 122.160667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 377.205430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 76972 40.34% 40.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 49989 26.20% 66.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 37639 19.72% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 19482 10.21% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 187 0.10% 96.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 252 0.13% 96.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 85 0.04% 96.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 218 0.11% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 85 0.04% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 231 0.12% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 52 0.03% 97.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 225 0.12% 97.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 65 0.03% 97.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 188 0.10% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 60 0.03% 97.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 181 0.09% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 44 0.02% 97.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 201 0.11% 97.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 67 0.04% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 181 0.09% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 66 0.03% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3167 1.66% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 20 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 13 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 12 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 12 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 13 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 17 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 15 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 15 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 19 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 18 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 13 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 11 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 14 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 14 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 15 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 21 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 12 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 17 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 16 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 16 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 13 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 12 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 14 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 9 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 19 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 10 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 20 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 10 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 16 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 12 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 21 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 13 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 16 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 15 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 18 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 7 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 15 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 17 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 14 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 12 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 28 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 16 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 14 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 7 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 17 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 11 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 14 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 12 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672 19 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 10 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 13 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 9 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 17 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 8 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 17 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 7 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 9 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 9 0.00% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 13 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 14 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 12 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 15 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 31 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 73 0.04% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 59 0.03% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888 4 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 6 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 53 0.03% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 190822 # Bytes accessed per row activation -system.physmem.totQLat 3804806750 # Total ticks spent queuing -system.physmem.totMemAccLat 15248020500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2374250000 # Total ticks spent in databus transfers -system.physmem.totBankLat 9068963750 # Total ticks spent accessing banks -system.physmem.avgQLat 8012.65 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 19098.59 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 28167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 403.324742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.656646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 439.024801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14746 52.35% 52.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2789 9.90% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 571 2.03% 64.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 164 0.58% 64.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 93 0.33% 65.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 524 1.86% 67.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 314 1.11% 68.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 86 0.31% 68.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8880 31.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 28167 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.707415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.187766 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.851977 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3989 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::31744-32767 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3992 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.551353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.521439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.024563 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3052 76.45% 76.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 627 15.71% 92.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 310 7.77% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3992 # Writes before turning the bus around for reads +system.physmem.totQLat 3604221250 # Total ticks spent queuing +system.physmem.totMemAccLat 15074013750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2372710000 # Total ticks spent in databus transfers +system.physmem.totBankLat 9097082500 # Total ticks spent accessing banks +system.physmem.avgQLat 7595.16 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 19170.24 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32111.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 48.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31765.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 48.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 48.29 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 48.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.72 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.84 # Average write queue length when enqueuing -system.physmem.readRowHits 300749 # Number of row buffer hits during reads -system.physmem.writeRowHits 49371 # Number of row buffer hits during writes -system.physmem.readRowHitRate 63.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.69 # Row buffer hit rate for writes -system.physmem.avgGap 1163520.10 # Average gap between requests -system.physmem.pageHitRate 64.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 24.30 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 55005389 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 408886 # Transaction distribution -system.membus.trans_dist::ReadResp 408885 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing +system.physmem.readRowHits 295971 # Number of row buffer hits during reads +system.physmem.writeRowHits 49954 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.58 # Row buffer hit rate for writes +system.physmem.avgGap 1163724.00 # Average gap between requests +system.physmem.pageHitRate 63.98 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 24.27 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 54995851 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408896 # Transaction distribution +system.membus.trans_dist::ReadResp 408896 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4262 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4262 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution system.membus.trans_dist::ReadExReq 66077 # Transaction distribution system.membus.trans_dist::ReadExResp 66077 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024547 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1024547 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34627840 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34627840 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34627840 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024636 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34628544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34628544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34628544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215457500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1215525500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4442862738 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4444359954 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 438247722 # Number of BP lookups -system.cpu.branchPred.condPredicted 350864471 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 248480162 # Number of BTB lookups -system.cpu.branchPred.BTBHits 229339460 # Number of BTB hits +system.cpu.branchPred.lookups 438199522 # Number of BP lookups +system.cpu.branchPred.condPredicted 350949441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30620410 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 248742563 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229772650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.296889 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52915671 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2805331 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.373676 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52962534 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2805242 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -402,100 +365,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1259070828 # number of cpu cycles simulated +system.cpu.numCycles 1259314774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354141020 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2279761292 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438247722 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282255131 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601258233 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157188182 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 134732573 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11340 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 159 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 334734643 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658358 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1216659303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.575913 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.175897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354212583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2278943291 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438199522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282735184 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601285341 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157201665 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 134990206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11080 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 114 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 334803997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11648696 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1217029612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.574413 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174582 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 615445842 50.58% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42369042 3.48% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95794203 7.87% 61.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 57788183 4.75% 66.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71908380 5.91% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44699403 3.67% 76.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31096366 2.56% 78.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31485891 2.59% 81.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226071993 18.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 615789102 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42212896 3.47% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95956201 7.88% 61.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57716133 4.74% 66.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 72254915 5.94% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44707595 3.67% 76.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31168110 2.56% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31500430 2.59% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 225724230 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1216659303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348072 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.810670 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405371770 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106745247 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 560687148 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17351012 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 126504126 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44828011 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11498 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3022924000 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 26519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 126504126 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441422956 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38086039 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 457739 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 539750713 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70437730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2941757147 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4808697 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54385461 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 740 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2930215043 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14237570542 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12151139431 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 84006834 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1217029612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.347967 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.809669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405265267 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107157501 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 560735859 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17352207 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 126518778 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44627065 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3022541715 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 126518778 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441244328 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38456610 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 454301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 539911121 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70444474 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2941731616 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4811465 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54362751 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2929353177 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14237214542 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12151315514 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 83979009 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 937074953 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20556 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18072 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179296103 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 971747851 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 485687926 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36754298 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 38315968 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2792666387 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27976 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2435151733 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13267287 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 894813074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2341267254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6592 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1216659303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.001507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.873340 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 936213087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20203 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17724 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179723252 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971631963 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 486198822 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36723664 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38677099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2793016392 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27622 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2435260833 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13305109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 895166670 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2343525890 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6238 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1217029612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.000987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.873461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 380682463 31.29% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183043299 15.04% 46.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204121257 16.78% 63.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169552429 13.94% 77.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132904836 10.92% 87.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92976040 7.64% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37964484 3.12% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12393775 1.02% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3020720 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 381057421 31.31% 31.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183026992 15.04% 46.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204041316 16.77% 63.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169676462 13.94% 77.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132865899 10.92% 87.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92968001 7.64% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37978061 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12373824 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3041636 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1216659303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1217029612 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714585 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 714935 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24383 0.03% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available @@ -523,13 +486,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55158409 62.92% 63.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31764976 36.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55166828 62.92% 63.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31766374 36.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1104245990 45.35% 45.35% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223912 0.46% 45.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1104417509 45.35% 45.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223990 0.46% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.81% # Type of FU issued @@ -548,93 +511,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.81% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876479 0.28% 46.15% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502438 0.23% 46.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23399832 0.96% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 840060400 34.50% 81.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442467389 18.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.15% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5501794 0.23% 46.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23394204 0.96% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 839996872 34.49% 81.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442474698 18.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2435151733 # Type of FU issued -system.cpu.iq.rate 1.934086 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87662351 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6065394864 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3604907210 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2250139818 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122497543 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82667139 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56433103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2459502901 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63311183 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84462690 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2435260833 # Type of FU issued +system.cpu.iq.rate 1.933798 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87672520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6066045738 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3605651148 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2250091074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122483169 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82625914 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56426435 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2459629474 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63303879 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84463938 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 340360670 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9529 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1430281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 208692629 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340244782 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10257 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1430041 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 209203525 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 356 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 126504126 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16045638 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1563592 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2792706809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1386483 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 971747851 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 485687926 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 17990 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1559989 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2525 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1430281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32383306 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1525297 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33908603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2359934527 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 794158761 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 75217206 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 126518778 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16487163 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1561706 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2793056470 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1389243 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971631963 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 486198822 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 17636 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558036 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1430041 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32401956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1516006 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33917962 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2359922616 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 794093704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75338217 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12446 # number of nop insts executed -system.cpu.iew.exec_refs 1217435347 # number of memory reference insts executed -system.cpu.iew.exec_branches 319532182 # Number of branches executed -system.cpu.iew.exec_stores 423276586 # Number of stores executed -system.cpu.iew.exec_rate 1.874346 # Inst execution rate -system.cpu.iew.wb_sent 2332318600 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2306572921 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1349155649 # num instructions producing a value -system.cpu.iew.wb_consumers 2527421878 # num instructions consuming a value +system.cpu.iew.exec_nop 12456 # number of nop insts executed +system.cpu.iew.exec_refs 1217365234 # number of memory reference insts executed +system.cpu.iew.exec_branches 319562430 # Number of branches executed +system.cpu.iew.exec_stores 423271530 # Number of stores executed +system.cpu.iew.exec_rate 1.873974 # Inst execution rate +system.cpu.iew.wb_sent 2332280723 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2306517509 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1349120960 # num instructions producing a value +system.cpu.iew.wb_consumers 2527351065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.831964 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533807 # average fanout of values written-back +system.cpu.iew.wb_rate 1.831566 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533808 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 907370579 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 907720231 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30609580 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1090155177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.729420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.397089 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30609492 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1090510834 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.728856 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.396955 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 449868742 41.27% 41.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288583282 26.47% 67.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95106533 8.72% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70222065 6.44% 82.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46473839 4.26% 87.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22181225 2.03% 89.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15848509 1.45% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10986576 1.01% 91.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884406 8.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 450229589 41.29% 41.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288600221 26.46% 67.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95089363 8.72% 76.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70207190 6.44% 82.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46482431 4.26% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22180112 2.03% 89.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15844912 1.45% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10980043 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90896973 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1090155177 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1090510834 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -645,240 +608,240 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884406 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90896973 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3791959363 # The number of ROB reads -system.cpu.rob.rob_writes 5711929117 # The number of ROB writes -system.cpu.timesIdled 353184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42411525 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3792652105 # The number of ROB reads +system.cpu.rob.rob_writes 5712643141 # The number of ROB writes +system.cpu.timesIdled 352993 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42285162 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.909490 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.909490 # CPI: Total CPI of All Threads -system.cpu.ipc 1.099518 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.099518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11767673388 # number of integer regfile reads -system.cpu.int_regfile_writes 2220511965 # number of integer regfile writes -system.cpu.fp_regfile_reads 68796181 # number of floating regfile reads -system.cpu.fp_regfile_writes 49544953 # number of floating regfile writes -system.cpu.misc_regfile_reads 1678583418 # number of misc regfile reads +system.cpu.cpi 0.909666 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.909666 # CPI: Total CPI of All Threads +system.cpu.ipc 1.099305 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.099305 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11767299799 # number of integer regfile reads +system.cpu.int_regfile_writes 2220455487 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795103 # number of floating regfile reads +system.cpu.fp_regfile_writes 49537962 # number of floating regfile writes +system.cpu.misc_regfile_reads 1678438007 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.toL2Bus.throughput 169029894 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1493831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1493830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 96313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 4265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 4265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72518 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54300 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3178976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3233276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1601152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104536256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 106137408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 106137408 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 272896 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 929776999 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 168942873 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1493289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1493289 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72517 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72517 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3179025 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3232233 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1565120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104535936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 106101056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106101056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929534000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 44342246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 43545495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2368551488 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2368755772 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 23332 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.273486 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 334698554 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25017 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13378.844546 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 22771 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.597248 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 334768394 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24455 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13689.159436 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1685 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.822754 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 669498564 # Number of tag accesses -system.cpu.icache.tags.data_accesses 669498564 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 334702534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 334702534 # number of overall hits -system.cpu.icache.overall_hits::total 334702534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32107 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32107 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32107 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32107 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32107 # number of overall misses -system.cpu.icache.overall_misses::total 32107 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 545585992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 545585992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 545585992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 545585992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 545585992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 545585992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 334734641 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 334734641 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 334734641 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 334734641 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 334734641 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 334734641 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16992.742766 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16992.742766 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16992.742766 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16992.742766 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16992.742766 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2092 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.597248 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801073 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801073 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1684 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 669636743 # Number of tag accesses +system.cpu.icache.tags.data_accesses 669636743 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 334772400 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 334772400 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 334772400 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 334772400 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 334772400 # number of overall hits +system.cpu.icache.overall_hits::total 334772400 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31595 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31595 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31595 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31595 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31595 # number of overall misses +system.cpu.icache.overall_misses::total 31595 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 539866742 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 539866742 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 539866742 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 539866742 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 539866742 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 539866742 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 334803995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 334803995 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 334803995 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 334803995 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 334803995 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 334803995 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17087.094224 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17087.094224 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17087.094224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17087.094224 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17087.094224 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1720 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.052632 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2825 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2825 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2825 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2825 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2825 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2825 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29282 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 29282 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 29282 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 29282 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 29282 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 29282 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435718750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 435718750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435718750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 435718750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435718750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 435718750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14880.088450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14880.088450 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14880.088450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14880.088450 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2842 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2842 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2842 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2842 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2842 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2842 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28753 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28753 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28753 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28753 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28753 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28753 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429678502 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429678502 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429678502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429678502 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429678502 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429678502 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14943.779849 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14943.779849 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14943.779849 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14943.779849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14943.779849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14943.779849 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 442179 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32678.084712 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1110777 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 474927 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.338837 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 442191 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32677.338993 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1109910 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 474938 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.336958 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1317.536898 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 51.699719 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31308.848096 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1321.185121 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.537350 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31305.616521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.040319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001542 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.955372 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997233 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32747 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5020 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26968 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60018.945634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63484.905946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63464.325281 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59400.074913 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59400.074913 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60081.580033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62664.492772 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62651.310734 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54709.755286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54709.755286 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62257.857453 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62246.412428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60018.945634 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62257.857453 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62246.412428 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1532970 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.376677 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 971409331 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1537066 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 631.989343 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 400505250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1532957 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.373897 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 971355471 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1537053 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 631.959647 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 402104250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.373897 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999603 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2410 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 400 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1949922120 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1949922120 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 695282746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 695282746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093049 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1949798453 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1949798453 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 695221170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 695221170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276100593 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276100593 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 971375795 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 971375795 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 971375795 # number of overall hits -system.cpu.dcache.overall_hits::total 971375795 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1954115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1954115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842629 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842629 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 971321763 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 971321763 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 971321763 # number of overall hits +system.cpu.dcache.overall_hits::total 971321763 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953864 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953864 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 835085 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 835085 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2796744 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2796744 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2796744 # number of overall misses -system.cpu.dcache.overall_misses::total 2796744 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80415220057 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80415220057 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 58619966916 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 58619966916 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 211750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 139035186973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 139035186973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 139035186973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 139035186973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 697236861 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 697236861 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2788949 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2788949 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2788949 # number of overall misses +system.cpu.dcache.overall_misses::total 2788949 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 82025897599 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 82025897599 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 54715114042 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 54715114042 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 225000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 136741011641 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 136741011641 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 136741011641 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 136741011641 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 697175034 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 697175034 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 974172539 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 974172539 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 974172539 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 974172539 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 974110712 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 974110712 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 974110712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 974110712 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002803 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002803 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003043 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003015 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003015 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002871 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002871 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41151.733678 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41151.733678 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69567.943800 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69567.943800 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70583.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49713.233307 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49713.233307 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49713.233307 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 939 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002863 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002863 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002863 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002863 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41981.375162 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41981.375162 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65520.412942 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65520.412942 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49029.584851 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 49029.584851 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 49029.584851 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2327 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 933 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.557692 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.550562 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.627451 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.483146 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96313 # number of writebacks -system.cpu.dcache.writebacks::total 96313 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 489564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765848 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks +system.cpu.dcache.writebacks::total 96321 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489326 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 489326 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 758271 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 758271 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1255412 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1255412 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1255412 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1255412 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464551 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464551 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76781 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76781 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541332 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541332 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541332 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541332 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42792151524 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 42792151524 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993494488 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47785646012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47785646012 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47785646012 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47785646012 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1247597 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1247597 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1247597 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1247597 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464538 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464538 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541352 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541352 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541352 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541352 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42911632024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42911632024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4684436204 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4684436204 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47596068228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47596068228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47596068228 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47596068228 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002101 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -1077,14 +1040,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001582 system.cpu.dcache.demand_mshr_miss_rate::total 0.001582 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001582 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001582 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29218.614800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29218.614800 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65035.549003 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31002.824837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31002.824837 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29300.456543 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29300.456543 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60984.146171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60984.146171 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30879.428079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30879.428079 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 391c7c37b..f3edc5948 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043690 # Number of seconds simulated -sim_ticks 43690025000 # Number of ticks simulated -final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043459 # Number of seconds simulated +sim_ticks 43458818000 # Number of ticks simulated +final_tick 43458818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133116 # Simulator instruction rate (inst/s) -host_op_rate 133116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65834414 # Simulator tick rate (ticks/s) -host_mem_usage 238716 # Number of bytes of host memory used -host_seconds 663.64 # Real time elapsed on the host +host_inst_rate 114678 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56415550 # Simulator tick rate (ticks/s) +host_mem_usage 273516 # Number of bytes of host memory used +host_seconds 770.33 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,27 +25,27 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10460294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 233286787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 243747080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167878657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10460294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 233286787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 411625737 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Number of read requests accepted system.physmem.writeReqs 113997 # Number of write requests accepted system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10592576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294400 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10379 # Per bank write bursts @@ -58,10 +58,10 @@ system.physmem.perBankRdBursts::6 9796 # Pe system.physmem.perBankRdBursts::7 10273 # Per bank write bursts system.physmem.perBankRdBursts::8 10509 # Per bank write bursts system.physmem.perBankRdBursts::9 10590 # Per bank write bursts -system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::10 10477 # Per bank write bursts system.physmem.perBankRdBursts::11 10188 # Per bank write bursts -system.physmem.perBankRdBursts::12 10237 # Per bank write bursts -system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::12 10236 # Per bank write bursts +system.physmem.perBankRdBursts::13 10580 # Per bank write bursts system.physmem.perBankRdBursts::14 10468 # Per bank write bursts system.physmem.perBankRdBursts::15 10593 # Per bank write bursts system.physmem.perBankWrBursts::0 7081 # Per bank write bursts @@ -69,20 +69,20 @@ system.physmem.perBankWrBursts::1 7259 # Pe system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 7091 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::7 7092 # Per bank write bursts +system.physmem.perBankWrBursts::8 7216 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7284 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7281 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.totGap 43458797000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,10 +97,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 113997 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 69517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -129,195 +129,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation -system.physmem.totQLat 6031819750 # Total ticks spent queuing -system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks -system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.014950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.118388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.708548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12628 30.21% 30.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8632 20.65% 50.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4415 10.56% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2749 6.58% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 5.41% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1680 4.02% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 3.45% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1629 3.90% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6369 15.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41807 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.954842 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 351.043824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6907 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.496599 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.404036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.150839 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6289 91.03% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.19% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 61 0.88% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 166 2.40% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 127 1.84% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.06% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 63 0.91% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 29 0.42% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.26% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.17% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 19 0.28% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 5 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6909 # Writes before turning the bus around for reads +system.physmem.totQLat 5306478250 # Total ticks spent queuing +system.physmem.totMemAccLat 7800537000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827545000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1666513750 # Total ticks spent accessing banks +system.physmem.avgQLat 32061.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10069.02 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47130.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 243.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 167.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 243.75 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 167.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 151507 # Number of row buffer hits during reads -system.physmem.writeRowHits 76598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes -system.physmem.avgGap 156308.15 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 409447420 # Throughput (bytes/s) +system.physmem.busUtil 3.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144461 # Number of row buffer hits during reads +system.physmem.writeRowHits 82889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.71 # Row buffer hit rate for writes +system.physmem.avgGap 155480.97 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.25 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 411625737 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -329,40 +281,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219845000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1520840750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18742723 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742760 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318400 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507492 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.075947 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277713 # DTB read hits +system.cpu.dtb.read_hits 20277780 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367861 # DTB read accesses -system.cpu.dtb.write_hits 14728970 # DTB write hits +system.cpu.dtb.read_accesses 20367928 # DTB read accesses +system.cpu.dtb.write_hits 14729056 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736222 # DTB write accesses -system.cpu.dtb.data_hits 35006683 # DTB hits +system.cpu.dtb.write_accesses 14736308 # DTB write accesses +system.cpu.dtb.data_hits 35006836 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104083 # DTB accesses -system.cpu.itb.fetch_hits 12367758 # ITB hits +system.cpu.dtb.data_accesses 35104236 # DTB accesses +system.cpu.itb.fetch_hits 12367757 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378779 # ITB accesses +system.cpu.itb.fetch_accesses 12378778 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -376,18 +328,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87380051 # number of cpu cycles simulated +system.cpu.numCycles 86917637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668524 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74162131 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481381 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174243 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). @@ -398,12 +350,12 @@ system.cpu.execution_unit.executions 44777932 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77191042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. -system.cpu.activity 79.624156 # Percentage of cycles cpu is active +system.cpu.timesIdled 229429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17341864 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575773 # Number of cycles cpu stages are processed. +system.cpu.activity 80.047934 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -415,62 +367,62 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.983891 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.983891 # CPI: Total CPI of All Threads +system.cpu.ipc 1.016372 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.016372 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34262012 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655625 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.581059 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44462439 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455198 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.845320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43887105 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030532 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.507250 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64797015 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120622 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.450096 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40875399 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042238 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.972262 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1905.831723 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250503 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1905.831723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930582 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits -system.cpu.icache.overall_hits::total 12250505 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses -system.cpu.icache.overall_misses::total 117242 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 12250503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250503 # number of overall hits +system.cpu.icache.overall_hits::total 12250503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117244 # number of overall misses +system.cpu.icache.overall_misses::total 117244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1999895234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1999895234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1999895234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1999895234 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses @@ -483,106 +435,106 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 343 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30827 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30827 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30827 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30827 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1419611513 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1419611513 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution +system.cpu.toL2Bus.throughput 676121104 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130829487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 323146469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30877.243576 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.905024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1776.684074 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826802 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061276 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054220 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942299 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17071 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17173 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13478 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3980332 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3980332 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980348 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,80 +613,80 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1624855000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2073151500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11301062250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11301062250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448296500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12925917250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13374213750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448296500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12925917250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13374213750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200250 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.081511 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33755026 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 302612000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.081511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995137 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995137 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3118 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits -system.cpu.dcache.overall_hits::total 33754883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses -system.cpu.dcache.overall_misses::total 1135132 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20180293 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574733 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574733 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755026 # number of overall hits +system.cpu.dcache.overall_hits::total 33755026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96345 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038644 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1134989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1134989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1134989 # number of overall misses +system.cpu.dcache.overall_misses::total 1134989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 87156667364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 87156667364 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -745,54 +697,54 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032530 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032530 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032530 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032530 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5467849 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116872 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.784936 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks -system.cpu.dcache.writebacks::total 168351 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks +system.cpu.dcache.writebacks::total 168352 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35578 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35578 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895064 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930642 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930642 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15537149031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15537149031 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -801,14 +753,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 629fb2f13..7573bf6de 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024877 # Number of seconds simulated -sim_ticks 24876941500 # Number of ticks simulated -final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024671 # Number of seconds simulated +sim_ticks 24670906500 # Number of ticks simulated +final_tick 24670906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202143 # Simulator instruction rate (inst/s) -host_op_rate 202143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63181048 # Simulator tick rate (ticks/s) -host_mem_usage 239772 # Number of bytes of host memory used -host_seconds 393.74 # Real time elapsed on the host +host_inst_rate 168282 # Simulator instruction rate (inst/s) +host_op_rate 168282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52161952 # Simulator tick rate (ticks/s) +host_mem_usage 276592 # Number of bytes of host memory used +host_seconds 472.97 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166334 # Number of read requests accepted -system.physmem.writeReqs 114019 # Number of write requests accepted -system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153856 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19834861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 411572068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 431406929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 295777052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19834861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 411572068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 727183981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166300 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10642752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10436 # Per bank write bursts -system.physmem.perBankRdBursts::1 10466 # Per bank write bursts -system.physmem.perBankRdBursts::2 10310 # Per bank write bursts -system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10323 # Per bank write bursts -system.physmem.perBankRdBursts::8 10612 # Per bank write bursts -system.physmem.perBankRdBursts::9 10641 # Per bank write bursts -system.physmem.perBankRdBursts::10 10552 # Per bank write bursts -system.physmem.perBankRdBursts::11 10231 # Per bank write bursts -system.physmem.perBankRdBursts::12 10282 # Per bank write bursts +system.physmem.perBankRdBursts::0 10427 # Per bank write bursts +system.physmem.perBankRdBursts::1 10465 # Per bank write bursts +system.physmem.perBankRdBursts::2 10308 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10424 # Per bank write bursts +system.physmem.perBankRdBursts::5 10403 # Per bank write bursts +system.physmem.perBankRdBursts::6 9851 # Per bank write bursts +system.physmem.perBankRdBursts::7 10318 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10551 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10627 # Per bank write bursts -system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7258 # Per bank write bursts +system.physmem.perBankRdBursts::14 10486 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7082 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7092 # Per bank write bursts -system.physmem.perBankWrBursts::8 7228 # Per bank write bursts +system.physmem.perBankWrBursts::7 7086 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7087 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24876907500 # Total gap between requests +system.physmem.totGap 24670873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166334 # Read request sizes (log2) +system.physmem.readPktSize::6 166300 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 69085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,233 +129,193 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation -system.physmem.totQLat 6294270000 # Total ticks spent queuing -system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks -system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 376.488173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.222062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.745587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13435 31.07% 31.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8988 20.78% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4626 10.70% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2682 6.20% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2451 5.67% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1626 3.76% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1548 3.58% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1315 3.04% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6576 15.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43247 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.949301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.898812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6941 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6943 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.417831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.341311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.942818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6412 92.35% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 48 0.69% 93.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 135 1.94% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 111 1.60% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 69 0.99% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 62 0.89% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.27% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.20% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 10 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6943 # Writes before turning the bus around for reads +system.physmem.totQLat 5579601250 # Total ticks spent queuing +system.physmem.totMemAccLat 7987531250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831465000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1576465000 # Total ticks spent accessing banks +system.physmem.avgQLat 33552.83 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9480.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48032.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 431.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 295.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 431.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 295.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.63 # Data bus utilization in percentage -system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 152220 # Number of row buffer hits during reads -system.physmem.writeRowHits 76017 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 88734.23 # Average gap between requests -system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 721253937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35533 # Transaction distribution -system.membus.trans_dist::ReadResp 35533 # Transaction distribution -system.membus.trans_dist::Writeback 114019 # Transaction distribution -system.membus.trans_dist::ReadExReq 130801 # Transaction distribution -system.membus.trans_dist::ReadExResp 130801 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17942592 # Total data (bytes) +system.physmem.busUtil 5.68 # Data bus utilization in percentage +system.physmem.busUtilRead 3.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144952 # Number of row buffer hits during reads +system.physmem.writeRowHits 82533 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.39 # Row buffer hit rate for writes +system.physmem.avgGap 88010.62 # Average gap between requests +system.physmem.pageHitRate 81.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.46 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 727183981 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35502 # Transaction distribution +system.membus.trans_dist::ReadResp 35502 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130798 # Transaction distribution +system.membus.trans_dist::ReadExResp 130798 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446617 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1535210250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16535475 # Number of BP lookups -system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits +system.cpu.branchPred.lookups 16545461 # Number of BP lookups +system.cpu.branchPred.condPredicted 10688882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 416220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11528806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7341014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.675406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1988101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40517 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22396974 # DTB read hits -system.cpu.dtb.read_misses 220986 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22617960 # DTB read accesses -system.cpu.dtb.write_hits 15703419 # DTB write hits -system.cpu.dtb.write_misses 41132 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15744551 # DTB write accesses -system.cpu.dtb.data_hits 38100393 # DTB hits -system.cpu.dtb.data_misses 262118 # DTB misses -system.cpu.dtb.data_acv 49 # DTB access violations -system.cpu.dtb.data_accesses 38362511 # DTB accesses -system.cpu.itb.fetch_hits 13901400 # ITB hits -system.cpu.itb.fetch_misses 35038 # ITB misses +system.cpu.dtb.read_hits 22395847 # DTB read hits +system.cpu.dtb.read_misses 219375 # DTB read misses +system.cpu.dtb.read_acv 51 # DTB read access violations +system.cpu.dtb.read_accesses 22615222 # DTB read accesses +system.cpu.dtb.write_hits 15705719 # DTB write hits +system.cpu.dtb.write_misses 41176 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15746895 # DTB write accesses +system.cpu.dtb.data_hits 38101566 # DTB hits +system.cpu.dtb.data_misses 260551 # DTB misses +system.cpu.dtb.data_acv 53 # DTB access violations +system.cpu.dtb.data_accesses 38362117 # DTB accesses +system.cpu.itb.fetch_hits 13909771 # ITB hits +system.cpu.itb.fetch_misses 35326 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13936438 # ITB accesses +system.cpu.itb.fetch_accesses 13945097 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,238 +329,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49753887 # number of cpu cycles simulated +system.cpu.numCycles 49341816 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15790710 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105357061 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16545461 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9329115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7570274 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314157 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13909771 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 205601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.358058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120608 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25134834 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1529938 3.42% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370308 3.07% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511826 3.38% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137251 9.26% 75.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1848058 4.14% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674230 1.51% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1068805 2.39% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7404340 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.335323 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.135249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16882265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7097756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18571135 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 780643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1347791 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745694 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106722 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103639332 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302042 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1347791 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17356196 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4802628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85206 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18838214 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249555 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102372003 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2542 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2130672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646955 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123349032 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123030884 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 318147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9100074 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5525 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5523 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4824517 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23234080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16271017 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1195142 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 460766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90738136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88425930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95845 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10681231 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4663960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44679590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.979112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109137 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16474837 36.87% 36.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6839728 15.31% 52.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5595634 12.52% 64.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4775900 10.69% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4713198 10.55% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2628457 5.88% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926364 4.31% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1289803 2.89% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 435669 0.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44679590 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126495 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 783002 42.16% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947503 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49357567 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43846 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38967 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848069 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894942 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued -system.cpu.iq.rate 1.777056 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88425930 # Type of FU issued +system.cpu.iq.rate 1.792109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1857000 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222881148 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101028016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86544064 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603147 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414515 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294050 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89981281 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301649 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467705 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2957442 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4633 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18287 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1657640 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 88581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1347791 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3663804 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77381 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100225939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 227298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23234080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16271017 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5320 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49801 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6534 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18287 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 195800 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87582928 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843002 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478272 # number of nop insts executed -system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed -system.cpu.iew.exec_branches 15081989 # Number of branches executed -system.cpu.iew.exec_stores 15744873 # Number of stores executed -system.cpu.iew.exec_rate 1.760176 # Inst execution rate -system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33348545 # num instructions producing a value -system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value +system.cpu.iew.exec_nop 9482483 # number of nop insts executed +system.cpu.iew.exec_refs 38365741 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084551 # Number of branches executed +system.cpu.iew.exec_stores 15747195 # Number of stores executed +system.cpu.iew.exec_rate 1.775024 # Inst execution rate +system.cpu.iew.wb_sent 87227797 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86838114 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33351220 # num instructions producing a value +system.cpu.iew.wb_consumers 43473707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759929 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767158 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 311933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43331799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038703 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20501224 47.31% 47.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7041698 16.25% 63.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3356099 7.75% 71.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2051116 4.73% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049317 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1167384 2.69% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1102119 2.54% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716210 1.65% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5346632 12.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43331799 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,230 +571,229 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5346632 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133915050 # The number of ROB reads -system.cpu.rob.rob_writes 195770285 # The number of ROB writes -system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133898086 # The number of ROB reads +system.cpu.rob.rob_writes 195811124 # The number of ROB writes +system.cpu.timesIdled 85852 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4662226 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads -system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115901393 # number of integer regfile reads -system.cpu.int_regfile_writes 57502981 # number of integer regfile writes -system.cpu.fp_regfile_reads 249622 # number of floating regfile reads -system.cpu.fp_regfile_writes 240154 # number of floating regfile writes -system.cpu.misc_regfile_reads 38048 # number of misc regfile reads +system.cpu.cpi 0.619936 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619936 # CPI: Total CPI of All Threads +system.cpu.ipc 1.613069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.613069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115913702 # number of integer regfile reads +system.cpu.int_regfile_writes 57508814 # number of integer regfile writes +system.cpu.fp_regfile_reads 249357 # number of floating regfile reads +system.cpu.fp_regfile_writes 240037 # number of floating regfile writes +system.cpu.misc_regfile_reads 38036 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes) +system.cpu.toL2Bus.throughput 1213726946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143419 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580053 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 766814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5976320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29943744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29943744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402865000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141399227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 324564248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91622 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91332 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.493490 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13803368 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.819319 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19891128250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.493490 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940182 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 359 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1527 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 358 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27896466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27896466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits -system.cpu.icache.overall_hits::total 13794941 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses -system.cpu.icache.overall_misses::total 106457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27912922 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27912922 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13803368 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13803368 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13803368 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13803368 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13803368 # number of overall hits +system.cpu.icache.overall_hits::total 13803368 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2000796974 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2000796974 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2000796974 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2000796974 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13909771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13909771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13909771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13909771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007650 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007650 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007650 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007650 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 263 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.916667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12786 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,171 +802,171 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114019 # number of writebacks -system.cpu.l2cache.writebacks::total 114019 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7667 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166335 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7667 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166335 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 500389250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1762290750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2262680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12178041500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12178041500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 500389250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13940332250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440721500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 500389250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13940332250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440721500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448535 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555912 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555912 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks +system.cpu.l2cache.writebacks::total 114017 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27856 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7647 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7647 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158654 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166301 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13800951750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448256 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556297 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771806 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201466 # number of replacements +system.cpu.dcache.tags.tagsinuse 4073.410780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34191132 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205562 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.330022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 225470250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4073.410780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994485 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994485 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1078 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1081 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2933 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71186914 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71186914 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits -system.cpu.dcache.overall_hits::total 34183845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses -system.cpu.dcache.overall_misses::total 1306786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 71201646 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71201646 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20617040 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20617040 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574040 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34191080 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34191080 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34191080 # number of overall hits +system.cpu.dcache.overall_hits::total 34191080 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267573 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267573 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306910 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306910 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306910 # number of overall misses +system.cpu.dcache.overall_misses::total 1306910 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 101058194323 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 101058194323 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20884613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20884613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35497990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35497990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35497990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35497990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036816 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036816 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036816 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036816 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4861037 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 111685 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.524529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks -system.cpu.dcache.writebacks::total 168930 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205428 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205428 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895920 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895920 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62145 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62145 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205562 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205562 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15946980246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15946980246 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9978094b9..e2e70aeb1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026790 # Number of seconds simulated -sim_ticks 26790388000 # Number of ticks simulated -final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026596 # Number of seconds simulated +sim_ticks 26596403000 # Number of ticks simulated +final_tick 26596403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134448 # Simulator instruction rate (inst/s) -host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50797444 # Simulator tick rate (ticks/s) -host_mem_usage 278572 # Number of bytes of host memory used -host_seconds 527.40 # Real time elapsed on the host +host_inst_rate 110554 # Simulator instruction rate (inst/s) +host_op_rate 156889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41466984 # Simulator tick rate (ticks/s) +host_mem_usage 321816 # Number of bytes of host memory used +host_seconds 641.39 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory -system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128754 # Number of read requests accepted -system.physmem.writeReqs 83937 # Number of write requests accepted -system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 297984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11203921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298648505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309852426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 202000248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11203921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298648505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 511852674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128766 # Number of read requests accepted +system.physmem.writeReqs 83945 # Number of write requests accepted +system.physmem.readBursts 128766 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83945 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8131 # Per bank write bursts -system.physmem.perBankRdBursts::1 8390 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8163 # Per bank write bursts -system.physmem.perBankRdBursts::4 8302 # Per bank write bursts -system.physmem.perBankRdBursts::5 8446 # Per bank write bursts -system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7962 # Per bank write bursts -system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts -system.physmem.perBankRdBursts::10 7786 # Per bank write bursts -system.physmem.perBankRdBursts::11 7812 # Per bank write bursts -system.physmem.perBankRdBursts::12 7879 # Per bank write bursts -system.physmem.perBankRdBursts::13 7885 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8010 # Per bank write bursts -system.physmem.perBankWrBursts::0 5179 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 300 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8143 # Per bank write bursts +system.physmem.perBankRdBursts::1 8388 # Per bank write bursts +system.physmem.perBankRdBursts::2 8255 # Per bank write bursts +system.physmem.perBankRdBursts::3 8165 # Per bank write bursts +system.physmem.perBankRdBursts::4 8298 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8084 # Per bank write bursts +system.physmem.perBankRdBursts::7 7964 # Per bank write bursts +system.physmem.perBankRdBursts::8 8055 # Per bank write bursts +system.physmem.perBankRdBursts::9 7611 # Per bank write bursts +system.physmem.perBankRdBursts::10 7782 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7884 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8009 # Per bank write bursts +system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5207 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts -system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::6 5201 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts system.physmem.perBankWrBursts::9 5089 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::10 5246 # Per bank write bursts system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5226 # Per bank write bursts +system.physmem.perBankWrBursts::14 5452 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26790282500 # Total gap between requests +system.physmem.totGap 26596386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128754 # Read request sizes (log2) +system.physmem.readPktSize::6 128766 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83937 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83945 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,219 +129,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation -system.physmem.totQLat 3022726750 # Total ticks spent queuing -system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks -system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 29627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 410.695649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 253.351666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 359.831379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7793 26.30% 26.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6034 20.37% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3130 10.56% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2203 7.44% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2053 6.93% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1365 4.61% 76.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 3.53% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1191 4.02% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4813 16.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 29627 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.322974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 394.325536 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5082 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5084 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.507474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.421096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.063173 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4555 89.59% 89.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 21 0.41% 90.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 58 1.14% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 170 3.34% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 125 2.46% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 1.12% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 23 0.45% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.30% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.20% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 13 0.26% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5084 # Writes before turning the bus around for reads +system.physmem.totQLat 2537399000 # Total ticks spent queuing +system.physmem.totMemAccLat 4590111500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1408907500 # Total ticks spent accessing banks +system.physmem.avgQLat 19706.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10942.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 35648.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 309.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 201.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 309.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 202.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 117872 # Number of row buffer hits during reads -system.physmem.writeRowHits 56933 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes -system.physmem.avgGap 125958.70 # Average gap between requests -system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 508101040 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26500 # Transaction distribution -system.membus.trans_dist::ReadResp 26500 # Transaction distribution -system.membus.trans_dist::Writeback 83937 # Transaction distribution -system.membus.trans_dist::UpgradeReq 308 # Transaction distribution -system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13612224 # Total data (bytes) +system.physmem.busUtil 4.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.58 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 112537 # Number of row buffer hits during reads +system.physmem.writeRowHits 62593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes +system.physmem.avgGap 125035.31 # Average gap between requests +system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 511852674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26511 # Transaction distribution +system.membus.trans_dist::ReadResp 26510 # Transaction distribution +system.membus.trans_dist::Writeback 83945 # Transaction distribution +system.membus.trans_dist::UpgradeReq 300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 300 # Transaction distribution +system.membus.trans_dist::ReadExReq 102255 # Transaction distribution +system.membus.trans_dist::ReadExResp 102255 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342076 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934794000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1201882201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16615535 # Number of BP lookups -system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits +system.cpu.branchPred.lookups 16626299 # Number of BP lookups +system.cpu.branchPred.condPredicted 12761376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10553987 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7772041 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.640805 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112970 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,136 +381,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53580777 # number of cpu cycles simulated +system.cpu.numCycles 53192807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12548027 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85225985 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16626299 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9595932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21195811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2371567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10764095 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 524 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11679981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332376 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25074842 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2134843 4.62% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1965334 4.25% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045724 4.42% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467866 3.17% 70.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377638 2.98% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 956719 2.07% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188096 2.57% 78.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10038787 21.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312567 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.602209 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9109376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19493309 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1372783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638539 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3331010 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104505 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116880506 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361697 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638539 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16346771 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2652791 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1020533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19105290 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5485925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114999580 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17445 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115318587 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529932404 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476522297 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2751 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16185915 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13024660 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29615928 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451967 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3877153 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4417845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111572377 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35991 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107273861 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274045 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10831021 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25918238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2205 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46249849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.319442 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990414 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10978806 23.74% 23.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8116860 17.55% 41.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7434269 16.07% 57.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7097763 15.35% 72.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5421519 11.72% 84.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3913580 8.46% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842525 3.98% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 870168 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574359 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46249849 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113368 4.58% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1353818 54.73% 59.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1006223 40.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56655592 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91505 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 217 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -582,84 +536,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28893939 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21632601 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued -system.cpu.iq.rate 2.001511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107273861 # Type of FU issued +system.cpu.iq.rate 2.016699 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2473411 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023057 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263544444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122467509 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105589962 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 918 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 177 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109746981 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 291 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178933 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2308820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6717 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29962 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1896229 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 670 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638539 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1135526 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46796 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111618146 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29615928 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451967 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6522 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5186 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29962 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573894 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106245086 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28594669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1028775 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9806 # number of nop insts executed -system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599283 # Number of branches executed -system.cpu.iew.exec_stores 21341796 # Number of stores executed -system.cpu.iew.exec_rate 1.982275 # Inst execution rate -system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53316718 # num instructions producing a value -system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value +system.cpu.iew.exec_nop 9778 # number of nop insts executed +system.cpu.iew.exec_refs 49940992 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602318 # Number of branches executed +system.cpu.iew.exec_stores 21346323 # Number of stores executed +system.cpu.iew.exec_rate 1.997358 # Inst execution rate +system.cpu.iew.wb_sent 105809508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105590139 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53305824 # num instructions producing a value +system.cpu.iew.wb_consumers 103866304 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back +system.cpu.iew.wb_rate 1.985045 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513216 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10986690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500884 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44611310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.255760 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.762475 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15517142 34.78% 34.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11686207 26.20% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3450926 7.74% 68.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2867812 6.43% 75.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872959 4.20% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1945129 4.36% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 689747 1.55% 85.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 566134 1.27% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015254 13.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44611310 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -670,243 +624,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015254 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150021199 # The number of ROB reads -system.cpu.rob.rob_writes 224747411 # The number of ROB writes -system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150189875 # The number of ROB reads +system.cpu.rob.rob_writes 224886049 # The number of ROB writes +system.cpu.timesIdled 80066 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6942958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511545132 # number of integer regfile reads -system.cpu.int_regfile_writes 103340839 # number of integer regfile writes -system.cpu.fp_regfile_reads 806 # number of floating regfile reads -system.cpu.fp_regfile_writes 694 # number of floating regfile writes -system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads +system.cpu.cpi 0.750170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750170 # CPI: Total CPI of All Threads +system.cpu.ipc 1.333030 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.333030 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511686083 # number of integer regfile reads +system.cpu.int_regfile_writes 103364033 # number of integer regfile writes +system.cpu.fp_regfile_reads 870 # number of floating regfile reads +system.cpu.fp_regfile_writes 762 # number of floating regfile writes +system.cpu.misc_regfile_reads 49348247 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 778162370 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63123 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 517732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2003904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20664256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20664256 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32064 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291006496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48441979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 259878236 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 29638 # number of replacements -system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29471 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.055358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11644351 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31508 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 369.568078 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits -system.cpu.icache.overall_hits::total 11640118 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses -system.cpu.icache.overall_misses::total 35738 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.055358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 681 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23391772 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23391772 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11644361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11644361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11644361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11644361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11644361 # number of overall hits +system.cpu.icache.overall_hits::total 11644361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35619 # number of overall misses +system.cpu.icache.overall_misses::total 35619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813918226 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813918226 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813918226 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813918226 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11679980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11679980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11679980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11679980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1148 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31984 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31984 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31984 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31984 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671357769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 671357769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002739 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002739 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20990.425494 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20990.425494 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3807 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3807 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3807 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3807 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3807 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3807 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31812 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31812 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31812 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31812 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31812 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31812 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 661574021 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 661574021 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 661574021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 661574021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 661574021 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 661574021 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002724 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002724 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002724 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95620 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29882.992791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 89182 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126734 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.703694 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95635 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29857.974256 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 88990 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126748 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.702102 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26677.610156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.039955 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1839.342681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041688 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056132 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 391 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949524 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2821016 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2821016 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26805 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 60268 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129182 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129182 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26805 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38257 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 65062 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26805 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38257 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.055649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20828 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7917 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2819349 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2819349 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128766 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128766 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303015250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1507731500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1810746750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3014299 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3014299 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6936413750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6936413750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303015250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8444145250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8747160500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303015250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8444145250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8747160500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305814 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.955414 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.955414 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955351 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955351 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.664688 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.664688 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65080.594931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158331 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.839586 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347897 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162427 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 158316 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.473281 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44361466 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162412 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.141554 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 367394250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.473281 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993280 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92273995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92273995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26048802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266579 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 92298894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 92298894 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 26061245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26061245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267715 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits -system.cpu.dcache.overall_hits::total 44315381 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses -system.cpu.dcache.overall_misses::total 1708462 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44328960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44328960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44328960 # number of overall hits +system.cpu.dcache.overall_hits::total 44328960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125143 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125143 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582186 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707329 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707329 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707329 # number of overall misses +system.cpu.dcache.overall_misses::total 1707329 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 127390955178 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 127390955178 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26186388 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26186388 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16033 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16033 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46036289 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46036289 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46036289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46036289 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4179 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1300 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 140 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.850000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks -system.cpu.dcache.writebacks::total 129182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 129156 # number of writebacks +system.cpu.dcache.writebacks::total 129156 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69730 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69730 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544602 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107314 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162727 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162727 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 01fe4f841..f20aedd28 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009838 # Number of seconds simulated -sim_ticks 1009838214500 # Number of ticks simulated -final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.007337 # Number of seconds simulated +sim_ticks 1007336591500 # Number of ticks simulated +final_tick 1007336591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128161 # Simulator instruction rate (inst/s) -host_op_rate 128161 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71119760 # Simulator tick rate (ticks/s) -host_mem_usage 230508 # Number of bytes of host memory used -host_seconds 14199.12 # Real time elapsed on the host +host_inst_rate 109896 # Simulator instruction rate (inst/s) +host_op_rate 109896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60832901 # Simulator tick rate (ticks/s) +host_mem_usage 265436 # Number of bytes of host memory used +host_seconds 16559.08 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,64 +25,64 @@ system.physmem.num_reads::cpu.data 1958829 # Nu system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 124143704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 124198144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54440 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 64520751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 64520751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 64520751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 124143704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 188718895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 124452002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 124506578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64680982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64680982 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64680982 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 124452002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 189187560 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1959688 # Number of read requests accepted system.physmem.writeReqs 1018055 # Number of write requests accepted system.physmem.readBursts 1959688 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1018055 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125384704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35328 # Total number of bytes read from write queue -system.physmem.bytesWritten 65154176 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 125336064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83968 # Total number of bytes read from write queue +system.physmem.bytesWritten 65153920 # Total number of bytes written to DRAM system.physmem.bytesReadSys 125420032 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 65155520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1312 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118719 # Per bank write bursts -system.physmem.perBankRdBursts::1 114075 # Per bank write bursts -system.physmem.perBankRdBursts::2 116210 # Per bank write bursts -system.physmem.perBankRdBursts::3 117697 # Per bank write bursts -system.physmem.perBankRdBursts::4 117769 # Per bank write bursts -system.physmem.perBankRdBursts::5 117504 # Per bank write bursts -system.physmem.perBankRdBursts::6 119870 # Per bank write bursts -system.physmem.perBankRdBursts::7 124481 # Per bank write bursts -system.physmem.perBankRdBursts::8 126964 # Per bank write bursts -system.physmem.perBankRdBursts::9 130062 # Per bank write bursts -system.physmem.perBankRdBursts::10 128627 # Per bank write bursts -system.physmem.perBankRdBursts::11 130265 # Per bank write bursts -system.physmem.perBankRdBursts::12 125943 # Per bank write bursts -system.physmem.perBankRdBursts::13 125205 # Per bank write bursts -system.physmem.perBankRdBursts::14 122569 # Per bank write bursts -system.physmem.perBankRdBursts::15 123176 # Per bank write bursts +system.physmem.perBankRdBursts::0 118685 # Per bank write bursts +system.physmem.perBankRdBursts::1 114026 # Per bank write bursts +system.physmem.perBankRdBursts::2 116162 # Per bank write bursts +system.physmem.perBankRdBursts::3 117671 # Per bank write bursts +system.physmem.perBankRdBursts::4 117731 # Per bank write bursts +system.physmem.perBankRdBursts::5 117464 # Per bank write bursts +system.physmem.perBankRdBursts::6 119807 # Per bank write bursts +system.physmem.perBankRdBursts::7 124441 # Per bank write bursts +system.physmem.perBankRdBursts::8 126920 # Per bank write bursts +system.physmem.perBankRdBursts::9 130015 # Per bank write bursts +system.physmem.perBankRdBursts::10 128574 # Per bank write bursts +system.physmem.perBankRdBursts::11 130216 # Per bank write bursts +system.physmem.perBankRdBursts::12 125899 # Per bank write bursts +system.physmem.perBankRdBursts::13 125145 # Per bank write bursts +system.physmem.perBankRdBursts::14 122505 # Per bank write bursts +system.physmem.perBankRdBursts::15 123115 # Per bank write bursts system.physmem.perBankWrBursts::0 61223 # Per bank write bursts system.physmem.perBankWrBursts::1 61467 # Per bank write bursts system.physmem.perBankWrBursts::2 60558 # Per bank write bursts -system.physmem.perBankWrBursts::3 61216 # Per bank write bursts +system.physmem.perBankWrBursts::3 61215 # Per bank write bursts system.physmem.perBankWrBursts::4 61647 # Per bank write bursts -system.physmem.perBankWrBursts::5 63084 # Per bank write bursts -system.physmem.perBankWrBursts::6 64137 # Per bank write bursts +system.physmem.perBankWrBursts::5 63083 # Per bank write bursts +system.physmem.perBankWrBursts::6 64136 # Per bank write bursts system.physmem.perBankWrBursts::7 65614 # Per bank write bursts system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65770 # Per bank write bursts -system.physmem.perBankWrBursts::10 65297 # Per bank write bursts -system.physmem.perBankWrBursts::11 65611 # Per bank write bursts -system.physmem.perBankWrBursts::12 64149 # Per bank write bursts -system.physmem.perBankWrBursts::13 64192 # Per bank write bursts -system.physmem.perBankWrBursts::14 64551 # Per bank write bursts +system.physmem.perBankWrBursts::9 65769 # Per bank write bursts +system.physmem.perBankWrBursts::10 65294 # Per bank write bursts +system.physmem.perBankWrBursts::11 65608 # Per bank write bursts +system.physmem.perBankWrBursts::12 64146 # Per bank write bursts +system.physmem.perBankWrBursts::13 64202 # Per bank write bursts +system.physmem.perBankWrBursts::14 64550 # Per bank write bursts system.physmem.perBankWrBursts::15 64186 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1009838141500 # Total gap between requests +system.physmem.totGap 1007336518500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,10 +97,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1018055 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1662258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1664981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 198590 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23846 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -129,234 +129,213 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 48930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1862398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 102.290110 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.389553 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 186.671437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1500560 80.57% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 201450 10.82% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59792 3.21% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 29273 1.57% 96.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16605 0.89% 97.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10399 0.56% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7221 0.39% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6896 0.37% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4046 0.22% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3343 0.18% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 3041 0.16% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 2820 0.15% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1620 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1539 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1515 0.08% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1490 0.08% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1330 0.07% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1307 0.07% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 969 0.05% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 1340 0.07% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 596 0.03% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2192 0.12% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 189 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 700 0.04% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 112 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 81 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 79 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 79 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 66 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 52 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 55 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 71 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 36 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 40 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 43 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 52 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 33 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 28 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 29 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 30 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 34 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 22 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 20 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 16 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 18 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 13 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 16 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 25 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 22 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 13 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 14 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 106 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 15 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 8 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 5 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 14 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 9 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 64 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 154 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1862398 # Bytes accessed per row activation -system.physmem.totQLat 23048924250 # Total ticks spent queuing -system.physmem.totMemAccLat 84969451750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9795680000 # Total ticks spent in databus transfers -system.physmem.totBankLat 52124847500 # Total ticks spent accessing banks -system.physmem.avgQLat 11764.84 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26606.04 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 56821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 58536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 64811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 64584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 72712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1266500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 109.102187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.148932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 142.836675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 979529 77.34% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 199046 15.72% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 36524 2.88% 95.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14982 1.18% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8864 0.70% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4419 0.35% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2809 0.22% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2238 0.18% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18089 1.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1266500 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58142 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.680816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.230571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58099 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58142 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58142 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.509374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.424358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.849185 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29010 49.90% 49.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1046 1.80% 51.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 6657 11.45% 63.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 16493 28.37% 91.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3312 5.70% 97.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1061 1.82% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 264 0.45% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 97 0.17% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 56 0.10% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 18 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 13 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 5 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 28 0.05% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 9 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::59 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58142 # Writes before turning the bus around for reads +system.physmem.totQLat 19659284500 # Total ticks spent queuing +system.physmem.totMemAccLat 80383790750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9791880000 # Total ticks spent in databus transfers +system.physmem.totBankLat 50932626250 # Total ticks spent accessing banks +system.physmem.avgQLat 10038.56 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26007.58 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43370.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 124.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 64.52 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 124.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 64.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41046.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 124.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 64.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 124.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 64.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.47 # Data bus utilization in percentage +system.physmem.busUtil 1.48 # Data bus utilization in percentage system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.50 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.29 # Average write queue length when enqueuing -system.physmem.readRowHits 771409 # Number of row buffer hits during reads -system.physmem.writeRowHits 343363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.73 # Row buffer hit rate for writes -system.physmem.avgGap 339128.71 # Average gap between requests -system.physmem.pageHitRate 37.44 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.16 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 188718895 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1178392 # Transaction distribution -system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 753336 # Number of row buffer hits during reads +system.physmem.writeRowHits 422191 # Number of row buffer hits during writes +system.physmem.readRowHitRate 38.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.47 # Row buffer hit rate for writes +system.physmem.avgGap 338288.60 # Average gap between requests +system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.29 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 189187560 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178393 # Transaction distribution +system.membus.trans_dist::ReadResp 1178393 # Transaction distribution system.membus.trans_dist::Writeback 1018055 # Transaction distribution -system.membus.trans_dist::ReadExReq 781296 # Transaction distribution -system.membus.trans_dist::ReadExResp 781296 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937431 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 4937431 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 190575552 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 190575552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11785228500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11782666500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18347417750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 326538257 # Number of BP lookups -system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220428800 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135446379 # Number of BTB hits +system.cpu.branchPred.lookups 326511183 # Number of BP lookups +system.cpu.branchPred.condPredicted 252559725 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138218265 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220270477 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135614039 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.446771 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.567052 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444831817 # DTB read hits +system.cpu.dtb.read_hits 444830139 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449728895 # DTB read accesses -system.cpu.dtb.write_hits 160846718 # DTB write hits +system.cpu.dtb.read_accesses 449727217 # DTB read accesses +system.cpu.dtb.write_hits 160844128 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162548022 # DTB write accesses -system.cpu.dtb.data_hits 605678535 # DTB hits +system.cpu.dtb.write_accesses 162545432 # DTB write accesses +system.cpu.dtb.data_hits 605674267 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612276917 # DTB accesses -system.cpu.itb.fetch_hits 231928870 # ITB hits +system.cpu.dtb.data_accesses 612272649 # DTB accesses +system.cpu.itb.fetch_hits 232118114 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231928892 # ITB accesses +system.cpu.itb.fetch_accesses 232118136 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -370,34 +349,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019676430 # number of cpu cycles simulated +system.cpu.numCycles 2014673184 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172263299 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154274958 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667627607 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172428181 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154083002 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667622783 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043830224 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043825400 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 231 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651720859 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884928 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120516333 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11119574 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131635907 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83564055 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.169113 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139356886 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 576 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651695392 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617886274 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120493688 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11126119 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131619807 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83580161 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.161629 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139354623 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1742060649 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742144730 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7515544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 447943086 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571733344 # Number of cycles cpu stages are processed. -system.cpu.activity 77.821047 # Percentage of cycles cpu is active +system.cpu.timesIdled 7512368 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 442846963 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571826221 # Number of cycles cpu stages are processed. +system.cpu.activity 78.018918 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -409,78 +388,78 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.109846 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.107097 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.109846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901026 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.107097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.903263 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.901026 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 833031386 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186645044 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 58.754216 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1085876271 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933800159 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.235137 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1047285367 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972391063 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.145884 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1610051904 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409624526 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.281691 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 998329594 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021346836 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.569825 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.903263 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 827756857 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186916327 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.913591 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1081059316 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933613868 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.340711 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1042290381 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972382803 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.265039 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1605047974 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409625210 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.332092 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 993337465 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021335719 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.694858 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 668.332859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 231927731 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 668.288600 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 232116975 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 269997.358556 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 270217.665891 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 668.288600 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.326313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.326313 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 463858599 # Number of tag accesses -system.cpu.icache.tags.data_accesses 463858599 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231927731 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231927731 # number of overall hits -system.cpu.icache.overall_hits::total 231927731 # number of overall hits +system.cpu.icache.tags.tag_accesses 464237087 # Number of tag accesses +system.cpu.icache.tags.data_accesses 464237087 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 232116975 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232116975 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232116975 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232116975 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232116975 # number of overall hits +system.cpu.icache.overall_hits::total 232116975 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses system.cpu.icache.overall_misses::total 1139 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 82716500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 82716500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 82716500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 82716500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 82716500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 82716500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231928870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231928870 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231928870 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231928870 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231928870 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231928870 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81449500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81449500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81449500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81449500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81449500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81449500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232118114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232118114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232118114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232118114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232118114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232118114 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72622.036874 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72622.036874 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72622.036874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72622.036874 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72622.036874 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71509.657594 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71509.657594 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71509.657594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71509.657594 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71509.657594 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -501,134 +480,134 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 65136250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 65136250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 65136250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 65136250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 65136250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 65136250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 63326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 63326500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 63326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 63326500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 63326500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 63326500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75827.997672 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75827.997672 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75827.997672 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75827.997672 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73721.187427 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73721.187427 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73721.187427 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73721.187427 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 811573074 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7222683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7222683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3693280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution +system.cpu.toL2Bus.throughput 813589109 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7222688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7222688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889624 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889624 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21917892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21917907 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819502528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 819557504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 819557504 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 819558080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819558080 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10096073000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10096080500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1445250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1443000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13991718500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13971303500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.l2cache.tags.replacements 1926957 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30919.698369 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8958682 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30916.680897 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8958690 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956750 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.578348 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 67892812750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14931.951876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.659960 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15953.086532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 4.578352 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 67897094750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.990701 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.739406 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15954.950790 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455536 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001060 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.486906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943502 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 613 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 725 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 586 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106291061 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106291061 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693280 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7152618 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7152618 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7152618 # number of overall hits -system.cpu.l2cache.overall_hits::total 7152618 # number of overall hits +system.cpu.l2cache.tags.tag_accesses 106291134 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106291134 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6044295 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044295 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693283 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693283 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108329 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108329 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7152624 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7152624 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7152624 # number of overall hits +system.cpu.l2cache.overall_hits::total 7152624 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177533 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178392 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 781295 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 781295 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1958829 # 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number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 64273250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169308019250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 169372292500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 62463500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95853275750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 95915739250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68840007000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 68840007000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 62463500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164693282750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 164755746250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 62463500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164693282750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 164755746250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221824 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222683 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693280 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693280 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889623 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889623 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221829 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222688 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693283 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693283 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889624 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889624 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111447 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112312 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111447 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112312 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163152 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.413466 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214986 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.215060 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214986 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.215060 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74823.341094 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83366.384636 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83360.157104 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91055.566968 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91055.566968 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86428.192906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74823.341094 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86433.281951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86428.192906 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72716.530850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81401.705386 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81395.374251 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88110.133816 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88110.133816 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84072.437169 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72716.530850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84077.417044 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84072.437169 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,91 +619,91 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177533 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178392 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781295 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 781295 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53491750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144747564750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 144801056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53491750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144747564750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 144801056500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51686000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81095366750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 81147052750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59075528500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59075528500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51686000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140170895250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 140222581250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51686000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140170895250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 140222581250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413466 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62272.118743 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70818.922272 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70812.691999 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78530.987935 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78530.987935 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62272.118743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73894.946802 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73889.852109 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60169.965076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68868.811219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68862.470118 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75612.321210 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75612.321210 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60169.965076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71558.515445 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71553.523444 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107351 # number of replacements -system.cpu.dcache.tags.tagsinuse 4082.357931 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 593283202 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111447 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.114049 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 12709353000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9107357 # number of replacements +system.cpu.dcache.tags.tagsinuse 4082.325879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 593298406 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111453 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.115674 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 12706876000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4082.325879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996662 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996662 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 590 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2876 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 560 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2879 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 619 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219759777 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219759777 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156014425 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593283202 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593283202 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593283202 # number of overall hits -system.cpu.dcache.overall_hits::total 593283202 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326886 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326886 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4714077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4714077 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 12040963 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12040963 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12040963 # number of overall misses -system.cpu.dcache.overall_misses::total 12040963 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183066004000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183066004000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 258278135000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 258278135000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 441344139000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 441344139000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 441344139000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 441344139000 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 1219759783 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219759783 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437268768 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268768 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156029638 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156029638 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593298406 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593298406 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593298406 # number of overall hits +system.cpu.dcache.overall_hits::total 593298406 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326895 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326895 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4698864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4698864 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 12025759 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12025759 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12025759 # number of overall misses +system.cpu.dcache.overall_misses::total 12025759 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180765205750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180765205750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 250221551250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 250221551250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 430986757000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 430986757000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 430986757000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 430986757000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -735,54 +714,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029329 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029329 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019892 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019892 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019892 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019892 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24985.512809 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24985.512809 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54788.696706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54788.696706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36653.558274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36653.558274 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36653.558274 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12098433 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7855784 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 422647 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 73423 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.625385 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 106.993503 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029235 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029235 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24671.461206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24671.461206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53251.498926 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53251.498926 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35838.632472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35838.632472 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35838.632472 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11447989 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7764770 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 416735 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73422 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.470668 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105.755359 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks -system.cpu.dcache.writebacks::total 3693280 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104620 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104620 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2824896 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2824896 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2929516 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2929516 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2929516 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2929516 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222266 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222266 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889181 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889181 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111447 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111447 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111447 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111447 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 165959957500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 165959957500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84276720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84276720000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 250236677500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 250236677500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 250236677500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 250236677500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693283 # number of writebacks +system.cpu.dcache.writebacks::total 3693283 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809682 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2809682 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2914306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2914306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2914306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2914306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222271 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222271 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111453 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111453 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111453 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111453 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 163647011750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 163647011750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81975016250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81975016250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245622028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 245622028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245622028000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 245622028000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -791,14 +770,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22978.931751 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22978.931751 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44610.188224 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44610.188224 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27463.988706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27463.988706 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22658.663978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22658.663978 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43391.804628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43391.804628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26957.503704 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26957.503704 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 09d12ecba..2f4d3475f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.685387 # Number of seconds simulated -sim_ticks 685386545000 # Number of ticks simulated -final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.682192 # Number of seconds simulated +sim_ticks 682191807000 # Number of ticks simulated +final_tick 682191807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166100 # Simulator instruction rate (inst/s) -host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65575812 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used -host_seconds 10451.82 # Real time elapsed on the host +host_inst_rate 139307 # Simulator instruction rate (inst/s) +host_op_rate 139307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54741914 # Simulator tick rate (ticks/s) +host_mem_usage 268504 # Number of bytes of host memory used +host_seconds 12461.96 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory -system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65263104 # Number of bytes written to this memory -system.physmem.bytes_written::total 65263104 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966466 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019736 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019736 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 183534481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 183624591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 95220871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 95220871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 183534481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278845462 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966466 # Number of read requests accepted -system.physmem.writeReqs 1019736 # Number of write requests accepted -system.physmem.readBursts 1966466 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1019736 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125817344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36480 # Total number of bytes read from write queue -system.physmem.bytesWritten 65263104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125853824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65263104 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 570 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125800064 # Number of bytes read from this memory +system.physmem.bytes_read::total 125861760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65265984 # Number of bytes written to this memory +system.physmem.bytes_written::total 65265984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 964 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965626 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966590 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019781 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019781 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 184405709 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 184496147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95671017 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95671017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 184405709 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 280167164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966590 # Number of read requests accepted +system.physmem.writeReqs 1019781 # Number of write requests accepted +system.physmem.readBursts 1966590 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1019781 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125780416 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65264896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125861760 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65265984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119017 # Per bank write bursts -system.physmem.perBankRdBursts::1 114428 # Per bank write bursts -system.physmem.perBankRdBursts::2 116569 # Per bank write bursts -system.physmem.perBankRdBursts::3 118023 # Per bank write bursts -system.physmem.perBankRdBursts::4 118127 # Per bank write bursts -system.physmem.perBankRdBursts::5 117816 # Per bank write bursts -system.physmem.perBankRdBursts::6 120202 # Per bank write bursts -system.physmem.perBankRdBursts::7 124913 # Per bank write bursts -system.physmem.perBankRdBursts::8 127544 # Per bank write bursts -system.physmem.perBankRdBursts::9 130446 # Per bank write bursts -system.physmem.perBankRdBursts::10 129104 # Per bank write bursts -system.physmem.perBankRdBursts::11 130773 # Per bank write bursts -system.physmem.perBankRdBursts::12 126663 # Per bank write bursts -system.physmem.perBankRdBursts::13 125636 # Per bank write bursts -system.physmem.perBankRdBursts::14 122981 # Per bank write bursts -system.physmem.perBankRdBursts::15 123654 # Per bank write bursts -system.physmem.perBankWrBursts::0 61274 # Per bank write bursts -system.physmem.perBankWrBursts::1 61571 # Per bank write bursts -system.physmem.perBankWrBursts::2 60654 # Per bank write bursts -system.physmem.perBankWrBursts::3 61312 # Per bank write bursts -system.physmem.perBankWrBursts::4 61747 # Per bank write bursts -system.physmem.perBankWrBursts::5 63190 # Per bank write bursts -system.physmem.perBankWrBursts::6 64213 # Per bank write bursts -system.physmem.perBankWrBursts::7 65700 # Per bank write bursts -system.physmem.perBankWrBursts::8 65483 # Per bank write bursts -system.physmem.perBankWrBursts::9 65878 # Per bank write bursts -system.physmem.perBankWrBursts::10 65419 # Per bank write bursts -system.physmem.perBankWrBursts::11 65720 # Per bank write bursts -system.physmem.perBankWrBursts::12 64327 # Per bank write bursts -system.physmem.perBankWrBursts::13 64305 # Per bank write bursts -system.physmem.perBankWrBursts::14 64649 # Per bank write bursts -system.physmem.perBankWrBursts::15 64294 # Per bank write bursts +system.physmem.perBankRdBursts::0 118991 # Per bank write bursts +system.physmem.perBankRdBursts::1 114394 # Per bank write bursts +system.physmem.perBankRdBursts::2 116519 # Per bank write bursts +system.physmem.perBankRdBursts::3 118029 # Per bank write bursts +system.physmem.perBankRdBursts::4 118142 # Per bank write bursts +system.physmem.perBankRdBursts::5 117777 # Per bank write bursts +system.physmem.perBankRdBursts::6 120156 # Per bank write bursts +system.physmem.perBankRdBursts::7 124892 # Per bank write bursts +system.physmem.perBankRdBursts::8 127514 # Per bank write bursts +system.physmem.perBankRdBursts::9 130376 # Per bank write bursts +system.physmem.perBankRdBursts::10 129025 # Per bank write bursts +system.physmem.perBankRdBursts::11 130742 # Per bank write bursts +system.physmem.perBankRdBursts::12 126628 # Per bank write bursts +system.physmem.perBankRdBursts::13 125605 # Per bank write bursts +system.physmem.perBankRdBursts::14 122932 # Per bank write bursts +system.physmem.perBankRdBursts::15 123597 # Per bank write bursts +system.physmem.perBankWrBursts::0 61284 # Per bank write bursts +system.physmem.perBankWrBursts::1 61572 # Per bank write bursts +system.physmem.perBankWrBursts::2 60658 # Per bank write bursts +system.physmem.perBankWrBursts::3 61323 # Per bank write bursts +system.physmem.perBankWrBursts::4 61765 # Per bank write bursts +system.physmem.perBankWrBursts::5 63192 # Per bank write bursts +system.physmem.perBankWrBursts::6 64214 # Per bank write bursts +system.physmem.perBankWrBursts::7 65706 # Per bank write bursts +system.physmem.perBankWrBursts::8 65482 # Per bank write bursts +system.physmem.perBankWrBursts::9 65855 # Per bank write bursts +system.physmem.perBankWrBursts::10 65405 # Per bank write bursts +system.physmem.perBankWrBursts::11 65740 # Per bank write bursts +system.physmem.perBankWrBursts::12 64329 # Per bank write bursts +system.physmem.perBankWrBursts::13 64310 # Per bank write bursts +system.physmem.perBankWrBursts::14 64647 # Per bank write bursts +system.physmem.perBankWrBursts::15 64282 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 685386422500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 682191684500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1966466 # Read request sizes (log2) +system.physmem.readPktSize::6 1966590 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1019736 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1645035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 231982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 68923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019781 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1642976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 230548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,235 +129,203 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 45483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 45666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 45709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 45692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 45696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 45650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 45697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 45706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 45762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 45739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 45791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 45957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 46127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 46326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 49473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 48655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1821867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.857955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 80.098310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 197.882118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1460616 80.17% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 186071 10.21% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71892 3.95% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 32365 1.78% 96.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 16766 0.92% 97.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 10653 0.58% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 7007 0.38% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 6870 0.38% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 3886 0.21% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3166 0.17% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2723 0.15% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1980 0.11% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1594 0.09% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1502 0.08% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1242 0.07% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1240 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1003 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1017 0.06% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 831 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 807 0.04% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 751 0.04% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2873 0.16% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 389 0.02% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 742 0.04% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 289 0.02% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 237 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 196 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 198 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 161 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 132 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 165 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 370 0.02% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 134 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 101 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 73 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 67 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 51 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 72 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 49 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 40 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 35 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 42 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 34 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 27 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 45 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 23 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 19 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 28 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 35 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 14 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 19 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 11 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 24 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 17 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 8 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 22 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 8 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 12 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 26 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 4 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 11 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 14 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 22 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 7 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 17 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 89 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 28 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 7 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 123 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1821867 # Bytes accessed per row activation -system.physmem.totQLat 24443368500 # Total ticks spent queuing -system.physmem.totMemAccLat 84807426000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9829480000 # Total ticks spent in databus transfers -system.physmem.totBankLat 50534577500 # Total ticks spent accessing banks -system.physmem.avgQLat 12433.70 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 25705.62 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 57221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 59586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 64812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 65271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 73465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 60584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 17452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1251998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 113.111439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.586325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 150.844327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 955672 76.33% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 201584 16.10% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38062 3.04% 95.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16101 1.29% 96.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9606 0.77% 97.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4835 0.39% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3234 0.26% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2576 0.21% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20328 1.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1251998 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 58888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.373692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.339848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 58850 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 58888 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 58888 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.317009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.233410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.918536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 34047 57.82% 57.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 20086 34.11% 91.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 4266 7.24% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 290 0.49% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 84 0.14% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 30 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 12 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 19 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 9 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 4 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-65 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::78-79 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::86-87 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-105 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::106-107 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 58888 # Writes before turning the bus around for reads +system.physmem.totQLat 20653307250 # Total ticks spent queuing +system.physmem.totMemAccLat 80037239750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9826595000 # Total ticks spent in databus transfers +system.physmem.totBankLat 49557337500 # Total ticks spent accessing banks +system.physmem.avgQLat 10508.88 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 25215.93 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43139.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 183.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 95.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 183.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 95.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40724.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 184.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 184.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.18 # Data bus utilization in percentage -system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 819101 # Number of row buffer hits during reads -system.physmem.writeRowHits 344664 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 229517.77 # Average gap between requests -system.physmem.pageHitRate 38.98 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 7.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 278845462 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1191273 # Transaction distribution -system.membus.trans_dist::ReadResp 1191273 # Transaction distribution -system.membus.trans_dist::Writeback 1019736 # Transaction distribution -system.membus.trans_dist::ReadExReq 775193 # Transaction distribution -system.membus.trans_dist::ReadExResp 775193 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4952668 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 191116928 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 191116928 # Total data (bytes) +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.busUtilRead 1.44 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.29 # Average write queue length when enqueuing +system.physmem.readRowHits 797879 # Number of row buffer hits during reads +system.physmem.writeRowHits 422825 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.46 # Row buffer hit rate for writes +system.physmem.avgGap 228435.01 # Average gap between requests +system.physmem.pageHitRate 40.89 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 7.23 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 280167164 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191439 # Transaction distribution +system.membus.trans_dist::ReadResp 1191439 # Transaction distribution +system.membus.trans_dist::Writeback 1019781 # Transaction distribution +system.membus.trans_dist::ReadExReq 775151 # Transaction distribution +system.membus.trans_dist::ReadExResp 775151 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4952961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4952961 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 191127744 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191127744 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11873404000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 11872683000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 18474077250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 381642976 # Number of BP lookups -system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262443817 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259723367 # Number of BTB hits +system.cpu.branchPred.lookups 381618384 # Number of BP lookups +system.cpu.branchPred.condPredicted 296575373 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16092188 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262164042 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259697812 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.963416 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24699577 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3003 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.059280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24705469 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3069 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613972689 # DTB read hits -system.cpu.dtb.read_misses 11257711 # DTB read misses +system.cpu.dtb.read_hits 613976008 # DTB read hits +system.cpu.dtb.read_misses 11261750 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625230400 # DTB read accesses -system.cpu.dtb.write_hits 212364531 # DTB write hits -system.cpu.dtb.write_misses 7123508 # DTB write misses +system.cpu.dtb.read_accesses 625237758 # DTB read accesses +system.cpu.dtb.write_hits 212363538 # DTB write hits +system.cpu.dtb.write_misses 7134748 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219488039 # DTB write accesses -system.cpu.dtb.data_hits 826337220 # DTB hits -system.cpu.dtb.data_misses 18381219 # DTB misses +system.cpu.dtb.write_accesses 219498286 # DTB write accesses +system.cpu.dtb.data_hits 826339546 # DTB hits +system.cpu.dtb.data_misses 18396498 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844718439 # DTB accesses -system.cpu.itb.fetch_hits 391054896 # ITB hits -system.cpu.itb.fetch_misses 42 # ITB misses +system.cpu.dtb.data_accesses 844736044 # DTB accesses +system.cpu.itb.fetch_hits 391110222 # ITB hits +system.cpu.itb.fetch_misses 44 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 391054938 # ITB accesses +system.cpu.itb.fetch_accesses 391110266 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -371,138 +339,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1370773091 # number of cpu cycles simulated +system.cpu.numCycles 1364383615 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402523002 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3161115412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381642976 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284422944 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574525052 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140645567 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 190952168 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 27 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1444 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 391054896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8064214 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.460399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.144459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402585287 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3161125101 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381618384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284403281 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574536383 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140665925 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 188120516 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1448 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 4 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391110222 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8062763 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.465662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.145744 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 710272753 55.28% 55.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42667609 3.32% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21782496 1.70% 60.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39699327 3.09% 63.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129330544 10.07% 73.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61540269 4.79% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38580495 3.00% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28116157 2.19% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212808155 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 707522863 55.19% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42675531 3.33% 58.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21787283 1.70% 60.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39707555 3.10% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129310443 10.09% 73.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61549431 4.80% 78.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38571496 3.01% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28142716 2.20% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212791928 16.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1284797805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.278414 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.306082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434521910 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 172167391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542471492 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18841651 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116795361 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58349498 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 879 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3088463521 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116795361 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 457475867 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116907635 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535572514 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 58038630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3006337354 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 608843 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1808950 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 51752219 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2247576032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3898866654 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3898722180 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 144473 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1282059246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.279700 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.316889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434597074 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 169317553 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542454813 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18875119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116814687 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58354170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 898 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3088496267 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2037 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116814687 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457547940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 113953082 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6967 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535589228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 58147342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3006454755 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 609106 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1833248 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51828481 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2247677853 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3898974365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3898830865 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143499 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 871373069 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 156 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 123546719 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679659315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255464076 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67507479 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36716823 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2724801247 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 120 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2509489521 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3207288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 979575578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 416138423 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1284797805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953217 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.971436 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 871474890 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 178 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 177 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123676155 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679702242 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255475560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67614908 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 37053481 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2724914461 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509610552 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3196332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 979670705 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416123894 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1282059246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.957484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.971278 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442944970 34.48% 34.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203642722 15.85% 50.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185470521 14.44% 64.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153370563 11.94% 76.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133097213 10.36% 87.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80758631 6.29% 93.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65098641 5.07% 98.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15296137 1.19% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5118407 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 440049739 34.32% 34.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203670606 15.89% 50.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185671301 14.48% 64.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153363283 11.96% 76.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133052268 10.38% 87.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80767651 6.30% 93.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65047769 5.07% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15319478 1.19% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5117151 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1284797805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1282059246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2193136 11.83% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11923525 64.32% 76.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4420966 23.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2188252 11.81% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11925862 64.39% 76.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4407339 23.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643778581 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 107 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643881644 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 99 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 275 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 160 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 33 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 265 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 23 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -524,84 +493,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641602507 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224107818 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641614566 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224113754 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2509489521 # Type of FU issued -system.cpu.iq.rate 1.830711 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18537627 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007387 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6323623582 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3703265011 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2413078875 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1898180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1217876 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 850894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2527088869 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 938279 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62595515 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509610552 # Type of FU issued +system.cpu.iq.rate 1.839373 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18521453 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007380 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6321098058 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3703474382 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413201675 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1900077 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1218284 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 852187 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527192648 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 939357 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62588107 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 235063652 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 262733 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 107683 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94735574 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235106579 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263309 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 109146 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94747058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 113 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1541249 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 184 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1530387 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116795361 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 56591518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1298088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2866959659 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8943399 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679659315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255464076 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 120 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 282702 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 18018 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 107683 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10360004 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8558145 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18918149 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2462143246 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625230973 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47346275 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116814687 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 54760955 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1302145 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867095326 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8936600 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679702242 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255475560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 285836 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 18373 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 109146 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10363389 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8561306 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462265598 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625238282 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47344954 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142158292 # number of nop insts executed -system.cpu.iew.exec_refs 844719037 # number of memory reference insts executed -system.cpu.iew.exec_branches 300873221 # Number of branches executed -system.cpu.iew.exec_stores 219488064 # Number of stores executed -system.cpu.iew.exec_rate 1.796171 # Inst execution rate -system.cpu.iew.wb_sent 2441862108 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413929769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388272639 # num instructions producing a value -system.cpu.iew.wb_consumers 1764258225 # num instructions consuming a value +system.cpu.iew.exec_nop 142180734 # number of nop insts executed +system.cpu.iew.exec_refs 844736593 # number of memory reference insts executed +system.cpu.iew.exec_branches 300891924 # Number of branches executed +system.cpu.iew.exec_stores 219498311 # Number of stores executed +system.cpu.iew.exec_rate 1.804673 # Inst execution rate +system.cpu.iew.wb_sent 2442007403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414053862 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388335082 # num instructions producing a value +system.cpu.iew.wb_consumers 1764294016 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.760999 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786887 # average fanout of values written-back +system.cpu.iew.wb_rate 1.769337 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 826504574 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 826637792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16081360 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1168002444 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.558028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.499439 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16091391 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1165244559 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.561715 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.500982 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 654033697 56.00% 56.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174911016 14.98% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86140681 7.38% 78.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53576194 4.59% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34697975 2.97% 85.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25994339 2.23% 88.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21604457 1.85% 89.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22883851 1.96% 91.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94160234 8.06% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 651170378 55.88% 55.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175014835 15.02% 70.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86149099 7.39% 78.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53527990 4.59% 82.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34710349 2.98% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26102733 2.24% 88.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21568948 1.85% 89.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22887442 1.96% 91.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94112785 8.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1168002444 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1165244559 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -612,225 +581,224 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94160234 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94112785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3634347710 # The number of ROB reads -system.cpu.rob.rob_writes 5409463480 # The number of ROB writes -system.cpu.timesIdled 947782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 85975286 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3631770492 # The number of ROB reads +system.cpu.rob.rob_writes 5409749589 # The number of ROB writes +system.cpu.timesIdled 953701 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 82324369 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.789596 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.789596 # CPI: Total CPI of All Threads -system.cpu.ipc 1.266471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.266471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3318031256 # number of integer regfile reads -system.cpu.int_regfile_writes 1931984794 # number of integer regfile writes -system.cpu.fp_regfile_reads 30556 # number of floating regfile reads -system.cpu.fp_regfile_writes 536 # number of floating regfile writes +system.cpu.cpi 0.785915 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.785915 # CPI: Total CPI of All Threads +system.cpu.ipc 1.272402 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.272402 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318200326 # number of integer regfile reads +system.cpu.int_regfile_writes 1932098427 # number of integer regfile writes +system.cpu.fp_regfile_reads 30699 # number of floating regfile reads +system.cpu.fp_regfile_writes 520 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1205179048 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7297603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3725230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1883628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1883628 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085762 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22087692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825951744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 826013504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 826013504 # Total data (bytes) +system.cpu.toL2Bus.throughput 1210780745 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3724768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883565 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1928 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22085326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22087254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825923008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 825984704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825984704 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10178550909 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 10177843430 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1605500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14084464250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14065476499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 773.100738 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 391053395 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 405236.678756 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.695817 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 391108717 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 964 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 405714.436722 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses -system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 391053395 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 391053395 # number of overall hits -system.cpu.icache.overall_hits::total 391053395 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1501 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1501 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1501 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1501 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1501 # number of overall misses -system.cpu.icache.overall_misses::total 1501 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 108152500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 108152500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 108152500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 108152500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 108152500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 391054896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 391054896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 391054896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 391054896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 391054896 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 773.695817 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 963 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470215 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782221404 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782221404 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 391108717 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391108717 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391108717 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391108717 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391108717 # number of overall hits +system.cpu.icache.overall_hits::total 391108717 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1503 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1503 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1503 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1503 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1503 # number of overall misses +system.cpu.icache.overall_misses::total 1503 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108284500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108284500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108284500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108284500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108284500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391110220 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391110220 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391110220 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391110220 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391110220 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72053.630913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72053.630913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72053.630913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72053.630913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 156 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72045.575516 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72045.575516 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72045.575516 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72045.575516 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 78 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75095000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 75095000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75095000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 75095000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75095000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 75095000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 539 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 539 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 539 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 539 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 539 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 539 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 964 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 964 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 964 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 964 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 964 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75722000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75722000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75722000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75722000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75722000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75722000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77818.652850 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77818.652850 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77818.652850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77818.652850 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78549.792531 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78549.792531 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78549.792531 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78549.792531 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1933762 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31423.393947 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9058762 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1963540 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.613485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28354220250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14586.517425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.834239 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16810.042284 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29778 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1933885 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31421.269549 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9058254 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1963664 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.612935 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28359986250 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14571.956791 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.815575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.497182 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.444701 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.513382 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958901 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29779 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17297 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10763 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908752 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107098856 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107098856 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3725230 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108435 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108435 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7214765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7214765 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7214765 # number of overall hits -system.cpu.l2cache.overall_hits::total 7214765 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1190308 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1191273 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 775193 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 775193 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1965501 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1966466 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1965501 # number of overall misses -system.cpu.l2cache.overall_misses::total 1966466 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74125000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 102633894750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102708019750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 67309627250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 67309627250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 74125000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 169943522000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 170017647000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 74125000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 169943522000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 170017647000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296638 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 86224.653409 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 86217.029808 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86829.508587 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86829.508587 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86458.472712 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76813.471503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86463.208108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86458.472712 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214114 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83983.473296 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -839,188 +807,188 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1019736 # number of writebacks -system.cpu.l2cache.writebacks::total 1019736 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1190308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1191273 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84983280750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 85045905750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55444498500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55444498500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62625000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 140427779250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 140490404250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62625000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 140427779250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 140490404250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163131 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163242 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411543 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411543 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163152 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163263 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411534 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411534 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214101 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74244.965125 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64218.652850 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73898.001069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73893.251142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214196 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64963.692946 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71386.027216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71380.830869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71527.352090 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71438.583665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64963.692946 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71441.759139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71438.583665 # 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Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.522150 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 705 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2966 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155539725 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694256136 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694256136 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694256136 # number of overall hits -system.cpu.dcache.overall_hits::total 694256136 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11395033 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11395033 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5188777 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5188777 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1430905565 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430905565 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 538740047 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538740047 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155537583 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155537583 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 694277630 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694277630 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694277630 # number of overall hits +system.cpu.dcache.overall_hits::total 694277630 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11394090 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11394090 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5190919 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5190919 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16583810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16583810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16583810 # number of overall misses -system.cpu.dcache.overall_misses::total 16583810 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 343354515500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 296317441834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 639671957334 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 639671957334 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 639671957334 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 550111444 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 550111444 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16585009 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16585009 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16585009 # number of overall misses +system.cpu.dcache.overall_misses::total 16585009 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 335805939499 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 289123962439 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 201500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 624929901938 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 624929901938 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 624929901938 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550134137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550134137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710839946 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710839946 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710839946 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710839946 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020714 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032283 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023330 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023330 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30131.945691 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30131.945691 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57107.376523 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57107.376523 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38572.074652 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38572.074652 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12375504 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8646342 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 745563 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 710862639 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710862639 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710862639 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710862639 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020711 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032296 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 29471.940234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 29471.940234 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55698.030048 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55698.030048 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 201500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 201500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37680.407767 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37680.407767 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11880802 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8587513 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745209 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65135 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.598871 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.744945 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.942913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131.841759 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725230 # number of writebacks -system.cpu.dcache.writebacks::total 3725230 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4098384 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3305161 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7403545 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7403545 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7403545 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296649 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883616 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883616 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724768 # number of writebacks +system.cpu.dcache.writebacks::total 3724768 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4097367 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3307364 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7404731 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7404731 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7404731 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883555 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883555 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180265 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180265 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180265 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 171833895250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 80710616128 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 89750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 252544511378 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 252544511378 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 252544511378 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180278 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180278 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180278 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 169103281751 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 78582140948 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 247685422699 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 247685422699 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 247685422699 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23549.700040 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42848.763298 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 89750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27509.501237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27509.501237 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012914 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23175.236576 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41720.120171 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 199500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26980.165818 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26980.165818 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 8c6f8359f..06e7873ee 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.533762 # Number of seconds simulated -sim_ticks 533761922000 # Number of ticks simulated -final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.530994 # Number of seconds simulated +sim_ticks 530994193500 # Number of ticks simulated +final_tick 530994193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155948 # Simulator instruction rate (inst/s) -host_op_rate 173972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53891847 # Simulator tick rate (ticks/s) -host_mem_usage 269768 # Number of bytes of host memory used -host_seconds 9904.32 # Real time elapsed on the host +host_inst_rate 125227 # Simulator instruction rate (inst/s) +host_op_rate 139700 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43051016 # Simulator tick rate (ticks/s) +host_mem_usage 313040 # Number of bytes of host memory used +host_seconds 12334.07 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory -system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory -system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246694 # Number of read requests accepted -system.physmem.writeReqs 1100579 # Number of write requests accepted -system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue -system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 47488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143709888 # Number of bytes read from this memory +system.physmem.bytes_read::total 143757376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70419456 # Number of bytes written to this memory +system.physmem.bytes_written::total 70419456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 742 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246209 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 270643050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 270732482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132618128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132618128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132618128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89432 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 270643050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 403350610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246209 # Number of read requests accepted +system.physmem.writeReqs 1100304 # Number of write requests accepted +system.physmem.readBursts 2246209 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1100304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 143663936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 93440 # Total number of bytes read from write queue +system.physmem.bytesWritten 70418368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 143757376 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 70419456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1460 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 139629 # Per bank write bursts -system.physmem.perBankRdBursts::1 136292 # Per bank write bursts -system.physmem.perBankRdBursts::2 133828 # Per bank write bursts -system.physmem.perBankRdBursts::3 136435 # Per bank write bursts -system.physmem.perBankRdBursts::4 134766 # Per bank write bursts -system.physmem.perBankRdBursts::5 135151 # Per bank write bursts -system.physmem.perBankRdBursts::6 136244 # Per bank write bursts -system.physmem.perBankRdBursts::7 136309 # Per bank write bursts -system.physmem.perBankRdBursts::8 143829 # Per bank write bursts -system.physmem.perBankRdBursts::9 146501 # Per bank write bursts -system.physmem.perBankRdBursts::10 144298 # Per bank write bursts -system.physmem.perBankRdBursts::11 146295 # Per bank write bursts -system.physmem.perBankRdBursts::12 145712 # Per bank write bursts -system.physmem.perBankRdBursts::13 146106 # Per bank write bursts -system.physmem.perBankRdBursts::14 142241 # Per bank write bursts -system.physmem.perBankRdBursts::15 142471 # Per bank write bursts -system.physmem.perBankWrBursts::0 69077 # Per bank write bursts -system.physmem.perBankWrBursts::1 67426 # Per bank write bursts -system.physmem.perBankWrBursts::2 65726 # Per bank write bursts -system.physmem.perBankWrBursts::3 66343 # Per bank write bursts -system.physmem.perBankWrBursts::4 66130 # Per bank write bursts -system.physmem.perBankWrBursts::5 66357 # Per bank write bursts -system.physmem.perBankWrBursts::6 67984 # Per bank write bursts -system.physmem.perBankWrBursts::7 68878 # Per bank write bursts -system.physmem.perBankWrBursts::8 70373 # Per bank write bursts -system.physmem.perBankWrBursts::9 70997 # Per bank write bursts -system.physmem.perBankWrBursts::10 70493 # Per bank write bursts -system.physmem.perBankWrBursts::11 70981 # Per bank write bursts -system.physmem.perBankWrBursts::12 70269 # Per bank write bursts -system.physmem.perBankWrBursts::13 70812 # Per bank write bursts -system.physmem.perBankWrBursts::14 69646 # Per bank write bursts -system.physmem.perBankWrBursts::15 69069 # Per bank write bursts +system.physmem.perBankRdBursts::0 139551 # Per bank write bursts +system.physmem.perBankRdBursts::1 136202 # Per bank write bursts +system.physmem.perBankRdBursts::2 133682 # Per bank write bursts +system.physmem.perBankRdBursts::3 136207 # Per bank write bursts +system.physmem.perBankRdBursts::4 134706 # Per bank write bursts +system.physmem.perBankRdBursts::5 135350 # Per bank write bursts +system.physmem.perBankRdBursts::6 136147 # Per bank write bursts +system.physmem.perBankRdBursts::7 135992 # Per bank write bursts +system.physmem.perBankRdBursts::8 143786 # Per bank write bursts +system.physmem.perBankRdBursts::9 146457 # Per bank write bursts +system.physmem.perBankRdBursts::10 144536 # Per bank write bursts +system.physmem.perBankRdBursts::11 146082 # Per bank write bursts +system.physmem.perBankRdBursts::12 145807 # Per bank write bursts +system.physmem.perBankRdBursts::13 145943 # Per bank write bursts +system.physmem.perBankRdBursts::14 141988 # Per bank write bursts +system.physmem.perBankRdBursts::15 142313 # Per bank write bursts +system.physmem.perBankWrBursts::0 69095 # Per bank write bursts +system.physmem.perBankWrBursts::1 67437 # Per bank write bursts +system.physmem.perBankWrBursts::2 65633 # Per bank write bursts +system.physmem.perBankWrBursts::3 66265 # Per bank write bursts +system.physmem.perBankWrBursts::4 66084 # Per bank write bursts +system.physmem.perBankWrBursts::5 66429 # Per bank write bursts +system.physmem.perBankWrBursts::6 67953 # Per bank write bursts +system.physmem.perBankWrBursts::7 68751 # Per bank write bursts +system.physmem.perBankWrBursts::8 70388 # Per bank write bursts +system.physmem.perBankWrBursts::9 70973 # Per bank write bursts +system.physmem.perBankWrBursts::10 70609 # Per bank write bursts +system.physmem.perBankWrBursts::11 70934 # Per bank write bursts +system.physmem.perBankWrBursts::12 70330 # Per bank write bursts +system.physmem.perBankWrBursts::13 70711 # Per bank write bursts +system.physmem.perBankWrBursts::14 69591 # Per bank write bursts +system.physmem.perBankWrBursts::15 69104 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 533761847000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 530994124500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2246694 # Read request sizes (log2) +system.physmem.readPktSize::6 2246209 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1100579 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1619262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 446010 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 134777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 44683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,216 +129,178 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2078319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.049035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 79.954808 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 184.695982 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 1660986 79.92% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 227336 10.94% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 68882 3.31% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 37662 1.81% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 25035 1.20% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 12093 0.58% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8438 0.41% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 8141 0.39% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 4391 0.21% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 3442 0.17% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 2829 0.14% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1974 0.09% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 1676 0.08% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 1442 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 1174 0.06% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 1106 0.05% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 969 0.05% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 858 0.04% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 735 0.04% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 673 0.03% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 651 0.03% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 3128 0.15% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 421 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 240 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 179 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 200 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 207 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 498 0.02% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 136 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 128 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 89 0.00% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 121 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 102 0.00% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 117 0.01% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 77 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 74 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 59 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 70 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 60 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 54 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 55 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 76 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 49 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 45 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 66 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 39 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 33 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 36 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 47 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 22 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 27 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 21 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 25 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 40 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 30 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 10 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 21 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 16 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 36 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 9 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 206 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation -system.physmem.totQLat 32815970750 # Total ticks spent queuing -system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers -system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks -system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 29573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 48522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 58770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 64531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 65202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 70263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 72456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 68391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1604351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 105.964762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.430314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 134.227606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1240784 77.34% 77.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261404 16.29% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44793 2.79% 96.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17157 1.07% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10128 0.63% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4810 0.30% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3056 0.19% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2546 0.16% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19673 1.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1604351 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 64945 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 34.562861 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 155.173168 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 64902 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 64945 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 64945 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.941828 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.872806 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.740981 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 45649 70.29% 70.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 15339 23.62% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 3628 5.59% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 219 0.34% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 37 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 12 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 17 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::66-67 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-77 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-81 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::82-83 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-89 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::90-91 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 64945 # Writes before turning the bus around for reads +system.physmem.totQLat 28406230500 # Total ticks spent queuing +system.physmem.totMemAccLat 98095071750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 11223745000 # Total ticks spent in databus transfers +system.physmem.totBankLat 58465096250 # Total ticks spent accessing banks +system.physmem.avgQLat 12654.52 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 26045.27 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43699.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 270.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 270.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing -system.physmem.readRowHits 932061 # Number of row buffer hits during reads -system.physmem.writeRowHits 336288 # Number of row buffer hits during writes -system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes -system.physmem.avgGap 159461.70 # Average gap between requests -system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 401350114 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1420099 # Transaction distribution -system.membus.trans_dist::ReadResp 1420098 # Transaction distribution -system.membus.trans_dist::Writeback 1100579 # Transaction distribution -system.membus.trans_dist::ReadExReq 826595 # Transaction distribution -system.membus.trans_dist::ReadExResp 826595 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 214225408 # Total data (bytes) +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.busUtilRead 2.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.38 # Average write queue length when enqueuing +system.physmem.readRowHits 908698 # Number of row buffer hits during reads +system.physmem.writeRowHits 419053 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.09 # Row buffer hit rate for writes +system.physmem.avgGap 158670.87 # Average gap between requests +system.physmem.pageHitRate 39.69 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 6.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 403350610 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1419771 # Transaction distribution +system.membus.trans_dist::ReadResp 1419771 # Transaction distribution +system.membus.trans_dist::Writeback 1100304 # Transaction distribution +system.membus.trans_dist::ReadExReq 826438 # Transaction distribution +system.membus.trans_dist::ReadExResp 826438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5592722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5592722 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214176832 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 214176832 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214176832 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 12918660500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 21056537500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 303426723 # Number of BP lookups -system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits +system.cpu.branchPred.lookups 303422540 # Number of BP lookups +system.cpu.branchPred.condPredicted 249650550 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15218950 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 174790549 # Number of BTB lookups +system.cpu.branchPred.BTBHits 161666933 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.491805 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17552768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 208 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -424,132 +386,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1067523845 # number of cpu cycles simulated +system.cpu.numCycles 1061988388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 298972523 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2188716520 # Number of instructions fetch has processed +system.cpu.fetch.Branches 303422540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 179219701 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 435616214 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 87982008 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 163592873 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 289402821 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5967581 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 968083151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.501232 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.206704 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 532467013 55.00% 55.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25400980 2.62% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39071584 4.04% 61.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48282365 4.99% 66.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43747142 4.52% 71.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46387901 4.79% 75.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38401401 3.97% 79.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18925667 1.95% 81.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175399098 18.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 968083151 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285712 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.060961 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 331186258 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 141449476 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 405224090 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20322579 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 69900748 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46031045 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 725 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2368410495 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2465 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 69900748 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 354622933 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 70003752 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18690 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 400463677 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73073351 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2305921736 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 149865 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5017686 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60142463 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2281817078 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10647699630 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9761875654 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 372 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 542 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 575497148 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 824 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 160915749 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 624658588 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 220783882 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 86055084 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 71680407 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2202175358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 849 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2018579412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4016690 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 474511400 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1127247409 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 968083151 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.085130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.905910 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 285219249 29.46% 29.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153603913 15.87% 45.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160908478 16.62% 61.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120369215 12.43% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123515877 12.76% 87.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73725483 7.62% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38349194 3.96% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9869125 1.02% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2522617 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 968083151 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 891948 3.74% 3.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5659 0.02% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18285123 76.74% 80.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4644794 19.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236892590 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 924644 0.05% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -571,90 +534,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 35 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 5 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587766580 29.12% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192995535 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued -system.cpu.iq.rate 1.891055 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2018579412 # Type of FU issued +system.cpu.iq.rate 1.900755 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23827524 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011804 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5033085915 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2676877502 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957286875 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 274 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2042406797 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64607409 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 138731819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 269264 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192926 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45936837 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4636852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 69900748 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 32985264 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1607893 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2202176322 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7875030 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 624658588 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 220783882 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 787 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 480489 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 97297 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192926 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8154150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9614096 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17768246 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1987907812 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 573917969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30671600 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143 # number of nop insts executed -system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed -system.cpu.iew.exec_branches 238318975 # Number of branches executed -system.cpu.iew.exec_stores 190166415 # Number of stores executed -system.cpu.iew.exec_rate 1.862270 # Inst execution rate -system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1295394361 # num instructions producing a value -system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value +system.cpu.iew.exec_nop 115 # number of nop insts executed +system.cpu.iew.exec_refs 764035004 # number of memory reference insts executed +system.cpu.iew.exec_branches 238344765 # Number of branches executed +system.cpu.iew.exec_stores 190117035 # Number of stores executed +system.cpu.iew.exec_rate 1.871873 # Inst execution rate +system.cpu.iew.wb_sent 1965721385 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957286989 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295353169 # num instructions producing a value +system.cpu.iew.wb_consumers 2059124619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back +system.cpu.iew.wb_rate 1.843040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629080 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 479201419 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15218256 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 898182403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.918401 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.718632 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 409520932 45.59% 45.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193341126 21.53% 67.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72856392 8.11% 75.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35266381 3.93% 79.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18923261 2.11% 81.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30757515 3.42% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19970325 2.22% 86.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11453537 1.28% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106092934 11.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 898182403 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -665,98 +628,99 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106092934 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2995284619 # The number of ROB reads -system.cpu.rob.rob_writes 4474886700 # The number of ROB writes -system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2994364142 # The number of ROB reads +system.cpu.rob.rob_writes 4474601624 # The number of ROB writes +system.cpu.timesIdled 1160522 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 93905237 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads -system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads -system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes -system.cpu.fp_regfile_reads 98 # number of floating regfile reads -system.cpu.fp_regfile_writes 94 # number of floating regfile writes -system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads +system.cpu.cpi 0.687566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.687566 # CPI: Total CPI of All Threads +system.cpu.ipc 1.454407 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.454407 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9955508978 # number of integer regfile reads +system.cpu.int_regfile_writes 1937309574 # number of integer regfile writes +system.cpu.fp_regfile_reads 108 # number of floating regfile reads +system.cpu.fp_regfile_writes 108 # number of floating regfile writes +system.cpu.misc_regfile_reads 737568033 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 1613255878 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7708873 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7708872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3782409 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893555 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893555 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1549 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22985720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22987269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856579904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 856629440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856629440 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10474986844 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1289999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14746367742 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 19 # number of replacements -system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17 # number of replacements +system.cpu.icache.tags.tagsinuse 631.201883 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 289401615 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 772 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 374872.558290 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 631.201883 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.308204 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.308204 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 755 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits -system.cpu.icache.overall_hits::total 289577640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses -system.cpu.icache.overall_misses::total 1205 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 729 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.368652 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 578806417 # Number of tag accesses +system.cpu.icache.tags.data_accesses 578806417 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 289401622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 289401622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 289401622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 289401622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 289401622 # number of overall hits +system.cpu.icache.overall_hits::total 289401622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1199 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1199 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1199 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1199 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1199 # number of overall misses +system.cpu.icache.overall_misses::total 1199 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 84823499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 84823499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 84823499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 84823499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 84823499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 84823499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 289402821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 289402821 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 289402821 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 289402821 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 289402821 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 289402821 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70745.203503 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87253.784500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87249.585859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74560.565276 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87253.784500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87249.585859 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -896,195 +864,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1100579 # number of writebacks -system.cpu.l2cache.writebacks::total 1100579 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1100304 # number of writebacks +system.cpu.l2cache.writebacks::total 1100304 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173822853500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173868116500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45263000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173822853500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184124 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184202 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436545 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436545 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.233959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.233959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60837.365591 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76013.056987 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76005.106334 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79764.988900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79764.988900 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 742 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1419771 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63474835750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63474835750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45997000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 167791188000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 167837185000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45997000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 167791188000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 167837185000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184096 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184174 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436448 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436448 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.233921 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958656 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233863 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.233921 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61990.566038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73512.487941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73506.466360 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76805.320847 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76805.320847 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74720.199679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61990.566038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74724.406103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74720.199679 # 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Cycle average of tags in use +system.cpu.dcache.tags.total_refs 656035033 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9601652 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 68.325225 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3543401250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.017894 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998051 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998051 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 619 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2366 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1110 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 1355956994 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355956994 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 489079777 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 489079777 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 166955126 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 166955126 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits -system.cpu.dcache.overall_hits::total 656012474 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11506498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11506498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5629782 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5629782 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 656034903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 656034903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 656034903 # number of overall hits +system.cpu.dcache.overall_hits::total 656034903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11511719 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11511719 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5630921 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5630921 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17136280 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17136280 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17136280 # number of overall misses -system.cpu.dcache.overall_misses::total 17136280 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 363307841237 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 307618244019 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 670926085256 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17142640 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17142640 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17142640 # number of overall misses +system.cpu.dcache.overall_misses::total 17142640 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 356637028987 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 356637028987 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 299385068793 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 299385068793 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 231500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 656022097780 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 656022097780 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 656022097780 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 656022097780 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500591496 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500591496 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673177543 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673177543 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673177543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673177543 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032627 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30980.345245 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30980.345245 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53168.046363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53168.046363 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38268.440437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38268.440437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38268.440437 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23433940 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3966170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1210564 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.357870 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 60.894338 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks -system.cpu.dcache.writebacks::total 3782070 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3782409 # number of writebacks +system.cpu.dcache.writebacks::total 3782409 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3803620 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3803620 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3737364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3737364 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 7540984 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7540984 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7540984 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7540984 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708099 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7708099 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893557 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601656 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601656 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601656 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601656 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194575797258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 194575797258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86895396246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86895396246 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 281471193504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 281471193504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 281471193504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 281471193504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25243.032978 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25243.032978 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45890.034599 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45890.034599 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29314.859177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29314.859177 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 3f6e9d455..17c346b69 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041680 # Number of seconds simulated -sim_ticks 41680207000 # Number of ticks simulated -final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041684 # Number of seconds simulated +sim_ticks 41683573000 # Number of ticks simulated +final_tick 41683573000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131207 # Simulator instruction rate (inst/s) -host_op_rate 131207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59505524 # Simulator tick rate (ticks/s) -host_mem_usage 234284 # Number of bytes of host memory used -host_seconds 700.44 # Real time elapsed on the host +host_inst_rate 119929 # Simulator instruction rate (inst/s) +host_op_rate 119929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54395175 # Simulator tick rate (ticks/s) +host_mem_usage 269084 # Number of bytes of host memory used +host_seconds 766.31 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4290190 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3292114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7582304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4290190 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4290190 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3292114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7582304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4289843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3291848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7581692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4289843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4289843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3291848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7581692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 41680133000 # Total gap between requests +system.physmem.totGap 41683192000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -154,65 +154,60 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.641992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.527903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 761.351186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 254 34.19% 34.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 96 12.92% 47.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 62 8.34% 55.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 50 6.73% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 29 3.90% 66.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 32 4.31% 70.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 22 2.96% 73.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 25 3.36% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 15 2.02% 78.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 12 1.62% 80.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 14 1.88% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 16 2.15% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 32 4.31% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 17 2.29% 90.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 5 0.67% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.67% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 8 1.08% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 5 0.67% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 6 0.81% 94.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 6 0.81% 95.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.27% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.13% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 3 0.40% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 2 0.27% 96.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.13% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.27% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.27% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 1 0.13% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 1 0.13% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.13% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.13% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.13% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 1 0.13% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 1 0.13% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.13% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 1 0.13% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 1 0.13% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 1 0.13% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 743 # Bytes accessed per row activation -system.physmem.totQLat 34070750 # Total ticks spent queuing -system.physmem.totMemAccLat 126424500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 541.521127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 335.427822 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.351632 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 20.42% 20.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 54 19.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24 8.45% 47.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 4.23% 52.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 3.52% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 3.17% 58.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 1.76% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 1.76% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 107 37.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 284 # Bytes accessed per row activation +system.physmem.totQLat 37971250 # Total ticks spent queuing +system.physmem.totMemAccLat 131493750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers -system.physmem.totBankLat 67663750 # Total ticks spent accessing banks -system.physmem.avgQLat 6899.71 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13702.66 # Average bank access latency per DRAM burst +system.physmem.totBankLat 68832500 # Total ticks spent accessing banks +system.physmem.avgQLat 7689.60 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13939.35 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25602.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26628.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s @@ -221,16 +216,16 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4195 # Number of row buffer hits during reads +system.physmem.readRowHits 4086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.95 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8440691.17 # Average gap between requests -system.physmem.pageHitRate 84.95 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.90 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 7582304 # Throughput (bytes/s) +system.physmem.avgGap 8441310.65 # Average gap between requests +system.physmem.pageHitRate 82.75 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 7581692 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3216 # Transaction distribution system.membus.trans_dist::ReadResp 3216 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution @@ -241,9 +236,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 316032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 5775000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 5776500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 45941000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 13412627 # Number of BP lookups @@ -259,18 +254,18 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996265 # DTB read hits +system.cpu.dtb.read_hits 19996264 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996275 # DTB read accesses -system.cpu.dtb.write_hits 6501862 # DTB write hits +system.cpu.dtb.read_accesses 19996274 # DTB read accesses +system.cpu.dtb.write_hits 6501866 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501885 # DTB write accesses -system.cpu.dtb.data_hits 26498127 # DTB hits +system.cpu.dtb.write_accesses 6501889 # DTB write accesses +system.cpu.dtb.data_hits 26498130 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498160 # DTB accesses +system.cpu.dtb.data_accesses 26498163 # DTB accesses system.cpu.itb.fetch_hits 9956950 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -288,18 +283,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83360415 # number of cpu cycles simulated +system.cpu.numCycles 83367147 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 5905662 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570552 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521866 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 26722393 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). @@ -310,12 +305,12 @@ system.cpu.execution_unit.executions 57404027 # Nu system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82971123 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82970332 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7752655 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607760 # Number of cycles cpu stages are processed. -system.cpu.activity 90.699836 # Percentage of cycles cpu is active +system.cpu.timesIdled 10410 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7759392 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75607755 # Number of cycles cpu stages are processed. +system.cpu.activity 90.692506 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -327,36 +322,36 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.907047 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.907121 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.907047 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102478 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.907121 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102389 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.102478 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27680069 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680346 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.794708 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34108732 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251683 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.082819 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33509067 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851348 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.802183 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65333914 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.624774 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29500658 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859757 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.610711 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.102389 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27686803 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55680344 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.789312 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34115467 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251680 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.078044 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33515800 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.797353 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65340657 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026490 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.623014 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29507392 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.605491 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 7635 # number of replacements -system.cpu.icache.tags.tagsinuse 1492.182806 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1492.188372 # Cycle average of tags in use system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1492.188372 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.728608 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.728608 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id @@ -378,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 11399 # n system.cpu.icache.demand_misses::total 11399 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11399 # number of overall misses system.cpu.icache.overall_misses::total 11399 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 325866750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 325866750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 325866750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 325866750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 325866750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 329283500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 329283500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 329283500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 329283500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 329283500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 9956950 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 9956950 # number of demand (read+write) accesses @@ -396,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28587.310290 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28587.310290 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28587.310290 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28587.310290 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28887.051496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28887.051496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28887.051496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28887.051496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -422,26 +417,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 9520 system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 266339500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 266339500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 266339500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 266339500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268822750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268822750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268822750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268822750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27976.838235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27976.838235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27976.838235 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28237.683824 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28237.683824 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28237.683824 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 18195687 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 18194218 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -457,19 +452,19 @@ system.cpu.toL2Bus.data_through_bus 758400 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 14812000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 14800250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3559500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3515750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2189.577948 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2189.597840 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.842967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.748644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986337 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.844631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.766792 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 350.986416 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy @@ -507,17 +502,17 @@ system.cpu.l2cache.demand_misses::total 4938 # nu system.cpu.l2cache.overall_misses::cpu.inst 2794 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4938 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32395250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 221677250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 122425750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189282000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 154821000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 344103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189282000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 154821000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 344103000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 191765250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32319750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 224085000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 125611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 191765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 157931250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 349696500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 191765250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 157931250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 349696500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses) @@ -542,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.420506 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67745.884037 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76765.995261 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68929.493159 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71095.092915 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69684.690158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67745.884037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72211.287313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69684.690158 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68634.663565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76587.085308 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69678.171642 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72945.121951 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70817.436209 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68634.663565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73661.963619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70817.436209 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 154136500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27132250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 181268750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101289750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 154136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128422000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 282558500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 154136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128422000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 282558500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 156642750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27057250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 183700000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104540000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 156642750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131597250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 288240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 156642750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131597250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 288240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses @@ -594,31 +589,31 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55166.964925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64294.431280 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56364.661070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58820.993031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55166.964925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59898.320896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57221.243418 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56063.976378 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64116.706161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57120.646766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60708.478513 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56063.976378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61379.314366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58371.810450 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.367780 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26488450 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1441.382253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26488456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11915.632029 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11915.634728 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.382253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.351900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.351900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id @@ -626,28 +621,28 @@ system.cpu.dcache.tags.tag_accesses 52996825 # Nu system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492829 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488450 # number of overall hits -system.cpu.dcache.overall_hits::total 26488450 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492835 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488456 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488456 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488456 # number of overall hits +system.cpu.dcache.overall_hits::total 26488456 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 577 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8274 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8274 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8851 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8851 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8851 # number of overall misses -system.cpu.dcache.overall_misses::total 8851 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 41023250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 41023250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 492650500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 492650500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 533673750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 533673750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 533673750 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 8268 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8268 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8845 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8845 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8845 # number of overall misses +system.cpu.dcache.overall_misses::total 8845 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40979500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40979500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 507652000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 507652000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 548631500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 548631500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 548631500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -658,25 +653,25 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001273 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001273 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001272 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001272 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71097.487002 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71097.487002 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59541.999033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59541.999033 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60295.305615 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60295.305615 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23884 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71021.663778 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71021.663778 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61399.612966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61399.612966 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62027.303561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62027.303561 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 25755 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 841 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 844 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.399524 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.515403 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -684,12 +679,12 @@ system.cpu.dcache.writebacks::writebacks 107 # nu system.cpu.dcache.writebacks::total 107 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6526 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6628 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6628 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6628 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6520 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6520 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6622 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6622 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6622 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -698,14 +693,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33418750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 124443250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 157862000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157862000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 157862000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33343250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127629000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160972250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160972250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160972250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -714,14 +709,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70355.263158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71191.790618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71013.045434 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71013.045434 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70196.315789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73014.302059 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72412.168241 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72412.168241 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b0acaf58e..c3a9e9ab9 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023462 # Number of seconds simulated -sim_ticks 23461709500 # Number of ticks simulated -final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023455 # Number of seconds simulated +sim_ticks 23455364500 # Number of ticks simulated +final_tick 23455364500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186682 # Simulator instruction rate (inst/s) -host_op_rate 186682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52030153 # Simulator tick rate (ticks/s) -host_mem_usage 235304 # Number of bytes of host memory used -host_seconds 450.93 # Real time elapsed on the host +host_inst_rate 164985 # Simulator instruction rate (inst/s) +host_op_rate 164985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45970553 # Simulator tick rate (ticks/s) +host_mem_usage 272156 # Number of bytes of host memory used +host_seconds 510.23 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 195968 # Nu system.physmem.num_reads::cpu.inst 3062 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8352674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5908521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14261194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8352674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8352674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5908521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14261194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8354933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14265052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8354933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8354933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14265052 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue @@ -41,20 +41,20 @@ system.physmem.bytesWrittenSys 0 # To system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 466 # Per bank write bursts +system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts -system.physmem.perBankRdBursts::2 300 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts +system.physmem.perBankRdBursts::2 301 # Per bank write bursts +system.physmem.perBankRdBursts::3 519 # Per bank write bursts system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 226 # Per bank write bursts -system.physmem.perBankRdBursts::6 219 # Per bank write bursts +system.physmem.perBankRdBursts::5 227 # Per bank write bursts +system.physmem.perBankRdBursts::6 220 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts -system.physmem.perBankRdBursts::8 240 # Per bank write bursts -system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::8 236 # Per bank write bursts +system.physmem.perBankRdBursts::9 278 # Per bank write bursts system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 254 # Per bank write bursts -system.physmem.perBankRdBursts::12 400 # Per bank write bursts -system.physmem.perBankRdBursts::13 336 # Per bank write bursts +system.physmem.perBankRdBursts::11 255 # Per bank write bursts +system.physmem.perBankRdBursts::12 401 # Per bank write bursts +system.physmem.perBankRdBursts::13 338 # Per bank write bursts system.physmem.perBankRdBursts::14 491 # Per bank write bursts system.physmem.perBankRdBursts::15 447 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23461582500 # Total gap between requests +system.physmem.totGap 23455237500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,84 +154,78 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 442.026667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.409345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 807.667918 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 266 35.47% 35.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 111 14.80% 50.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 59 7.87% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 40 5.33% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 26 3.47% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 30 4.00% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 24 3.20% 74.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 16 2.13% 76.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.20% 77.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 13 1.73% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 15 2.00% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 13 1.73% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 37 4.93% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 11 1.47% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.80% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 3 0.40% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 7 0.93% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 7 0.93% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 3 0.40% 92.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 3 0.40% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 8 1.07% 94.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.13% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 3 0.40% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.27% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 4 0.53% 95.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 2 0.27% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.13% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 1 0.13% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 3 0.40% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 3 0.40% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 1 0.13% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 3 0.40% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.13% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 1 0.13% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 3 0.40% 98.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 1 0.13% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.13% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 2 0.27% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 1 0.13% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 1 0.13% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 1 0.13% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.13% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 1 0.13% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.13% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.13% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 2 0.27% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 750 # Bytes accessed per row activation -system.physmem.totQLat 37518750 # Total ticks spent queuing -system.physmem.totMemAccLat 134402500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.348083 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 311.933424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.197716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 23.89% 23.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 64 18.88% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 21 6.19% 48.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17 5.01% 53.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.65% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 2.36% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.06% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.88% 61.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 129 38.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 339 # Bytes accessed per row activation +system.physmem.totQLat 42838250 # Total ticks spent queuing +system.physmem.totMemAccLat 141220750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers -system.physmem.totBankLat 70743750 # Total ticks spent accessing banks -system.physmem.avgQLat 7176.50 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13531.70 # Average bank access latency per DRAM burst +system.physmem.totBankLat 72242500 # Total ticks spent accessing banks +system.physmem.avgQLat 8194.00 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 13818.38 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25708.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27012.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.26 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.11 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4478 # Number of row buffer hits during reads +system.physmem.readRowHits 4346 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.13 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4487678.37 # Average gap between requests -system.physmem.pageHitRate 85.65 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.19 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 14261194 # Throughput (bytes/s) +system.physmem.avgGap 4486464.71 # Average gap between requests +system.physmem.pageHitRate 83.13 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 1.10 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 14265052 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 3523 # Transaction distribution system.membus.trans_dist::ReadResp 3523 # Transaction distribution system.membus.trans_dist::ReadExReq 1705 # Transaction distribution @@ -242,40 +236,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 334592 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6831000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6760500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 48963750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14847721 # Number of BP lookups -system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8301784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6957680 # Number of BTB hits +system.cpu.branchPred.lookups 14848335 # Number of BP lookups +system.cpu.branchPred.condPredicted 10770516 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 922016 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8296689 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6955595 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.809456 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1467978 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3097 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.835793 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1468520 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3112 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23117785 # DTB read hits -system.cpu.dtb.read_misses 192281 # DTB read misses +system.cpu.dtb.read_hits 23116922 # DTB read hits +system.cpu.dtb.read_misses 193562 # DTB read misses system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 23310066 # DTB read accesses -system.cpu.dtb.write_hits 7068175 # DTB write hits -system.cpu.dtb.write_misses 1137 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 7069312 # DTB write accesses -system.cpu.dtb.data_hits 30185960 # DTB hits -system.cpu.dtb.data_misses 193418 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30379378 # DTB accesses -system.cpu.itb.fetch_hits 14734161 # ITB hits -system.cpu.itb.fetch_misses 103 # ITB misses +system.cpu.dtb.read_accesses 23310484 # DTB read accesses +system.cpu.dtb.write_hits 7068693 # DTB write hits +system.cpu.dtb.write_misses 1118 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7069811 # DTB write accesses +system.cpu.dtb.data_hits 30185615 # DTB hits +system.cpu.dtb.data_misses 194680 # DTB misses +system.cpu.dtb.data_acv 6 # DTB access violations +system.cpu.dtb.data_accesses 30380295 # DTB accesses +system.cpu.itb.fetch_hits 14732180 # ITB hits +system.cpu.itb.fetch_misses 100 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14734264 # ITB accesses +system.cpu.itb.fetch_accesses 14732280 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -289,139 +283,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46923420 # number of cpu cycles simulated +system.cpu.numCycles 46910730 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15463381 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126961894 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14847721 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8425658 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22130056 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4473003 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5559398 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2205 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14734161 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324644 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.720324 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376096 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15458006 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 126949517 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14848335 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8424115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22129467 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4471319 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5547804 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2176 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14732180 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 325492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.721156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376288 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24541547 52.58% 52.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2361252 5.06% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1192515 2.56% 60.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1742111 3.73% 63.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2755701 5.90% 69.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149393 2.46% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1220691 2.62% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 771780 1.65% 76.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10936613 23.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24523314 52.57% 52.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2362460 5.06% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1191709 2.55% 60.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1744531 3.74% 63.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2756035 5.91% 69.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1149513 2.46% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1216156 2.61% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 771099 1.65% 76.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10937964 23.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46671603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.316425 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.705725 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17289395 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4257221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20524693 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1095542 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3504752 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2511898 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12167 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123979126 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 31595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3504752 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18431780 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 963421 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7928 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20455398 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3308324 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121154570 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 400162 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2430153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88974225 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157440425 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 150394655 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7045769 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46652781 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316523 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.706194 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17279755 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4249359 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20525557 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1094653 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3503457 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12079 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 123971467 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 32460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3503457 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18421615 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 960025 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8092 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20456033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3303559 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121144333 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 398869 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2427038 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 88958437 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157404324 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 150359413 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7044910 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20546864 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 749 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 744 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8783261 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25363133 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8241349 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2569635 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 893782 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105438334 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 961 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96565072 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178504 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20784578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15622466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 572 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46671603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.069033 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.876517 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20531076 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 753 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 746 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8762869 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25364686 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8245053 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2579677 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 916866 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105436349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1901 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96572685 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177506 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20788885 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15603704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1512 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46652781 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.070031 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.877189 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12133902 26.00% 26.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9340972 20.01% 46.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8404137 18.01% 64.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6285068 13.47% 77.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4921137 10.54% 88.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2853571 6.11% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727806 3.70% 97.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 798697 1.71% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 206313 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12130850 26.00% 26.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9330795 20.00% 46.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8389374 17.98% 63.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6281972 13.47% 77.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4924466 10.56% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2864469 6.14% 94.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1724344 3.70% 97.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 801135 1.72% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205376 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46671603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46652781 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187905 11.99% 11.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 187827 11.99% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 11.99% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 11.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 198 0.01% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7114 0.45% 12.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5683 0.36% 12.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843073 53.81% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 444038 28.34% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78699 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 195 0.01% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7087 0.45% 12.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5615 0.36% 12.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 842803 53.78% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 445934 28.46% 95.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77665 4.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58732393 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479878 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58739096 60.82% 60.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479860 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798409 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115272 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2387143 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 310920 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760028 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2798014 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115391 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2386555 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 310970 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 759904 0.79% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued @@ -443,84 +437,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23829441 24.68% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7151262 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23830824 24.68% 92.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7151745 7.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96565072 # Type of FU issued -system.cpu.iq.rate 2.057929 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1566710 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226434513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117518300 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87069210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15112448 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8740080 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062492 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90145382 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7986393 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1518186 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96572685 # Type of FU issued +system.cpu.iq.rate 2.058648 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1567126 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016227 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226432918 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117523015 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87074868 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15109865 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8738386 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7061397 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90154911 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7984893 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1517468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5366935 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18425 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34629 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740246 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5368488 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18513 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34393 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1743950 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10551 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2023 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10556 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2089 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3504752 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 133474 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18356 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115674265 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 366324 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25363133 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8241349 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 961 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3503457 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134155 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17977 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115673905 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371989 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25364686 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8245053 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1901 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2671 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 35 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34629 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 535207 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 494157 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1029364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95337689 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23310553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1227383 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 34393 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 533358 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495038 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028396 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95341973 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23310954 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1230712 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10234970 # number of nop insts executed -system.cpu.iew.exec_refs 30380075 # number of memory reference insts executed -system.cpu.iew.exec_branches 12022158 # Number of branches executed -system.cpu.iew.exec_stores 7069522 # Number of stores executed -system.cpu.iew.exec_rate 2.031772 # Inst execution rate -system.cpu.iew.wb_sent 94652012 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94131702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64474346 # num instructions producing a value -system.cpu.iew.wb_consumers 89850691 # num instructions consuming a value +system.cpu.iew.exec_nop 10235655 # number of nop insts executed +system.cpu.iew.exec_refs 30380968 # number of memory reference insts executed +system.cpu.iew.exec_branches 12023807 # Number of branches executed +system.cpu.iew.exec_stores 7070014 # Number of stores executed +system.cpu.iew.exec_rate 2.032413 # Inst execution rate +system.cpu.iew.wb_sent 94656410 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94136265 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64475750 # num instructions producing a value +system.cpu.iew.wb_consumers 89852391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.006071 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717572 # average fanout of values written-back +system.cpu.iew.wb_rate 2.006711 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717574 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23772316 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23771863 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 910471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43166851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.129019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.746086 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 910264 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43149324 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.129884 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.746526 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16723468 38.74% 38.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9908468 22.95% 61.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4486822 10.39% 72.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263317 5.24% 77.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1605459 3.72% 81.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1122723 2.60% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719573 1.67% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 818065 1.90% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5518956 12.79% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16704227 38.71% 38.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9920088 22.99% 61.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4481212 10.39% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2253745 5.22% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1606057 3.72% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1123881 2.60% 83.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722151 1.67% 85.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820935 1.90% 87.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5517028 12.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43166851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43149324 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -531,173 +525,173 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5518956 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5517028 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153322226 # The number of ROB reads -system.cpu.rob.rob_writes 234879469 # The number of ROB writes -system.cpu.timesIdled 5401 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 251817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153306174 # The number of ROB reads +system.cpu.rob.rob_writes 234877097 # The number of ROB writes +system.cpu.timesIdled 5272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 257949 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.557420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.557420 # CPI: Total CPI of All Threads -system.cpu.ipc 1.793981 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.793981 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129048096 # number of integer regfile reads -system.cpu.int_regfile_writes 70519803 # number of integer regfile writes -system.cpu.fp_regfile_reads 6188545 # number of floating regfile reads -system.cpu.fp_regfile_writes 6044303 # number of floating regfile writes -system.cpu.misc_regfile_reads 714547 # number of misc regfile reads +system.cpu.cpi 0.557269 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.557269 # CPI: Total CPI of All Threads +system.cpu.ipc 1.794466 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.794466 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129050731 # number of integer regfile reads +system.cpu.int_regfile_writes 70522819 # number of integer regfile writes +system.cpu.fp_regfile_reads 6187407 # number of floating regfile reads +system.cpu.fp_regfile_writes 6043154 # number of floating regfile writes +system.cpu.misc_regfile_reads 714454 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 37824354 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 12026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12026 # Transaction distribution +system.cpu.toL2Bus.throughput 37351626 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 11849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11849 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1731 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1731 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22666 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 736640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27269 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 725312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 887424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 876096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 876096 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 7042000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 6953500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17847250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17562000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3539750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 9576 # number of replacements -system.cpu.icache.tags.tagsinuse 1596.482984 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14719872 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1278.876803 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9398 # number of replacements +system.cpu.icache.tags.tagsinuse 1599.250917 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 14718111 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11333 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1298.695050 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1599.250917 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.780884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1935 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 924 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 29479830 # Number of tag accesses -system.cpu.icache.tags.data_accesses 29479830 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14719872 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14719872 # number of overall hits -system.cpu.icache.overall_hits::total 14719872 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14288 # number of overall misses -system.cpu.icache.overall_misses::total 14288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413271500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413271500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413271500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413271500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413271500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14734160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14734160 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14734160 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14734160 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14734160 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14734160 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28924.377100 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28924.377100 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28924.377100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28924.377100 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28924.377100 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 548 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 929 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944824 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29475691 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29475691 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 14718111 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14718111 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14718111 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14718111 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14718111 # number of overall hits +system.cpu.icache.overall_hits::total 14718111 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14068 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14068 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14068 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14068 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14068 # number of overall misses +system.cpu.icache.overall_misses::total 14068 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413989500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413989500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413989500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413989500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413989500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413989500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14732179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14732179 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14732179 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14732179 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14732179 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14732179 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000955 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000955 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000955 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000955 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000955 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000955 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29427.743816 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29427.743816 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29427.743816 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29427.743816 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 165 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2778 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2778 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2778 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2778 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2778 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2778 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11510 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11510 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 303668250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 303668250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 303668250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 303668250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 303668250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 303668250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000781 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26382.993050 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26382.993050 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26382.993050 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26382.993050 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2735 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2735 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2735 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2735 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2735 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2735 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11333 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11333 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11333 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11333 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11333 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11333 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 305304500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 305304500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 305304500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 305304500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 305304500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 305304500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000769 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000769 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000769 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000769 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26939.424689 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26939.424689 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26939.424689 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26939.424689 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2409.583505 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8517 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2413.657208 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8341 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3590 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.372423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.323398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.678720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2010.447963 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 381.456822 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 17.675331 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2012.279201 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 383.702676 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061410 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011710 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073659 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3590 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 910 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 904 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2435 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116249 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116249 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8448 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 114833 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 114833 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8271 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8503 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 8326 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8448 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8271 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8529 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34560750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 242229000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 124310250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 124310250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207668250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 366539250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207668250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158871000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 366539250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11510 # 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number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 516 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12026 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11849 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1731 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1731 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11510 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 11333 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2247 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13757 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11510 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 13580 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11333 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2247 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13757 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266030 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 13580 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.270184 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.893411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.292949 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.297325 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984980 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.984980 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266030 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.270184 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380025 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266030 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.384978 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.270184 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380025 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67821.113651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74969.088937 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68756.457565 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72909.237537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70110.797628 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67821.113651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73347.645429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70110.797628 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.384978 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68991.998694 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79441.431670 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70359.352824 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73669.648094 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71438.934583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68991.998694 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74898.084026 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71438.934583 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,135 +768,136 @@ system.cpu.l2cache.demand_mshr_misses::total 5228 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3062 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168834750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28858250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197693000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 103390750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168834750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132249000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 301083750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168834750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132249000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 301083750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 172480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 203395500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 104707750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 135622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308103250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 135622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 308103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.893411 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292949 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.297325 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984980 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380025 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266030 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.384978 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.270184 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380025 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55138.716525 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62599.240781 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56114.958842 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60639.736070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55138.716525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61056.786704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57590.617827 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.384978 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56329.359895 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67060.737527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57733.607721 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61412.170088 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56329.359895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62614.381348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58933.291890 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1459.152638 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28079168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1460.308394 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28078942 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2247 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12496.291945 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12496.191366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1460.308394 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356521 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356521 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1391 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 56179001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 56179001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 264 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 264 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28078904 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28078904 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28078904 # number of overall hits -system.cpu.dcache.overall_hits::total 28078904 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 974 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 974 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8234 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8234 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 56178581 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56178581 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21585827 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21585827 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492868 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492868 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 247 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 247 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28078695 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28078695 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28078695 # number of overall hits +system.cpu.dcache.overall_hits::total 28078695 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 989 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 989 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8235 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8235 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9208 # number of overall misses -system.cpu.dcache.overall_misses::total 9208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58289250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58289250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 505816795 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 505816795 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9224 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9224 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9224 # number of overall misses +system.cpu.dcache.overall_misses::total 9224 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64012750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64012750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 517866286 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 517866286 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564106045 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564106045 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564106045 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21587009 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21587009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 581879036 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 581879036 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 581879036 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21586816 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21586816 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 265 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28088112 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28088112 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28088112 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28088112 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28087919 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28087919 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28087919 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28087919 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001267 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001267 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003774 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003774 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004032 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004032 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59845.225873 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59845.225873 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61430.264149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61430.264149 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64724.721941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64724.721941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62886.009229 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62886.009229 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61262.602628 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61262.602628 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63083.156548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63083.156548 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 336 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 346 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.583333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71.728324 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6503 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6503 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6962 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6962 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6962 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 474 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 474 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6504 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6978 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6978 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6978 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses @@ -913,36 +908,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2246 system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 35552000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126441497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126441497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37612750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127737997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127737997 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161993497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161993497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161993497 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 165350747 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 165350747 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 165350747 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003774 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003774 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004032 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69033.009709 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73045.347776 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73045.347776 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73034.466019 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73794.336800 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73794.336800 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72125.332591 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72125.332591 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73620.101069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73620.101069 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index a1592fc7b..975655111 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074220 # Number of seconds simulated -sim_ticks 74219931000 # Number of ticks simulated -final_tick 74219931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074212 # Number of seconds simulated +sim_ticks 74211770500 # Number of ticks simulated +final_tick 74211770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128899 # Simulator instruction rate (inst/s) -host_op_rate 141133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55523526 # Simulator tick rate (ticks/s) -host_mem_usage 273064 # Number of bytes of host memory used -host_seconds 1336.73 # Real time elapsed on the host +host_inst_rate 109728 # Simulator instruction rate (inst/s) +host_op_rate 120142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47260193 # Simulator tick rate (ticks/s) +host_mem_usage 316324 # Number of bytes of host memory used +host_seconds 1570.28 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory -system.physmem.bytes_read::total 242752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112000 # Number of bytes read from this memory +system.physmem.bytes_read::total 243072 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 131072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 131072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1745 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3793 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1765995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1504717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3270712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1765995 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1765995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1504717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3270712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3794 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1750 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3798 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1766189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1509195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3275383 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1766189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1766189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1509195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3275383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3799 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3794 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3799 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 242816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 243136 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 242816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 243136 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 306 # Per bank write bursts system.physmem.perBankRdBursts::1 215 # Per bank write bursts -system.physmem.perBankRdBursts::2 133 # Per bank write bursts +system.physmem.perBankRdBursts::2 132 # Per bank write bursts system.physmem.perBankRdBursts::3 308 # Per bank write bursts system.physmem.perBankRdBursts::4 298 # Per bank write bursts system.physmem.perBankRdBursts::5 299 # Per bank write bursts -system.physmem.perBankRdBursts::6 264 # Per bank write bursts -system.physmem.perBankRdBursts::7 216 # Per bank write bursts +system.physmem.perBankRdBursts::6 265 # Per bank write bursts +system.physmem.perBankRdBursts::7 218 # Per bank write bursts system.physmem.perBankRdBursts::8 246 # Per bank write bursts -system.physmem.perBankRdBursts::9 215 # Per bank write bursts +system.physmem.perBankRdBursts::9 214 # Per bank write bursts system.physmem.perBankRdBursts::10 289 # Per bank write bursts -system.physmem.perBankRdBursts::11 193 # Per bank write bursts -system.physmem.perBankRdBursts::12 189 # Per bank write bursts -system.physmem.perBankRdBursts::13 206 # Per bank write bursts -system.physmem.perBankRdBursts::14 217 # Per bank write bursts +system.physmem.perBankRdBursts::11 192 # Per bank write bursts +system.physmem.perBankRdBursts::12 190 # Per bank write bursts +system.physmem.perBankRdBursts::13 208 # Per bank write bursts +system.physmem.perBankRdBursts::14 219 # Per bank write bursts system.physmem.perBankRdBursts::15 200 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 74219912500 # Total gap between requests +system.physmem.totGap 74211752000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3794 # Read request sizes (log2) +system.physmem.readPktSize::6 3799 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -154,101 +154,102 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.192469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.652659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 576.534776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 257 35.84% 35.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 120 16.74% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 71 9.90% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 49 6.83% 69.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 19 2.65% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 26 3.63% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 20 2.79% 78.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 17 2.37% 80.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 17 2.37% 83.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 40 5.58% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 17 2.37% 91.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 6 0.84% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 6 0.84% 92.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 8 1.12% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 6 0.84% 94.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 5 0.70% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 4 0.56% 95.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 1 0.14% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.28% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 2 0.28% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 2 0.28% 96.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 2 0.28% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.14% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 1 0.14% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.14% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.14% 97.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 1 0.14% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 2 0.28% 98.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 1 0.14% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 2 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 1 0.14% 98.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 1 0.14% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 1 0.14% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 1 0.14% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 1 0.14% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 1 0.14% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 1 0.14% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 1 0.14% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.14% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 1 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation -system.physmem.totQLat 25208000 # Total ticks spent queuing -system.physmem.totMemAccLat 100718000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 18970000 # Total ticks spent in databus transfers -system.physmem.totBankLat 56540000 # Total ticks spent accessing banks -system.physmem.avgQLat 6644.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14902.48 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.476190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.440190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 401.372897 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 87 34.52% 34.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58 23.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17 6.75% 64.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 1.98% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 2.78% 69.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 3.17% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.59% 73.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.19% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 63 25.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 252 # Bytes accessed per row activation +system.physmem.totQLat 23847500 # Total ticks spent queuing +system.physmem.totMemAccLat 100702500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 18995000 # Total ticks spent in databus transfers +system.physmem.totBankLat 57860000 # Total ticks spent accessing banks +system.physmem.avgQLat 6277.31 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15230.32 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26546.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26507.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3077 # Number of row buffer hits during reads +system.physmem.readRowHits 3018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19562443.99 # Average gap between requests -system.physmem.pageHitRate 81.10 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.24 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 3270712 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 2723 # Transaction distribution -system.membus.trans_dist::ReadResp 2722 # Transaction distribution +system.physmem.avgGap 19534549.09 # Average gap between requests +system.physmem.pageHitRate 79.44 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.21 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 3275383 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2728 # Transaction distribution +system.membus.trans_dist::ReadResp 2727 # Transaction distribution system.membus.trans_dist::ReadExReq 1071 # Transaction distribution system.membus.trans_dist::ReadExResp 1071 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7587 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 242752 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 242752 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7597 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 243072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 243072 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 4681000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4687500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35532250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35592500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 94784239 # Number of BP lookups -system.cpu.branchPred.condPredicted 74783977 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6281559 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44678373 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43049971 # Number of BTB hits +system.cpu.branchPred.lookups 94795806 # Number of BP lookups +system.cpu.branchPred.condPredicted 74795654 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6279989 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44691885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43051051 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.355279 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4356641 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88400 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.328564 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354918 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88426 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -334,135 +335,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148439863 # number of cpu cycles simulated +system.cpu.numCycles 148423542 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39656875 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380179667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94784239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47406612 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80370607 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27283097 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7220794 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6206 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39654967 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380195915 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94795806 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47405969 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80368300 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27279262 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7212539 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5988 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 50 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36850851 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1831977 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801605 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 36848695 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1833193 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802047 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153051 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68038529 45.90% 45.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5265458 3.55% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540663 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10285699 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8660453 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6545120 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6246377 4.21% 77.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8002820 5.40% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24655172 16.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68026374 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5263091 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10536182 7.11% 56.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285653 6.94% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8660137 5.84% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6544581 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6243734 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8007959 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24657510 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148240291 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638536 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.561170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45513767 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5886575 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74804066 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1203498 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20832385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14327909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164350 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392779624 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 733803 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20832385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50900716 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 730751 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 603183 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70558259 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4614997 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371307860 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 42 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 339068 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3661204 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 148225221 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638684 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.561561 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45510679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5881311 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74801618 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1201370 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20830243 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14327753 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164034 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392767808 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 749358 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20830243 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50895494 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 723680 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602483 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70555782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4617539 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371309891 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 37 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 338990 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3664355 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 25 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631703204 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1588513521 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1506815662 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3203425 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 631718613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1588504211 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1506839397 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3198087 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333659065 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25072 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25068 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13010227 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43012674 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16416368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5733538 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3666489 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329189946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47154 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249456447 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 789359 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139503196 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 362394637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1938 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148240291 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.682784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761427 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333674474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25005 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13030816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 43005440 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16429294 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5701095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3639070 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329189812 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47090 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249460239 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787524 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139505237 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 362363758 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1874 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148225221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.682981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761692 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56059626 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22638758 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24824129 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20343397 13.72% 83.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12534810 8.46% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6516110 4.40% 96.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4026087 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1116064 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181310 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56054819 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22642547 15.28% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24806201 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20327492 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12550892 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6518173 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4029511 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113373 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182213 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148240291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148225221 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 965209 38.57% 38.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5593 0.22% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1158969 46.31% 85.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372730 14.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 964965 38.34% 38.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5593 0.22% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 99 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 49 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1170821 46.51% 85.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375623 14.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194899827 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 979613 0.39% 78.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194894311 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979316 0.39% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued @@ -481,93 +482,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33082 0.01% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164367 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255141 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76420 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 466123 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206380 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71866 0.03% 79.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33075 0.01% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164356 0.07% 78.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254647 0.10% 78.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76432 0.03% 78.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465549 0.19% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206388 0.08% 79.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71859 0.03% 79.03% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38355265 15.38% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13948042 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38358541 15.38% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13955444 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249456447 # Type of FU issued -system.cpu.iq.rate 1.680522 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2502650 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010032 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646705187 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466563017 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237885267 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3740007 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2195697 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1842613 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250082678 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1876419 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2013206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249460239 # Type of FU issued +system.cpu.iq.rate 1.680732 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2517150 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646712991 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466571759 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237891174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3737382 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2188885 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1841279 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250102160 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875229 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007089 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13163190 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11604 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3771734 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13155956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11631 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18977 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3784660 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 107 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 11 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20832385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18544 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 886 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329254297 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 785292 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43012674 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16416368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24746 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 181 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3889950 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3760088 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7650038 # Number of branch mispredicts detected at execute +system.cpu.iew.iewSquashCycles 20830243 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18508 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 911 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329253924 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 785902 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 43005440 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16429294 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24682 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 206 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18977 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3891616 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3758665 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7650281 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 242960344 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36851914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6496103 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts 36855491 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6499895 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 17197 # number of nop insts executed -system.cpu.iew.exec_refs 50500351 # number of memory reference insts executed -system.cpu.iew.exec_branches 53426054 # Number of branches executed -system.cpu.iew.exec_stores 13648437 # Number of stores executed -system.cpu.iew.exec_rate 1.636759 # Inst execution rate -system.cpu.iew.wb_sent 240785488 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239727880 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148473973 # num instructions producing a value -system.cpu.iew.wb_consumers 267261246 # num instructions consuming a value +system.cpu.iew.exec_nop 17022 # number of nop insts executed +system.cpu.iew.exec_refs 50506525 # number of memory reference insts executed +system.cpu.iew.exec_branches 53424421 # Number of branches executed +system.cpu.iew.exec_stores 13651034 # Number of stores executed +system.cpu.iew.exec_rate 1.636939 # Inst execution rate +system.cpu.iew.wb_sent 240787816 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239732453 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148473522 # num instructions producing a value +system.cpu.iew.wb_consumers 267271209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.614983 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555539 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555516 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140583409 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140583033 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6128231 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127407906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480841 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.185453 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6126865 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127394978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.480992 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57701601 45.29% 45.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31696921 24.88% 70.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13777775 10.81% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7640604 6.00% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4387783 3.44% 90.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321955 1.04% 91.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703214 1.34% 92.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1308007 1.03% 93.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7870046 6.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57713917 45.30% 45.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31674198 24.86% 70.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13788488 10.82% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7625423 5.99% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4380329 3.44% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321262 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1701589 1.34% 92.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1311888 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877884 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127407906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127394978 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,230 +579,230 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7870046 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877884 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448786959 # The number of ROB reads -system.cpu.rob.rob_writes 679450685 # The number of ROB writes -system.cpu.timesIdled 2806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199572 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448765817 # The number of ROB reads +system.cpu.rob.rob_writes 679447245 # The number of ROB writes +system.cpu.timesIdled 2831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 198321 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads -system.cpu.ipc 1.160760 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.160760 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079416198 # number of integer regfile reads -system.cpu.int_regfile_writes 384871537 # number of integer regfile writes -system.cpu.fp_regfile_reads 2913086 # number of floating regfile reads -system.cpu.fp_regfile_writes 2499105 # number of floating regfile writes -system.cpu.misc_regfile_reads 64870078 # number of misc regfile reads +system.cpu.cpi 0.861410 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861410 # CPI: Total CPI of All Threads +system.cpu.ipc 1.160887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.160887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079439987 # number of integer regfile reads +system.cpu.int_regfile_writes 384873432 # number of integer regfile writes +system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads +system.cpu.fp_regfile_writes 2497165 # number of floating regfile writes +system.cpu.misc_regfile_reads 64868455 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.toL2Bus.throughput 5170363 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 4900 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 4899 # Transaction distribution +system.cpu.toL2Bus.throughput 5152821 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4879 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4878 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 18 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1079 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1079 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11975 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 264064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 383744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 383744 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8203 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11933 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 262464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 382400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 382400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3016500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3006000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6553746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6511747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3047989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051239 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 2395 # number of replacements -system.cpu.icache.tags.tagsinuse 1347.740461 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 36845513 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4126 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8930.080708 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2374 # number of replacements +system.cpu.icache.tags.tagsinuse 1347.666302 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 36843383 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8983.999756 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740461 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 73705828 # Number of tag accesses -system.cpu.icache.tags.data_accesses 73705828 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 36845513 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36845513 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36845513 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36845513 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36845513 # number of overall hits -system.cpu.icache.overall_hits::total 36845513 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5338 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5338 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5338 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5338 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5338 # number of overall misses -system.cpu.icache.overall_misses::total 5338 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 225943745 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 225943745 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 225943745 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 225943745 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 225943745 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36850851 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36850851 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36850851 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36850851 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36850851 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000145 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000145 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000145 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000145 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000145 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42327.415699 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42327.415699 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42327.415699 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42327.415699 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1128 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1347.666302 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.658040 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1727 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1040 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.843262 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 73701491 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73701491 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 36843383 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36843383 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36843383 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36843383 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36843383 # number of overall hits +system.cpu.icache.overall_hits::total 36843383 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5312 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5312 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5312 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5312 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5312 # number of overall misses +system.cpu.icache.overall_misses::total 5312 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 224724996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 224724996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 224724996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 224724996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 224724996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36848695 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36848695 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36848695 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36848695 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36848695 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000144 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000144 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000144 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000144 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000144 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42305.157380 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42305.157380 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42305.157380 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42305.157380 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1646 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.368421 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.631579 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1211 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1211 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1211 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1211 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1211 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4127 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4127 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4127 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4127 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4127 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168102254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168102254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168102254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168102254 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40732.312576 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40732.312576 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40732.312576 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40732.312576 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117257250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101142000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 218399250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.871928 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.555714 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1750 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3799 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117223750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 41708750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 158932500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59427500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117223750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101136250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 218360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117223750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101136250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 218360000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.873874 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992586 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992586 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.634554 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942225 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.634554 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57226.573939 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62760.014837 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58596.217407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54940.943044 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57226.573939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.031519 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57564.377965 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.637630 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.499512 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942888 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.637630 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57210.224500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61426.730486 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58259.714076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55487.861811 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57210.224500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57792.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57478.283759 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1406.103051 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46786126 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1852 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25262.487041 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 59 # number of replacements +system.cpu.dcache.tags.tagsinuse 1407.038554 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46795712 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1856 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25213.206897 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103051 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1407.038554 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.343515 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 93593354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 93593354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 34384681 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34384681 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356564 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22474 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22474 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.438721 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 93612504 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93612504 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 34394263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34394263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356566 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356566 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22476 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22476 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46741245 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46741245 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46741245 # number of overall hits -system.cpu.dcache.overall_hits::total 46741245 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1900 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1900 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7723 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7723 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46750829 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46750829 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46750829 # number of overall hits +system.cpu.dcache.overall_hits::total 46750829 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7721 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7721 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9623 # number of overall misses -system.cpu.dcache.overall_misses::total 9623 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 121712227 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 121712227 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 465623746 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 465623746 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9610 # number of overall misses +system.cpu.dcache.overall_misses::total 9610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 119060977 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 119060977 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 479134996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 479134996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 142500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 587335973 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 587335973 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 587335973 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34386581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34386581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598195973 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598195973 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598195973 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34396152 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34396152 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22476 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22476 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22478 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22478 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46750868 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46750868 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46750868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46750868 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46760439 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46760439 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46760439 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46760439 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000624 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64059.066842 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64059.066842 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60290.527774 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60290.527774 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.574378 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.574378 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62056.080300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62056.080300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61034.601787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61034.601787 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 314 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62247.239646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62247.239646 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 566 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 318 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.818182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 78.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 79.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks system.cpu.dcache.writebacks::total 18 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6645 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6645 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1111 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1111 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7771 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7771 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7771 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7754 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7754 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7754 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 778 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1078 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1078 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53118011 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73393498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 126511509 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126511509 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 126511509 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1856 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1856 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1856 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 52580511 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 73988748 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 126569259 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 126569259 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 126569259 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses @@ -990,14 +991,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68627.921189 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68083.022263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68310.750000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68310.750000 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67584.204370 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68635.202226 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68194.643858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68194.643858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 1427887bb..cc1011ed3 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144463 # Number of seconds simulated -sim_ticks 144463317000 # Number of ticks simulated -final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144377 # Number of seconds simulated +sim_ticks 144377116000 # Number of ticks simulated +final_tick 144377116000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81167 # Simulator instruction rate (inst/s) -host_op_rate 136043 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88782348 # Simulator tick rate (ticks/s) -host_mem_usage 282908 # Number of bytes of host memory used -host_seconds 1627.16 # Real time elapsed on the host +host_inst_rate 66784 # Simulator instruction rate (inst/s) +host_op_rate 111936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73006862 # Simulator tick rate (ticks/s) +host_mem_usage 319660 # Number of bytes of host memory used +host_seconds 1977.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory -system.physmem.bytes_read::total 342656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5354 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1502721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 869203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2371924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1502721 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1502721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 869203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2371924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5354 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory +system.physmem.bytes_read::total 343040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5360 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1509824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 866176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2376000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1509824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1509824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 866176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2376000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5361 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5354 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5361 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 342656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 343104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 342656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 343104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 163 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 289 # Per bank write bursts -system.physmem.perBankRdBursts::1 357 # Per bank write bursts -system.physmem.perBankRdBursts::2 453 # Per bank write bursts -system.physmem.perBankRdBursts::3 356 # Per bank write bursts -system.physmem.perBankRdBursts::4 332 # Per bank write bursts -system.physmem.perBankRdBursts::5 326 # Per bank write bursts -system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 377 # Per bank write bursts -system.physmem.perBankRdBursts::8 341 # Per bank write bursts -system.physmem.perBankRdBursts::9 276 # Per bank write bursts -system.physmem.perBankRdBursts::10 232 # Per bank write bursts -system.physmem.perBankRdBursts::11 277 # Per bank write bursts -system.physmem.perBankRdBursts::12 205 # Per bank write bursts -system.physmem.perBankRdBursts::13 465 # Per bank write bursts -system.physmem.perBankRdBursts::14 384 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 150 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 281 # Per bank write bursts +system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts +system.physmem.perBankRdBursts::3 351 # Per bank write bursts +system.physmem.perBankRdBursts::4 335 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts +system.physmem.perBankRdBursts::7 381 # Per bank write bursts +system.physmem.perBankRdBursts::8 343 # Per bank write bursts +system.physmem.perBankRdBursts::9 292 # Per bank write bursts +system.physmem.perBankRdBursts::10 228 # Per bank write bursts +system.physmem.perBankRdBursts::11 284 # Per bank write bursts +system.physmem.perBankRdBursts::12 208 # Per bank write bursts +system.physmem.perBankRdBursts::13 469 # Per bank write bursts +system.physmem.perBankRdBursts::14 386 # Per bank write bursts system.physmem.perBankRdBursts::15 282 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 144463266500 # Total gap between requests +system.physmem.totGap 144377080000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5354 # Read request sizes (log2) +system.physmem.readPktSize::6 5361 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 145 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -154,346 +154,337 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.307957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 612.115437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 385 40.23% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 164 17.14% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 81 8.46% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 46 4.81% 70.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 43 4.49% 75.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 20 2.09% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 26 2.72% 79.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 19 1.99% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 17 1.78% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 26 2.72% 86.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 27 2.82% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 7 0.73% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 7 0.73% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 7 0.73% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 3 0.31% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 5 0.52% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 6 0.63% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 6 0.63% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 4 0.42% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 2 0.21% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 2 0.21% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 3 0.31% 94.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 7 0.73% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 1 0.10% 95.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 5 0.52% 96.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 4 0.42% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 2 0.21% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 2 0.21% 96.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 2 0.21% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 3 0.31% 97.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 2 0.21% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 1 0.10% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 1 0.10% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 1 0.10% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 1 0.10% 98.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 1 0.10% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 2 0.21% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 1 0.10% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 2 0.21% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 3 0.31% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 1 0.10% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 1 0.10% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 1 0.10% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation -system.physmem.totQLat 28783000 # Total ticks spent queuing -system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers -system.physmem.totBankLat 82293750 # Total ticks spent accessing banks -system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 508.672783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.998238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 425.682375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 88 26.91% 26.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 53 16.21% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 8.56% 51.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 4.89% 56.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 2.75% 59.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 1.83% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 0.92% 62.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 0.92% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 121 37.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 327 # Bytes accessed per row activation +system.physmem.totQLat 28551000 # Total ticks spent queuing +system.physmem.totMemAccLat 139987250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 84631250 # Total ticks spent accessing banks +system.physmem.avgQLat 5325.69 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 15786.47 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26112.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4397 # Number of row buffer hits during reads +system.physmem.readRowHits 4274 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26982306.03 # Average gap between requests -system.physmem.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.41 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 2371924 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 3822 # Transaction distribution -system.membus.trans_dist::ReadResp 3822 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution -system.membus.trans_dist::UpgradeResp 163 # Transaction distribution -system.membus.trans_dist::ReadExReq 1532 # Transaction distribution -system.membus.trans_dist::ReadExResp 1532 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 342656 # Total data (bytes) +system.physmem.avgGap 26930997.95 # Average gap between requests +system.physmem.pageHitRate 79.72 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.40 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 2375113 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3828 # Transaction distribution +system.membus.trans_dist::ReadResp 3825 # Transaction distribution +system.membus.trans_dist::UpgradeReq 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::ReadExReq 1533 # Transaction distribution +system.membus.trans_dist::ReadExResp 1533 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11019 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11019 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342912 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342912 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6993500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50706850 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18648233 # Number of BP lookups -system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits +system.cpu.branchPred.lookups 18662333 # Number of BP lookups +system.cpu.branchPred.condPredicted 18662333 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1490477 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11407057 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10802916 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.703796 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1319575 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23217 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289221873 # number of cpu cycles simulated +system.cpu.numCycles 289035036 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23466628 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206674196 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18662333 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12122491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54224578 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15529649 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177872737 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1739 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9780 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22363082 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227556 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757498 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216567147 80.40% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2849140 1.06% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2312743 0.86% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640443 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3223496 1.20% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3388678 1.26% 85.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3828931 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2559342 0.95% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31982800 11.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269352720 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064568 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36872291 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 166882879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41583049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10237266 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13777235 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336030589 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13777235 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44927552 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116592006 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 33482 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42725844 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51296601 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329644603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10793 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25973281 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22738118 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382392326 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917644681 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605892364 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4122807 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 122962876 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2119 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 104910685 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84442386 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30099715 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58118082 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18905602 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322699954 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4280 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260615725 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 114961 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100953398 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209924725 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3035 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269352720 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.967563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344835 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143250903 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55370436 20.56% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34176648 12.69% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19094867 7.09% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10869897 4.04% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4155062 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1825131 0.68% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476500 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133276 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269352720 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130941 4.84% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2275620 84.10% 88.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 299199 11.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210799 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162097443 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790400 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035783 2.70% 65.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1447528 0.56% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65478586 25.12% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22555186 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued -system.cpu.iq.rate 0.900699 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260615725 # Type of FU issued +system.cpu.iq.rate 0.901675 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2705760 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788512519 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420334227 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255242293 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4892372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3608187 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2352192 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259648600 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2462086 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18920241 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27792799 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 290410 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9583998 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 49921 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13777235 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85064772 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5446513 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322704234 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 135340 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84442386 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30099715 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2049 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2678194 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 290410 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 639185 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 902051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1541236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258833919 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64703526 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1781806 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed -system.cpu.iew.exec_branches 14265859 # Number of branches executed -system.cpu.iew.exec_stores 22347175 # Number of stores executed -system.cpu.iew.exec_rate 0.894581 # Inst execution rate -system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 205928299 # num instructions producing a value -system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value +system.cpu.iew.exec_refs 87053484 # number of memory reference insts executed +system.cpu.iew.exec_branches 14272898 # Number of branches executed +system.cpu.iew.exec_stores 22349958 # Number of stores executed +system.cpu.iew.exec_rate 0.895511 # Inst execution rate +system.cpu.iew.wb_sent 258192676 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257594485 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206043233 # num instructions producing a value +system.cpu.iew.wb_consumers 369200904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back +system.cpu.iew.wb_rate 0.891222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.558079 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101415579 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1491917 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255575485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.866137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.656618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156360594 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57109316 22.35% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13985683 5.47% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12037857 4.71% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4182593 1.64% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2963821 1.16% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 909345 0.36% 96.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1046624 0.41% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6979652 2.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255575485 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -504,240 +495,240 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6979652 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571692690 # The number of ROB reads -system.cpu.rob.rob_writes 659422914 # The number of ROB writes -system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571374796 # The number of ROB reads +system.cpu.rob.rob_writes 659361249 # The number of ROB writes +system.cpu.timesIdled 5927783 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19682316 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 451224153 # number of integer regfile reads -system.cpu.int_regfile_writes 233957254 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes -system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads -system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes -system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads +system.cpu.cpi 2.188479 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.188479 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456938 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456938 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 451403378 # number of integer regfile reads +system.cpu.int_regfile_writes 234040975 # number of integer regfile writes +system.cpu.fp_regfile_reads 3219859 # number of floating regfile reads +system.cpu.fp_regfile_writes 2011879 # number of floating regfile writes +system.cpu.cc_regfile_reads 102824885 # number of cc regfile reads +system.cpu.cc_regfile_writes 59817361 # number of cc regfile writes +system.cpu.misc_regfile_reads 133392985 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13403 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17751 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 423616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 552704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 552704 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 10496 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 3846371 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7121 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 15 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 150 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13184 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 417024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 545664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 545664 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 9664 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4430500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10573999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3437150 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 4653 # number of replacements -system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4547 # number of replacements +system.cpu.icache.tags.tagsinuse 1629.451963 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22354297 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6517 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3430.151450 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1967 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.960449 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 44713203 # Number of tag accesses -system.cpu.icache.tags.data_accesses 44713203 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits -system.cpu.icache.overall_hits::total 22344300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses -system.cpu.icache.overall_misses::total 8910 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1629.451963 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.795631 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1970 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 757 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 807 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.961914 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 44732829 # Number of tag accesses +system.cpu.icache.tags.data_accesses 44732829 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22354297 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22354297 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22354297 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22354297 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22354297 # number of overall hits +system.cpu.icache.overall_hits::total 22354297 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8784 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8784 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8784 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8784 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8784 # number of overall misses +system.cpu.icache.overall_misses::total 8784 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365846249 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365846249 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365846249 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365846249 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365846249 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22363081 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22363081 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22363081 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22363081 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22363081 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000393 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000393 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000393 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000393 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000393 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41649.163138 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41649.163138 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41649.163138 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41649.163138 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 800 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2116 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6668 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6668 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6668 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1500150 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1500150 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85063500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85063500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 191583500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112656000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304239500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 191583500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112656000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 304239500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.921225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.548896 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994809 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994809 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.629595 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.522787 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977978 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.629595 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56232.315820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65540.380048 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57256.008359 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55488.258317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56232.315820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57654.042989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56750.512964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 57 # number of replacements -system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1432.023881 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66143701 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33154.737343 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1432.023881 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349615 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 132211530 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 132211530 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits -system.cpu.dcache.overall_hits::total 66102126 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses -system.cpu.dcache.overall_misses::total 2637 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 427 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1393 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.473145 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 132294203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 132294203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45629460 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45629460 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514040 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66143500 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66143500 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66143500 # number of overall hits +system.cpu.dcache.overall_hits::total 66143500 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 913 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 913 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1691 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1691 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2604 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2604 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2604 # number of overall misses +system.cpu.dcache.overall_misses::total 2604 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59632801 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59632801 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 113805150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 113805150 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 173437951 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 173437951 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 173437951 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45630373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45630373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67126.809626 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67126.809626 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66925.477673 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66925.477673 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66996.863860 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66996.863860 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 66146104 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66146104 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66146104 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66146104 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65315.225630 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65315.225630 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67300.502661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67300.502661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66604.435868 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66604.435868 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.750000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 13 # number of writebacks -system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 468 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 468 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 15 # number of writebacks +system.cpu.dcache.writebacks::total 15 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 455 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 455 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 467 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1701 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1701 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33590500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 109769587 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 143360087 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143360087 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 143360087 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 456 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 456 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 456 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1690 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1690 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33615250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 109709600 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 143324850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 143324850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 143324850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000083 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71928.265525 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64532.385068 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66125.501384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66125.501384 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000082 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73395.742358 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64916.923077 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66724.790503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66724.790503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |