diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-18 10:30:04 -0400 |
| commit | d2b57a7473768e8aff3707916b40b264cab6821c (patch) | |
| tree | f4e64db0a8bb23dd26a1c8f1ec5b887be346f625 /tests/long/se | |
| parent | 7c55464aac2bcab15699e563f18a7d3d565d949a (diff) | |
| download | gem5-d2b57a7473768e8aff3707916b40b264cab6821c.tar.xz | |
Stats: Update stats to reflect SimpleMemory bandwidth
This patch simply bumps the stats to reflect the introduction of a
bandwidth limit of 12.8GB/s for SimpleMemory.
Diffstat (limited to 'tests/long/se')
15 files changed, 5603 insertions, 5604 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 5b9902e79..56312634f 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.274137 # Number of seconds simulated -sim_ticks 274137499500 # Number of ticks simulated -final_tick 274137499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 274137453500 # Number of ticks simulated +final_tick 274137453500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167497 # Simulator instruction rate (inst/s) -host_op_rate 167497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76292716 # Simulator tick rate (ticks/s) -host_mem_usage 218988 # Number of bytes of host memory used -host_seconds 3593.23 # Real time elapsed on the host +host_inst_rate 134061 # Simulator instruction rate (inst/s) +host_op_rate 134061 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61063086 # Simulator tick rate (ticks/s) +host_mem_usage 219148 # Number of bytes of host memory used +host_seconds 4489.41 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -24,32 +24,32 @@ system.physmem.num_reads::total 26157 # Nu system.physmem.num_writes::writebacks 891 # Number of write requests responded to by this memory system.physmem.num_writes::total 891 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 196339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5910260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6106600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5910261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6106601 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 196339 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 196339 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 208012 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 208012 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 208012 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 196339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5910260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6314612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5910261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6314613 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114518785 # DTB read hits +system.cpu.dtb.read_hits 114518787 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114521416 # DTB read accesses -system.cpu.dtb.write_hits 39662429 # DTB write hits +system.cpu.dtb.read_accesses 114521418 # DTB read accesses +system.cpu.dtb.write_hits 39662426 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39664731 # DTB write accesses -system.cpu.dtb.data_hits 154181214 # DTB hits +system.cpu.dtb.write_accesses 39664728 # DTB write accesses +system.cpu.dtb.data_hits 154181213 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 154186147 # DTB accesses +system.cpu.dtb.data_accesses 154186146 # DTB accesses system.cpu.itb.fetch_hits 25086764 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 548275000 # number of cpu cycles simulated +system.cpu.numCycles 548274908 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 86322538 # Number of BP lookups @@ -80,13 +80,13 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu system.cpu.branch_predictor.BTBHitPct 64.827784 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 36908227 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 49414311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541561070 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 541561072 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1005415916 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1005415918 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255070177 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255070175 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 155050348 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 33771595 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2589470 # Number of Branches Incorrectly Predicted As Not Taken). @@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 412334459 # Nu system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 539843930 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 539843953 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 672410 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59138192 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 489136808 # Number of cycles cpu stages are processed. -system.cpu.activity 89.213772 # Percentage of cycles cpu is active +system.cpu.timesIdled 672397 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59138093 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 489136815 # Number of cycles cpu stages are processed. +system.cpu.activity 89.213788 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -120,28 +120,28 @@ system.cpu.cpi_total 0.910972 # CP system.cpu.ipc 1.097728 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 1.097728 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 209383014 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338891986 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.810585 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 237433241 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310841759 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 56.694498 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 206489440 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341785560 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 62.338345 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 436702963 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 209382923 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338891985 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.810595 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 237433150 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310841758 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 56.694507 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 206489347 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341785561 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 62.338355 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 436702871 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 111572037 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.349649 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 201266098 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 347008902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 63.291031 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 20.349652 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 201266007 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 347008901 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 63.291042 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 728.512372 # Cycle average of tags in use +system.cpu.icache.tagsinuse 728.512382 # Cycle average of tags in use system.cpu.icache.total_refs 25085741 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29340.047953 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 728.512372 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 728.512382 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.355719 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.355719 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 25085741 # number of ReadReq hits @@ -220,12 +220,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54774.853801 system.cpu.icache.overall_avg_mshr_miss_latency::total 54774.853801 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.836595 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4093.836594 # Cycle average of tags in use system.cpu.dcache.total_refs 152406041 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 334.667796 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 294657000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.836595 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.836594 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999472 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999472 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 114120497 # number of ReadReq hits @@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 1559322 # n system.cpu.dcache.demand_misses::total 1559322 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1559322 # number of overall misses system.cpu.dcache.overall_misses::total 1559322 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7771987500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228669000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30228669000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38000656500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38000656500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38000656500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38000656500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7771987000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7771987000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30228329000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30228329000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38000316000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38000316000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38000316000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38000316000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -268,19 +268,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010128 system.cpu.dcache.demand_miss_rate::total 0.010128 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010128 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010128 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.662796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.662796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25930.061238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25930.061238 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24369.986763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.986763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24369.986763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28255500 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19748.661525 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19748.661525 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25929.769587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25929.769587 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24369.768399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24369.768399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24369.768399 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28216000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 3255084000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3561 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3564 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211493 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7934.709351 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7916.947250 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 15390.977479 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136800000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136800000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820778500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7820778500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820778500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7820778500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2683978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2683978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5136655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5136655500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7820633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7820633500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7820633500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7820633500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -318,24 +318,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.732070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.732070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.652219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.652219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.615213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.615213 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.729586 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.729586 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20210.083686 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20210.083686 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17173.296808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17173.296808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 917 # number of replacements -system.cpu.l2cache.tagsinuse 22837.818259 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22837.818508 # Cycle average of tags in use system.cpu.l2cache.total_refs 538848 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23142 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 23.284418 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21635.297134 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 719.415397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 483.105728 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21635.297320 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 719.415407 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 483.105781 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.660257 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.021955 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.014743 # Average percentage of cache occupancy @@ -365,16 +365,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 841 # system.cpu.l2cache.overall_misses::cpu.data 25316 # number of overall misses system.cpu.l2cache.overall_misses::total 26157 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45384000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 260244500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215316500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1215316500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 214860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 260244000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1215397500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1215397500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 45384000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1430177000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1475561000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1430257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1475641500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 45384000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1430177000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1475561000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1430257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1475641500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201219 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202074 # number of ReadReq accesses(hits+misses) @@ -400,21 +400,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 system.cpu.l2cache.overall_miss_rate::cpu.data 0.055591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057330 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53964.328181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.606796 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52458.072969 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57337.068315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57337.068315 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52150.485437 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52457.972183 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 57340.889791 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 57340.889791 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 56411.706235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 56414.783805 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53964.328181 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56493.008374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 56411.706235 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3459500 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56496.188181 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 56414.783805 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3419500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 116 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 115 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29823.275862 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29734.782609 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26157 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35146000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 165361000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200507000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954428500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954428500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 954509500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 954509500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119789500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1154935500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1119870500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1155016500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119789500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1154935500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1119870500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1155016500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020475 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024550 # mshr miss rate for ReadReq accesses @@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.057330 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41790.725327 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40136.165049 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40416.649869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45028.708247 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45028.708247 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45032.529723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45032.529723 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41790.725327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44232.481435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44153.974080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44235.680992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44157.070765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 5f66a5052..f78f2bef4 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.135505 # Number of seconds simulated -sim_ticks 135504709500 # Number of ticks simulated -final_tick 135504709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.135471 # Number of seconds simulated +sim_ticks 135471331500 # Number of ticks simulated +final_tick 135471331500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 302966 # Simulator instruction rate (inst/s) -host_op_rate 302966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72589653 # Simulator tick rate (ticks/s) -host_mem_usage 220016 # Number of bytes of host memory used -host_seconds 1866.72 # Real time elapsed on the host +host_inst_rate 255662 # Simulator instruction rate (inst/s) +host_op_rate 255662 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61240707 # Simulator tick rate (ticks/s) +host_mem_usage 220172 # Number of bytes of host memory used +host_seconds 2212.11 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1627200 # Number of bytes read from this memory -system.physmem.bytes_read::total 1688960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 58880 # Number of bytes written to this memory -system.physmem.bytes_written::total 58880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25425 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 920 # Number of write requests responded to by this memory -system.physmem.num_writes::total 920 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 455778 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12008439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12464216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 455778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 434524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 434524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 434524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 455778 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12008439 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12898740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1627392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1689280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 58944 # Number of bytes written to this memory +system.physmem.bytes_written::total 58944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25428 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26395 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 921 # Number of write requests responded to by this memory +system.physmem.num_writes::total 921 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 456835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12012815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12469649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 456835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 435103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 435103 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 435103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 456835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12012815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12904752 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 123973202 # DTB read hits -system.cpu.dtb.read_misses 28801 # DTB read misses +system.cpu.dtb.read_hits 123970603 # DTB read hits +system.cpu.dtb.read_misses 28720 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124002003 # DTB read accesses -system.cpu.dtb.write_hits 40826098 # DTB write hits -system.cpu.dtb.write_misses 43038 # DTB write misses +system.cpu.dtb.read_accesses 123999323 # DTB read accesses +system.cpu.dtb.write_hits 40821734 # DTB write hits +system.cpu.dtb.write_misses 42993 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 40869136 # DTB write accesses -system.cpu.dtb.data_hits 164799300 # DTB hits -system.cpu.dtb.data_misses 71839 # DTB misses +system.cpu.dtb.write_accesses 40864727 # DTB write accesses +system.cpu.dtb.data_hits 164792337 # DTB hits +system.cpu.dtb.data_misses 71713 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 164871139 # DTB accesses -system.cpu.itb.fetch_hits 66654125 # ITB hits +system.cpu.dtb.data_accesses 164864050 # DTB accesses +system.cpu.itb.fetch_hits 66629589 # ITB hits system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 66654164 # ITB accesses +system.cpu.itb.fetch_accesses 66629628 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,140 +67,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 271009420 # number of cpu cycles simulated +system.cpu.numCycles 270942664 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 78550084 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 72909802 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3049618 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 42960098 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 41697412 # Number of BTB hits +system.cpu.BPredUnit.lookups 78540801 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 72908130 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 3045250 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 42784442 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 41679238 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1627945 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 225 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68633140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 712310900 # Number of instructions fetch has processed -system.cpu.fetch.Branches 78550084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43325357 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 119402153 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13096957 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 72942972 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1625962 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68608304 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 712216936 # Number of instructions fetch has processed +system.cpu.fetch.Branches 78540801 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43305200 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 119376688 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13084394 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 72934666 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 66654125 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 952316 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 270973447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.628711 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.455670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66629589 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 948387 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 270906593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.629013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.455853 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 151571294 55.94% 55.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10370513 3.83% 59.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11843929 4.37% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10611726 3.92% 68.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6997698 2.58% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2669321 0.99% 71.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3542857 1.31% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3106060 1.15% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 70260049 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 151529905 55.93% 55.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10364245 3.83% 59.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11839822 4.37% 64.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10610225 3.92% 68.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 6991463 2.58% 70.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2667986 0.98% 71.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3540757 1.31% 72.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3105472 1.15% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 70256718 25.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270973447 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.289843 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.628362 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 86239898 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 56889648 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 104078394 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13772489 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9993018 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3907857 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703284399 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 4152 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9993018 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 94515684 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12291800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1567 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104313558 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49857820 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 691204157 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5604 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37465189 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 6251536 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 527653035 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 907560525 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 907557502 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3023 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 270906593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.289880 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.628663 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 86218522 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 56873885 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 104030125 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13799230 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9984831 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3903379 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1089 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703205131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4386 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9984831 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 94485896 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12289062 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1666 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104300720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49844418 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 691143238 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5409 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 37459217 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 6250189 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 527606706 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 907468723 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 907465803 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2920 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 63798146 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 98 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 109 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110554649 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 129201281 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42494660 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14706454 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9724071 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 626942555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608726605 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 349964 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60693556 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33842727 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270973447 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.246444 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.833475 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 63751817 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 108 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 122 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 110700400 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 129196942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42484118 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14760258 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9703253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 626892028 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 99 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608695355 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 350153 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60644934 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33797171 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270906593 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.246883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.833563 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55588929 20.51% 20.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55068872 20.32% 40.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 54063102 19.95% 60.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36829632 13.59% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31174989 11.50% 85.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23761374 8.77% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10484912 3.87% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3386761 1.25% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 614876 0.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55377469 20.44% 20.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55325876 20.42% 40.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 54071762 19.96% 60.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36846414 13.60% 74.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30891550 11.40% 85.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23842623 8.80% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10560250 3.90% 98.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3379294 1.25% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 611355 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270973447 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270906593 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2718607 75.19% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 33 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 573635 15.86% 91.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 323505 8.95% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2755770 75.48% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 75.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 573872 15.72% 91.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 321392 8.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 441168683 72.47% 72.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7348 0.00% 72.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 441149057 72.47% 72.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7297 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 30 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 5 0.00% 72.48% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 126287390 20.75% 93.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41263140 6.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 126283457 20.75% 93.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41255500 6.78% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608726605 # Type of FU issued -system.cpu.iq.rate 2.246146 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3615780 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005940 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1492388483 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 687638825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 598965859 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3918 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2476 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608695355 # Type of FU issued +system.cpu.iq.rate 2.246584 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3651064 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005998 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1492294648 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 687539732 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 598944947 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3872 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2425 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1713 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 612340430 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1955 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12180256 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 612344476 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1943 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12180058 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14687239 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 33196 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5150 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3043339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14682900 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 33847 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5158 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3032797 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6743 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 162277 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6745 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 162513 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9993018 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 593522 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 81920 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 671227772 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1733098 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 129201281 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42494660 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9721 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 904 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5150 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1349008 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2205914 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3554922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 602873827 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 124002105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5852778 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 9984831 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 591994 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80208 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 671175480 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1733020 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 129196942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42484118 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 99 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8476 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 909 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5158 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1342632 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 2208039 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3550671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 602850413 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 123999444 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5844942 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 44285129 # number of nop insts executed -system.cpu.iew.exec_refs 164888589 # number of memory reference insts executed -system.cpu.iew.exec_branches 67046898 # Number of branches executed -system.cpu.iew.exec_stores 40886484 # Number of stores executed -system.cpu.iew.exec_rate 2.224549 # Inst execution rate -system.cpu.iew.wb_sent 600233130 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 598967572 # cumulative count of insts written-back -system.cpu.iew.wb_producers 417280903 # num instructions producing a value -system.cpu.iew.wb_consumers 532263406 # num instructions consuming a value +system.cpu.iew.exec_nop 44283353 # number of nop insts executed +system.cpu.iew.exec_refs 164880697 # number of memory reference insts executed +system.cpu.iew.exec_branches 67045865 # Number of branches executed +system.cpu.iew.exec_stores 40881253 # Number of stores executed +system.cpu.iew.exec_rate 2.225011 # Inst execution rate +system.cpu.iew.wb_sent 600209978 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 598946660 # cumulative count of insts written-back +system.cpu.iew.wb_producers 417271834 # num instructions producing a value +system.cpu.iew.wb_consumers 532298467 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.210136 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.783974 # average fanout of values written-back +system.cpu.iew.wb_rate 2.210603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.783906 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69254422 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69202424 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3048560 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 260980429 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.306138 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692981 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3044252 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 260921762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.306657 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.693748 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 82002311 31.42% 31.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72802901 27.90% 59.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 26180796 10.03% 69.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8233037 3.15% 72.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10839669 4.15% 76.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 20863917 7.99% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6243794 2.39% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3659698 1.40% 88.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30154306 11.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 81870366 31.38% 31.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72918515 27.95% 59.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 26232772 10.05% 69.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8204750 3.14% 72.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10788682 4.13% 76.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20849092 7.99% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6203888 2.38% 87.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3594438 1.38% 88.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30259259 11.60% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 260980429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 260921762 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 30154306 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 30259259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 901873119 # The number of ROB reads -system.cpu.rob.rob_writes 1352238413 # The number of ROB writes -system.cpu.timesIdled 924 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 901657501 # The number of ROB reads +system.cpu.rob.rob_writes 1352126118 # The number of ROB writes +system.cpu.timesIdled 919 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36071 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.479194 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.479194 # CPI: Total CPI of All Threads -system.cpu.ipc 2.086837 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.086837 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 848955638 # number of integer regfile reads -system.cpu.int_regfile_writes 492807399 # number of integer regfile writes -system.cpu.fp_regfile_reads 373 # number of floating regfile reads +system.cpu.cpi 0.479076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.479076 # CPI: Total CPI of All Threads +system.cpu.ipc 2.087351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.087351 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 848921354 # number of integer regfile reads +system.cpu.int_regfile_writes 492788777 # number of integer regfile writes +system.cpu.fp_regfile_reads 376 # number of floating regfile reads system.cpu.fp_regfile_writes 51 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 45 # number of replacements -system.cpu.icache.tagsinuse 834.184340 # Cycle average of tags in use -system.cpu.icache.total_refs 66652701 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 988 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67462.247976 # Average number of references to valid blocks. +system.cpu.icache.replacements 46 # number of replacements +system.cpu.icache.tagsinuse 834.348638 # Cycle average of tags in use +system.cpu.icache.total_refs 66628172 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67301.183838 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 834.184340 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.407317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.407317 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 66652701 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 66652701 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 66652701 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 66652701 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 66652701 # number of overall hits -system.cpu.icache.overall_hits::total 66652701 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1424 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1424 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1424 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1424 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1424 # number of overall misses -system.cpu.icache.overall_misses::total 1424 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 52187000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 52187000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 52187000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 52187000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 52187000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 52187000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66654125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66654125 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66654125 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66654125 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66654125 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66654125 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 834.348638 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.407397 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.407397 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 66628172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 66628172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 66628172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 66628172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 66628172 # number of overall hits +system.cpu.icache.overall_hits::total 66628172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1417 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1417 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1417 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1417 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1417 # number of overall misses +system.cpu.icache.overall_misses::total 1417 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51973000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51973000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51973000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51973000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51973000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51973000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66629589 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66629589 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66629589 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66629589 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66629589 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66629589 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36648.174157 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36648.174157 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36648.174157 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36648.174157 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36648.174157 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36678.193366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36678.193366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36678.193366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36678.193366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36678.193366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,296 +388,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 436 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 436 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 436 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 436 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 436 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 436 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 988 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 988 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 988 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 988 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 988 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37189000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37189000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37189000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37189000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 427 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 427 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 427 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 427 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 427 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 427 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37151000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37151000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37151000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37151000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37640.688259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37640.688259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37640.688259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37640.688259 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37526.262626 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37526.262626 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37526.262626 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37526.262626 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460628 # number of replacements -system.cpu.dcache.tagsinuse 4093.382195 # Cycle average of tags in use -system.cpu.dcache.total_refs 148766128 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464724 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 320.117162 # Average number of references to valid blocks. +system.cpu.dcache.replacements 460520 # number of replacements +system.cpu.dcache.tagsinuse 4093.381550 # Cycle average of tags in use +system.cpu.dcache.total_refs 148763474 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464616 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 320.185861 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 141133000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.382195 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4093.381550 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999361 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999361 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 111085210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 111085210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37680869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37680869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 148766079 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 148766079 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 148766079 # number of overall hits -system.cpu.dcache.overall_hits::total 148766079 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 577881 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 577881 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1770452 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1770452 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2348333 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2348333 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2348333 # number of overall misses -system.cpu.dcache.overall_misses::total 2348333 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8220967500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8220967500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 45275400067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45275400067 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 31000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 31000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53496367567 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53496367567 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53496367567 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53496367567 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 111663091 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 111663091 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 111082723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 111082723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37680696 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37680696 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 55 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 55 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 148763419 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 148763419 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 148763419 # number of overall hits +system.cpu.dcache.overall_hits::total 148763419 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 577759 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 577759 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1770625 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1770625 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2348384 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2348384 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2348384 # number of overall misses +system.cpu.dcache.overall_misses::total 2348384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8217146500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8217146500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45283421033 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45283421033 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 15500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 15500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53500567533 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53500567533 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53500567533 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53500567533 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 111660482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 111660482 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 51 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 151114412 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 151114412 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 151114412 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 151114412 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005175 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005175 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.044877 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.039216 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.039216 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015540 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015540 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015540 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015540 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14226.056057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14226.056057 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25572.791619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25572.791619 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151111803 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151111803 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151111803 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151111803 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005174 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005174 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.044881 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.044881 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017857 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015541 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015541 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015541 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015541 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14222.446556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14222.446556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25574.823033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25574.823033 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22780.571396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22780.571396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22780.571396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 267496 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22781.865118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22781.865118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22781.865118 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 260996 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 204500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 99 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2286.290598 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2636.323232 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20450 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444923 # number of writebacks -system.cpu.dcache.writebacks::total 444923 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367661 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 367661 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1515948 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1515948 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1883609 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1883609 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1883609 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1883609 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210220 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254504 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254504 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464724 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464724 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1663922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1663922500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5123963342 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5123963342 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6787885842 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6787885842 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6787885842 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6787885842 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001883 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001883 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 444797 # number of writebacks +system.cpu.dcache.writebacks::total 444797 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 367652 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 367652 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1516116 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1516116 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1883768 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1883768 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1883768 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1883768 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210107 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210107 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254509 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254509 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1661680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1661680500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5124983839 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5124983839 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6786664339 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6786664339 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6786664339 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6786664339 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001882 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001882 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003075 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003075 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003075 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7915.148416 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7915.148416 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20133.134811 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20133.134811 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14606.273491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14606.273491 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7908.734597 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7908.734597 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20136.748952 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20136.748952 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14607.039661 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14607.039661 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14607.039661 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 949 # number of replacements -system.cpu.l2cache.tagsinuse 22947.355822 # Cycle average of tags in use -system.cpu.l2cache.total_refs 555465 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23383 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.755078 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 950 # number of replacements +system.cpu.l2cache.tagsinuse 22952.523790 # Cycle average of tags in use +system.cpu.l2cache.total_refs 555154 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23388 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.736703 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21503.111139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 828.347740 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 615.896944 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.656223 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.025279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.018796 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.700298 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21504.844350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 828.512552 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 619.166888 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.656276 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.025284 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.018895 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.700455 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 205921 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 205944 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 444923 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 444923 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 233378 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 373e7efc5..c74978b2c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164812 # Number of seconds simulated -sim_ticks 164812294500 # Number of ticks simulated -final_tick 164812294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164804 # Number of seconds simulated +sim_ticks 164803697500 # Number of ticks simulated +final_tick 164803697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186522 # Simulator instruction rate (inst/s) -host_op_rate 197094 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53926880 # Simulator tick rate (ticks/s) -host_mem_usage 234728 # Number of bytes of host memory used -host_seconds 3056.22 # Real time elapsed on the host -sim_insts 570052720 # Number of instructions simulated -sim_ops 602360926 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1770688 # Number of bytes read from this memory -system.physmem.bytes_read::total 1818880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 203712 # Number of bytes written to this memory -system.physmem.bytes_written::total 203712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 753 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27667 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28420 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3183 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3183 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 292405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10743665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11036070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 292405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 292405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1236024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1236024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1236024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 292405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10743665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12272094 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 225505 # Simulator instruction rate (inst/s) +host_op_rate 238286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65194032 # Simulator tick rate (ticks/s) +host_mem_usage 234780 # Number of bytes of host memory used +host_seconds 2527.90 # Real time elapsed on the host +sim_insts 570052730 # Number of instructions simulated +sim_ops 602360936 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1769280 # Number of bytes read from this memory +system.physmem.bytes_read::total 1816896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 202944 # Number of bytes written to this memory +system.physmem.bytes_written::total 202944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27645 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28389 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3171 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3171 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 288926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10735681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11024607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 288926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 288926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1231429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1231429 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1231429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 288926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10735681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12256036 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,106 +77,106 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329624590 # number of cpu cycles simulated +system.cpu.numCycles 329607396 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85521151 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80320824 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2362426 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47149352 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46837857 # Number of BTB hits +system.cpu.BPredUnit.lookups 85521262 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80324005 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2361364 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47163773 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46836425 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1443093 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 967 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68941793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669884423 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85521151 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48280950 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130081078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13500418 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119459363 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1442496 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 971 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68931742 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669855776 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85521262 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48278921 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130072968 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13495551 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119465420 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67507706 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 807322 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329533342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166395 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195647 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 697 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67497575 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 806206 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329517095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195660 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199452502 60.53% 60.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20948711 6.36% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4950582 1.50% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14318865 4.35% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8979173 2.72% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9434613 2.86% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4385548 1.33% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5816824 1.77% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61246524 18.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199444353 60.53% 60.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20947099 6.36% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4950101 1.50% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14318334 4.35% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8976585 2.72% 75.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9434873 2.86% 78.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4385962 1.33% 79.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5814434 1.76% 81.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61245354 18.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329533342 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259450 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032265 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93614628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96158900 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108189069 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20521940 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11048805 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4786965 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706200361 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6232 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11048805 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107837275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14152380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114426981 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82018229 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697376779 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 154 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59681814 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20119568 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723981883 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3242139777 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3242139649 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 329517095 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259464 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032284 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93615293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96153951 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108189677 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20513543 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11044631 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4783839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1715 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 706162861 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6102 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11044631 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107837587 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14124315 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49845 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114419609 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82041108 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697343102 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59702950 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20121716 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723953896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241969745 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241969617 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419189 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96562694 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6452 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6400 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169999822 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172950765 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80642212 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21622434 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28168591 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682111188 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4787 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646911424 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1425738 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79572817 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198257861 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1856 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329533342 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.727328 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419205 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96534691 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6461 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6411 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169960309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172942863 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80636505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21738448 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28392401 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 682081084 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4755 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646873471 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1427255 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79546312 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198336630 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1822 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329517095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726025 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69109124 20.97% 20.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85502964 25.95% 46.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75902592 23.03% 69.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 41003361 12.44% 82.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28586147 8.67% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15096087 4.58% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5691070 1.73% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6514226 1.98% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2127771 0.65% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69073062 20.96% 20.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85428169 25.93% 46.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76011979 23.07% 69.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40983157 12.44% 82.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28619491 8.69% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15088313 4.58% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5676552 1.72% 97.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6597944 2.00% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2038428 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329533342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329517095 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205938 5.35% 5.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 205689 5.35% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.35% # attempts to use FU when none available @@ -205,13 +205,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.35% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.35% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2629007 68.31% 73.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1013747 26.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2625601 68.27% 73.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1014507 26.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403964135 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6565 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403948716 62.45% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166144548 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76796173 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166134463 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76783723 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646911424 # Type of FU issued -system.cpu.iq.rate 1.962570 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3848692 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628630584 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761700595 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638589501 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646873471 # Type of FU issued +system.cpu.iq.rate 1.962558 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3845797 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005945 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628537053 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761643882 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638542497 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650760096 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650719248 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30444381 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30433842 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23997945 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 128330 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12058 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10420972 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23990041 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 126515 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11992 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10415263 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12743 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 33964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12768 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35443 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11048805 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 670880 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80193 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682182162 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 671811 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172950765 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80642212 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21821 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3936 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12058 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2895790 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642749974 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 164016211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4161450 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11044631 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 670742 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80165 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 682151912 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 669326 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172942863 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80636505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21938 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3947 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11992 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1313002 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1582154 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2895156 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642705109 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 164002272 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4168362 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66187 # number of nop insts executed -system.cpu.iew.exec_refs 240022824 # number of memory reference insts executed -system.cpu.iew.exec_branches 74673150 # Number of branches executed -system.cpu.iew.exec_stores 76006613 # Number of stores executed -system.cpu.iew.exec_rate 1.949945 # Inst execution rate -system.cpu.iew.wb_sent 640083965 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638589517 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419034564 # num instructions producing a value -system.cpu.iew.wb_consumers 650591569 # num instructions consuming a value +system.cpu.iew.exec_nop 66073 # number of nop insts executed +system.cpu.iew.exec_refs 239994615 # number of memory reference insts executed +system.cpu.iew.exec_branches 74670654 # Number of branches executed +system.cpu.iew.exec_stores 75992343 # Number of stores executed +system.cpu.iew.exec_rate 1.949911 # Inst execution rate +system.cpu.iew.wb_sent 640039570 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638542513 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419139421 # num instructions producing a value +system.cpu.iew.wb_consumers 650719166 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937324 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644082 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937282 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644117 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79830456 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2931 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2422889 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318484538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891335 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233401 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79800581 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2933 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2421751 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318472465 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.891407 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233429 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93876011 29.48% 29.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104566020 32.83% 62.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43293403 13.59% 75.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8795442 2.76% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26035150 8.17% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12750697 4.00% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7572699 2.38% 93.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1269382 0.40% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20325734 6.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93877002 29.48% 29.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104551194 32.83% 62.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43288621 13.59% 75.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8793504 2.76% 78.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26039044 8.18% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12759663 4.01% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7570973 2.38% 93.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1268002 0.40% 93.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20324462 6.38% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318484538 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052771 # Number of instructions committed -system.cpu.commit.committedOps 602360977 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318472465 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052781 # Number of instructions committed +system.cpu.commit.committedOps 602360987 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174060 # Number of memory references committed -system.cpu.commit.loads 148952820 # Number of loads committed +system.cpu.commit.refs 219174064 # Number of memory references committed +system.cpu.commit.loads 148952822 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828827 # Number of branches committed +system.cpu.commit.branches 70828829 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523539 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20325734 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20324462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980349625 # The number of ROB reads -system.cpu.rob.rob_writes 1375464218 # The number of ROB writes -system.cpu.timesIdled 6594 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 91248 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052720 # Number of Instructions Simulated -system.cpu.committedOps 602360926 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052720 # Number of Instructions Simulated -system.cpu.cpi 0.578235 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.578235 # CPI: Total CPI of All Threads -system.cpu.ipc 1.729400 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.729400 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210711882 # number of integer regfile reads -system.cpu.int_regfile_writes 664273083 # number of integer regfile writes +system.cpu.rob.rob_reads 980308959 # The number of ROB reads +system.cpu.rob.rob_writes 1375400190 # The number of ROB writes +system.cpu.timesIdled 6717 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90301 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052730 # Number of Instructions Simulated +system.cpu.committedOps 602360936 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052730 # Number of Instructions Simulated +system.cpu.cpi 0.578205 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.578205 # CPI: Total CPI of All Threads +system.cpu.ipc 1.729490 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.729490 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210477235 # number of integer regfile reads +system.cpu.int_regfile_writes 664240650 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905231466 # number of misc regfile reads -system.cpu.misc_regfile_writes 3110 # number of misc regfile writes -system.cpu.icache.replacements 57 # number of replacements -system.cpu.icache.tagsinuse 692.699547 # Cycle average of tags in use -system.cpu.icache.total_refs 67506606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 819 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 82425.648352 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 905174301 # number of misc regfile reads +system.cpu.misc_regfile_writes 3114 # number of misc regfile writes +system.cpu.icache.replacements 52 # number of replacements +system.cpu.icache.tagsinuse 687.184912 # Cycle average of tags in use +system.cpu.icache.total_refs 67496491 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 806 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 83742.544665 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 692.699547 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.338232 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.338232 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67506606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67506606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67506606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67506606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67506606 # number of overall hits -system.cpu.icache.overall_hits::total 67506606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1100 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1100 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1100 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1100 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1100 # number of overall misses -system.cpu.icache.overall_misses::total 1100 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38665000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38665000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38665000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38665000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38665000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38665000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67507706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67507706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67507706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67507706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67507706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67507706 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 687.184912 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.335540 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.335540 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67496491 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67496491 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67496491 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67496491 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67496491 # number of overall hits +system.cpu.icache.overall_hits::total 67496491 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1084 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1084 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1084 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1084 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1084 # number of overall misses +system.cpu.icache.overall_misses::total 1084 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38240500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38240500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38240500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38240500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38240500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38240500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67497575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67497575 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67497575 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67497575 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67497575 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67497575 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35150 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35150 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35150 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35150 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35150 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35277.214022 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35277.214022 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35277.214022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35277.214022 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,146 +398,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 281 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 281 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 281 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 281 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 281 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28673500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28673500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28673500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28673500 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 806 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 806 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28447000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28447000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28447000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28447000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28447000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28447000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40398908535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40398908535 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 237000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44092364035 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44092364035 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44092364035 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44092364035 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 132307849 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 132307849 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2863199 # 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number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036878 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036878 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014185 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014185 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014185 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014185 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12252.420824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12252.420824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15781.014745 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 15781.014745 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 11285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 11285.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15409.281291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15409.281291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15409.281291 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30249535 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036905 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.036905 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012331 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.012331 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014194 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014194 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014194 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014194 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12258.808478 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12258.808478 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15792.333580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15792.333580 # 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number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9966.897858 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10475.010359 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420982 # number of writebacks -system.cpu.dcache.writebacks::total 420982 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104126 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2312844 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2312844 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 420959 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4299529629 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4299529629 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001491 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001491 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003560 # mshr miss rate for WriteReq accesses @@ -546,161 +546,161 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002203 system.cpu.dcache.demand_mshr_miss_rate::total 0.002203 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002203 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002203 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7834.229504 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7834.229504 # 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number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 22177 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 27667 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 28420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 27667 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 28420 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24642000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 175481000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200123000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 812123285 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 812123285 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 987604285 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1012246285 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 987604285 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1012246285 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027823 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031509 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089738 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089738 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063827 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919414 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062251 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063827 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32725.099602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31963.752277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32055.582252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36620.069667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36620.069667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32725.099602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35696.110348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35617.392153 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5477 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6221 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22168 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22168 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27645 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27645 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28389 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24393000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 175108500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199501500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 838007785 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 838007785 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24393000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1013116285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1037509285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24393000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1013116285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1037509285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027765 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089705 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063768 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063768 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32786.290323 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31971.608545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32069.040347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37802.588641 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37802.588641 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index 009981c70..c0dac2931 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.389171 # Number of seconds simulated -sim_ticks 389171398000 # Number of ticks simulated -final_tick 389171398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 389171400000 # Number of ticks simulated +final_tick 389171400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172352 # Simulator instruction rate (inst/s) -host_op_rate 172895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47869738 # Simulator tick rate (ticks/s) -host_mem_usage 232600 # Number of bytes of host memory used -host_seconds 8129.80 # Real time elapsed on the host +host_inst_rate 248197 # Simulator instruction rate (inst/s) +host_op_rate 248980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68935275 # Simulator tick rate (ticks/s) +host_mem_usage 223264 # Number of bytes of host memory used +host_seconds 5645.46 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 78528 # Number of bytes read from this memory @@ -35,7 +35,7 @@ system.physmem.bw_total::cpu.inst 201783 # To system.physmem.bw_total::cpu.data 4314891 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4936519 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 778342797 # number of cpu cycles simulated +system.cpu.numCycles 778342801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 98197174 # Number of BP lookups @@ -52,16 +52,16 @@ system.cpu.fetch.Branches 98197174 # Nu system.cpu.fetch.predictedBranches 65666167 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 330411204 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 21674066 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 264316799 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 264316803 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 122 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2684 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 162819499 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 755607 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 778298468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.124294 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.146110 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 447887260 57.55% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 447887264 57.55% 57.55% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 74376407 9.56% 67.10% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 37977630 4.88% 71.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 9084449 1.17% 73.15% # Number of instructions fetched each cycle (Total) @@ -73,24 +73,24 @@ system.cpu.fetch.rateDist::8 146598890 18.84% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 778298464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 778298468 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.126162 # Number of branch fetches per cycle system.cpu.fetch.rate 2.118344 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 217730423 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214714894 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 285147826 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 43019383 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 217730424 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214714897 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 285147825 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 43019384 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 17685938 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 1642518992 # Number of instructions handled by decode system.cpu.rename.SquashCycles 17685938 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 241679768 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 241679770 # Number of cycles rename is idle system.cpu.rename.BlockCycles 36912628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 51960575 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 51960576 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 303022356 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 127037199 # Number of cycles rename is unblocking +system.cpu.rename.UnblockCycles 127037200 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 1631180439 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 31545211 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73402474 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 73402475 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 3147906 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 1360824399 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 2755700072 # Number of register rename lookups that rename has made @@ -104,7 +104,7 @@ system.cpu.rename.skidInsts 273063750 # co system.cpu.memDep0.insertedLoads 438707438 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 180249753 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 255184370 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 82754828 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 82754827 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 1516941659 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2635026 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 1460769058 # Number of instructions issued @@ -112,23 +112,23 @@ system.cpu.iq.iqSquashedInstsIssued 54636 # Nu system.cpu.iq.iqSquashedInstsExamined 113641063 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 136677185 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 391355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 778298468 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.876875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.427909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147064057 18.90% 18.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 186545297 23.97% 42.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 210910023 27.10% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 147064058 18.90% 18.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 186545303 23.97% 42.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 210910021 27.10% 69.96% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 130868567 16.81% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70782480 9.09% 95.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70782478 9.09% 95.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 20278912 2.61% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 7762488 1.00% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 7762489 1.00% 99.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 3994514 0.51% 99.99% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 92126 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 778298464 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 778298468 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 113664 7.00% 7.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 7.00% # attempts to use FU when none available @@ -159,7 +159,7 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 17.26% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 17.26% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.26% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 17.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1139490 70.19% 87.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1139492 70.19% 87.45% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 203791 12.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available @@ -199,15 +199,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 1460769058 # Type of FU issued system.cpu.iq.rate 1.876768 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1623524 # FU busy when requested +system.cpu.iq.fu_busy_cnt 1623526 # FU busy when requested system.cpu.iq.fu_busy_rate 0.001111 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3683829696 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 3683829702 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 1624339460 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1444358901 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 17685044 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 9115270 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 8537907 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1453371390 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1453371392 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 9021192 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 215484580 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -245,8 +245,8 @@ system.cpu.iew.exec_stores 170572268 # Nu system.cpu.iew.exec_rate 1.869642 # Inst execution rate system.cpu.iew.wb_sent 1453822475 # cumulative count of insts sent to commit system.cpu.iew.wb_count 1452896808 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1154316777 # num instructions producing a value -system.cpu.iew.wb_consumers 1205166277 # num instructions consuming a value +system.cpu.iew.wb_producers 1154316776 # num instructions producing a value +system.cpu.iew.wb_consumers 1205166275 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.866654 # insts written-back per cycle system.cpu.iew.wb_fanout 0.957807 # average fanout of values written-back @@ -254,23 +254,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 124161815 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 3785239 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 760613141 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.958319 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.503249 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 241688690 31.78% 31.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 276879553 36.40% 68.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43195227 5.68% 73.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 276879555 36.40% 68.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43195229 5.68% 73.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 54904670 7.22% 81.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19686775 2.59% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13341138 1.75% 85.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19686776 2.59% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13341139 1.75% 85.42% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 30448610 4.00% 89.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10352977 1.36% 90.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70115497 9.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10352976 1.36% 90.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70115496 9.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 760613137 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 760613141 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -281,9 +281,9 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70115497 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70115496 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2304117867 # The number of ROB reads +system.cpu.rob.rob_reads 2304117872 # The number of ROB reads system.cpu.rob.rob_writes 3245080355 # The number of ROB writes system.cpu.timesIdled 1467 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 44333 # Total number of cycles that the CPU has spent unscheduled due to idling @@ -415,14 +415,14 @@ system.cpu.dcache.overall_misses::cpu.data 2771932 # system.cpu.dcache.overall_misses::total 2771932 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 11940266500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 11940266500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531206941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57531206941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57531211441 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57531211441 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 69000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 69000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 69471473441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 69471473441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 69471473441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 69471473441 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 69471477941 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 69471477941 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 69471477941 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 69471477941 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 201522884 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 201522884 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) @@ -445,14 +445,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.007525 system.cpu.dcache.overall_miss_rate::total 0.007525 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.527361 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.527361 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 9857.142857 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 9857.142857 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25062.473914 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25062.473914 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25062.475537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.475537 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25062.475537 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 4500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -483,14 +483,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 461980 system.cpu.dcache.overall_mshr_misses::total 461980 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 927311500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 927311500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914389505 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914389505 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5914391005 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5914391005 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 47000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 47000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841701005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6841701005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841701005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6841701005 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6841702505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6841702505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6841702505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6841702505 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000992 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001570 # mshr miss rate for WriteReq accesses @@ -503,24 +503,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001254 system.cpu.dcache.overall_mshr_miss_rate::total 0.001254 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 4637.577767 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 4637.577767 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.943810 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.943810 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 6714.285714 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 6714.285714 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.517739 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.517739 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.520986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.520986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2682 # number of replacements -system.cpu.l2cache.tagsinuse 22381.194058 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22381.194051 # Cycle average of tags in use system.cpu.l2cache.total_refs 541474 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 24308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.275547 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20744.863113 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 994.979192 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 641.351753 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 20744.863109 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 994.979191 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 641.351751 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.633083 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.030364 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.019573 # Average percentage of cache occupancy @@ -552,14 +552,14 @@ system.cpu.l2cache.overall_misses::total 27465 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42694000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 151831500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 194525500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842839500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 842839500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 842840000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 842840000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 42694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 994671000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1037365000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 994671500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1037365500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 42694000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 994671000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1037365000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 994671500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1037365500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1363 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 199948 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 201311 # number of ReadReq accesses(hits+misses) @@ -587,14 +587,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.059275 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.065541 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.065541 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37770.453304 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.577712 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37770.453304 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 64232919f..516126aba 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.064346 # Number of seconds simulated -sim_ticks 64346039000 # Number of ticks simulated -final_tick 64346039000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 64346040000 # Number of ticks simulated +final_tick 64346040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77016 # Simulator instruction rate (inst/s) -host_op_rate 135613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31367260 # Simulator tick rate (ticks/s) -host_mem_usage 410996 # Number of bytes of host memory used -host_seconds 2051.38 # Real time elapsed on the host +host_inst_rate 132449 # Simulator instruction rate (inst/s) +host_op_rate 233222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53944275 # Simulator tick rate (ticks/s) +host_mem_usage 365660 # Number of bytes of host memory used +host_seconds 1192.82 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192462 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 68352 # Number of bytes read from this memory @@ -24,7 +24,7 @@ system.physmem.num_reads::total 30652 # Nu system.physmem.num_writes::writebacks 319 # Number of write requests responded to by this memory system.physmem.num_writes::total 319 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 1062257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 29424904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 29424903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 30487160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1062257 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1062257 # Instruction read bandwidth from this memory (bytes/s) @@ -32,10 +32,10 @@ system.physmem.bw_write::writebacks 317284 # Wr system.physmem.bw_write::total 317284 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 317284 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1062257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 29424904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30804445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 29424903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30804444 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 128692079 # number of cpu cycles simulated +system.cpu.numCycles 128692081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 35576702 # Number of BP lookups @@ -287,7 +287,7 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 426345169 # The number of ROB reads system.cpu.rob.rob_writes 653150724 # The number of ROB writes system.cpu.timesIdled 2141 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33722 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33724 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192462 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated @@ -301,12 +301,12 @@ system.cpu.fp_regfile_reads 165 # nu system.cpu.fp_regfile_writes 88 # number of floating regfile writes system.cpu.misc_regfile_reads 195572528 # number of misc regfile reads system.cpu.icache.replacements 92 # number of replacements -system.cpu.icache.tagsinuse 843.498154 # Cycle average of tags in use +system.cpu.icache.tagsinuse 843.498155 # Cycle average of tags in use system.cpu.icache.total_refs 27158781 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 1076 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 25240.502788 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 843.498154 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 843.498155 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.411864 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.411864 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 27158782 # number of ReadReq hits @@ -321,12 +321,12 @@ system.cpu.icache.demand_misses::cpu.inst 1385 # n system.cpu.icache.demand_misses::total 1385 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1385 # number of overall misses system.cpu.icache.overall_misses::total 1385 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51448500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 51455500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 51455500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 51455500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 51455500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 51455500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 51455500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 27160167 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 27160167 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 27160167 # number of demand (read+write) accesses @@ -339,12 +339,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37146.931408 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37146.931408 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37146.931408 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37146.931408 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37146.931408 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37151.985560 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37151.985560 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37151.985560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37151.985560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37151.985560 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,24 +365,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1078 system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39433000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39433000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39433000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39438000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39438000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000040 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000040 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36579.777365 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36579.777365 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36579.777365 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36579.777365 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36584.415584 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36584.415584 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36584.415584 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36584.415584 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2072148 # number of replacements system.cpu.dcache.tagsinuse 4072.029897 # Cycle average of tags in use @@ -493,14 +493,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 4704.008866 system.cpu.dcache.overall_avg_mshr_miss_latency::total 4704.008866 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1466 # number of replacements -system.cpu.l2cache.tagsinuse 19909.538266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 19909.538394 # Cycle average of tags in use system.cpu.l2cache.total_refs 4027133 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 30632 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 131.468171 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 19409.012511 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 268.281429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 232.244325 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 19409.012644 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 268.281425 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 232.244324 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.592316 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.008187 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.007088 # Average percentage of cache occupancy @@ -533,17 +533,17 @@ system.cpu.l2cache.demand_misses::total 30652 # nu system.cpu.l2cache.overall_misses::cpu.inst 1068 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29584 # number of overall misses system.cpu.l2cache.overall_misses::total 30652 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37875000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37880000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20966500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 58841500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 58846500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 988882500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 988882500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 37875000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37880000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 1009849000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1047724000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 37875000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 1047729000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37880000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 1009849000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1047724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1047729000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1994091 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1995167 # number of ReadReq accesses(hits+misses) @@ -572,17 +572,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014756 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992565 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014249 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014756 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35463.483146 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35468.164794 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35657.312925 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35532.306763 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35535.326087 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34104.100566 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34104.100566 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34181.260603 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35463.483146 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34181.423724 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35468.164794 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.971606 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34181.260603 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34181.423724 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,19 +606,19 @@ system.cpu.l2cache.demand_mshr_misses::total 30652 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1068 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29584 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30652 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34493000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53606000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19113500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53612000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899198000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899198000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34493000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 952804000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34493000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 952804000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 918311500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 952810000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 918311500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 952810000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000295 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000830 # mshr miss rate for ReadReq accesses @@ -632,19 +632,19 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014756 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992565 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014249 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014756 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32296.816479 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.102041 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32370.772947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32301.966292 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32505.952381 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32374.396135 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31011.104980 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31011.104980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32296.816479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.799081 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.562182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32301.966292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31040.815982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31084.757928 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index fb71d744c..c461f7be8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.213306 # Number of seconds simulated -sim_ticks 213305827500 # Number of ticks simulated -final_tick 213305827500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.213288 # Number of seconds simulated +sim_ticks 213288042000 # Number of ticks simulated +final_tick 213288042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122434 # Simulator instruction rate (inst/s) -host_op_rate 137922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51312604 # Simulator tick rate (ticks/s) -host_mem_usage 243816 # Number of bytes of host memory used -host_seconds 4156.99 # Real time elapsed on the host +host_inst_rate 175103 # Simulator instruction rate (inst/s) +host_op_rate 197255 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73380577 # Simulator tick rate (ticks/s) +host_mem_usage 239036 # Number of bytes of host memory used +host_seconds 2906.60 # Real time elapsed on the host sim_insts 508955143 # Number of instructions simulated sim_ops 573341703 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10018112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10236992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6680832 # Number of bytes written to this memory -system.physmem.bytes_written::total 6680832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 159953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104388 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104388 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1026132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46965955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47992088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1026132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1026132 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31320438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31320438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31320438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1026132 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46965955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79312526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 218176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10017792 # Number of bytes read from this memory +system.physmem.bytes_read::total 10235968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6680384 # Number of bytes written to this memory +system.physmem.bytes_written::total 6680384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3409 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156528 # Number of read requests responded to by this memory +system.physmem.num_reads::total 159937 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104381 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104381 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1022917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46968372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47991289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1022917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1022917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31320950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31320950 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31320950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1022917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46968372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 79312238 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 426611656 # number of cpu cycles simulated +system.cpu.numCycles 426576085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 180727823 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 143302439 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7746795 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 94842136 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 87606401 # Number of BTB hits +system.cpu.BPredUnit.lookups 180740413 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 143314852 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7747678 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 94843879 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 87610894 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12449624 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 117248 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 121010673 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 797304667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 180727823 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 100056025 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 177314401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 41698826 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 95806477 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 633 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 114358410 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2503764 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 425037502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.155810 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.022430 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12444215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 117322 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 121008241 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 797329554 # Number of instructions fetch has processed +system.cpu.fetch.Branches 180740413 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 100055109 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 177305493 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 41694280 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 95788373 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 733 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 114354334 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2502299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 425002999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.155911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.022478 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 247735901 58.29% 58.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14398989 3.39% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 20690991 4.87% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22948184 5.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21028166 4.95% 76.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13190111 3.10% 79.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13289231 3.13% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12171348 2.86% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59584581 14.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 247710334 58.28% 58.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14399236 3.39% 61.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 20683472 4.87% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22949546 5.40% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21027590 4.95% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13189722 3.10% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13290408 3.13% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12169042 2.86% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 59583649 14.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 425037502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.423635 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.868924 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 133844968 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89919956 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165224759 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5218013 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 30829806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26552808 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78494 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 873544954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311862 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 30829806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 144308291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8889002 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66226963 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159805436 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14978004 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 818752285 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2838539 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8233022 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 166 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 966651195 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3575004515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3574999805 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4710 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 425002999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.423700 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.869138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 133837358 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 89905115 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 165211809 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5224015 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 30824702 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26552626 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78407 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 873532911 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312665 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 30824702 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 144300164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8880120 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 66226908 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 159798205 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14972900 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 818719964 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1527 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2831804 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8232958 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 169 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 966624126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3574819006 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3574814464 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4542 # Number of floating rename lookups system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 294451032 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5324262 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5323899 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 70506892 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172716678 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75192368 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27652992 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15476560 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 763674623 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6775753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 672581286 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1543643 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 194823037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 494499430 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3054637 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 425037502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.582405 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.714766 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 294423963 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5324035 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5323684 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 70502461 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172694215 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75173419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27528293 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15558221 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 763633649 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6775757 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 672560408 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1538791 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 194774219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 494406883 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3054641 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 425002999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.582484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.714723 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 161217436 37.93% 37.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 79193919 18.63% 56.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71219740 16.76% 73.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 52703176 12.40% 85.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30630317 7.21% 92.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16016984 3.77% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9411904 2.21% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3391461 0.80% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1252565 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 161186473 37.93% 37.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 79207972 18.64% 56.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71181654 16.75% 73.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 52720158 12.40% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 30652473 7.21% 92.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16004592 3.77% 96.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9408207 2.21% 98.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3385200 0.80% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1256270 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 425037502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 425002999 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 468985 4.81% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6682386 68.55% 73.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2596899 26.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 468819 4.82% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6672896 68.60% 73.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2585103 26.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451788730 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 385834 0.06% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 451779647 67.17% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 385833 0.06% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 242 0.00% 67.23% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 224 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued @@ -239,84 +239,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155276883 23.09% 90.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65129594 9.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155287999 23.09% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65106702 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 672581286 # Type of FU issued -system.cpu.iq.rate 1.576566 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9748270 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014494 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1781491468 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 966076983 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 652193699 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 519 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 994 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 672560408 # Type of FU issued +system.cpu.iq.rate 1.576648 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9726818 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014462 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1781388941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 965987028 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 652168068 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 483 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 954 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 682329295 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 261 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8459367 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 682286983 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8456716 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 45943639 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43480 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 808541 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17588407 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 45921176 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 43296 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 808281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17569458 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19485 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1190 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19481 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1162 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 30829806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4164559 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 269371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 776620659 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1214502 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172716678 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75192368 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5287034 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 138183 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8014 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 808541 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4710218 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6437306 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11147524 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 662618807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151738432 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9962479 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 30824702 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4157242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 268994 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 776579176 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1213475 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172694215 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75173419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5287043 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 138286 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7916 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 808281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4709079 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6438741 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11147820 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 662598495 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 151749553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9961913 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 6170283 # number of nop insts executed -system.cpu.iew.exec_refs 215459970 # number of memory reference insts executed -system.cpu.iew.exec_branches 137327241 # Number of branches executed -system.cpu.iew.exec_stores 63721538 # Number of stores executed -system.cpu.iew.exec_rate 1.553213 # Inst execution rate -system.cpu.iew.wb_sent 657384625 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 652193715 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375712620 # num instructions producing a value -system.cpu.iew.wb_consumers 644546393 # num instructions consuming a value +system.cpu.iew.exec_nop 6169770 # number of nop insts executed +system.cpu.iew.exec_refs 215449893 # number of memory reference insts executed +system.cpu.iew.exec_branches 137324622 # Number of branches executed +system.cpu.iew.exec_stores 63700340 # Number of stores executed +system.cpu.iew.exec_rate 1.553295 # Inst execution rate +system.cpu.iew.wb_sent 657360539 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 652168084 # cumulative count of insts written-back +system.cpu.iew.wb_producers 375706484 # num instructions producing a value +system.cpu.iew.wb_consumers 644527400 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.528776 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.582910 # average fanout of values written-back +system.cpu.iew.wb_rate 1.528844 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.582918 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 201955385 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 201913792 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9921280 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 394207697 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.457824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.150931 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9922149 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 394178298 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.457933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.151181 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 179674322 45.58% 45.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103038794 26.14% 71.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36295508 9.21% 80.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18900800 4.79% 85.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16480626 4.18% 89.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8181222 2.08% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6907237 1.75% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3752163 0.95% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20977025 5.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 179646663 45.57% 45.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103047571 26.14% 71.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 36291741 9.21% 80.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18910694 4.80% 85.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16473731 4.18% 89.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8163992 2.07% 91.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6899886 1.75% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3743908 0.95% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 21000112 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 394207697 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 394178298 # Number of insts commited each cycle system.cpu.commit.committedInsts 510299027 # Number of instructions committed system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,69 +327,69 @@ system.cpu.commit.branches 120192224 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 473701629 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20977025 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 21000112 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1149864506 # The number of ROB reads -system.cpu.rob.rob_writes 1584255068 # The number of ROB writes -system.cpu.timesIdled 77013 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1574154 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1149770427 # The number of ROB reads +system.cpu.rob.rob_writes 1584166126 # The number of ROB writes +system.cpu.timesIdled 75828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1573086 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 508955143 # Number of Instructions Simulated system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated -system.cpu.cpi 0.838211 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.838211 # CPI: Total CPI of All Threads -system.cpu.ipc 1.193017 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.193017 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3092210365 # number of integer regfile reads -system.cpu.int_regfile_writes 760501959 # number of integer regfile writes +system.cpu.cpi 0.838141 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.838141 # CPI: Total CPI of All Threads +system.cpu.ipc 1.193117 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.193117 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3092127855 # number of integer regfile reads +system.cpu.int_regfile_writes 760494999 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1025217817 # number of misc regfile reads +system.cpu.misc_regfile_reads 1025229715 # number of misc regfile reads system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes -system.cpu.icache.replacements 15942 # number of replacements -system.cpu.icache.tagsinuse 1098.022149 # Cycle average of tags in use -system.cpu.icache.total_refs 114338741 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6422.442341 # Average number of references to valid blocks. +system.cpu.icache.replacements 16005 # number of replacements +system.cpu.icache.tagsinuse 1098.211630 # Cycle average of tags in use +system.cpu.icache.total_refs 114334583 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17866 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6399.562465 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1098.022149 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.536144 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.536144 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114338741 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114338741 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114338741 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114338741 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114338741 # number of overall hits -system.cpu.icache.overall_hits::total 114338741 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19669 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19669 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19669 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19669 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19669 # number of overall misses -system.cpu.icache.overall_misses::total 19669 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 281943000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 281943000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 281943000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 281943000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 281943000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 281943000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114358410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114358410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114358410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114358410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114358410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114358410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000172 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000172 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000172 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000172 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000172 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000172 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14334.384056 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14334.384056 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14334.384056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14334.384056 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14334.384056 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1098.211630 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.536236 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.536236 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114334583 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114334583 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114334583 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114334583 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114334583 # number of overall hits +system.cpu.icache.overall_hits::total 114334583 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19751 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19751 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19751 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19751 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19751 # number of overall misses +system.cpu.icache.overall_misses::total 19751 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 282522500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 282522500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 282522500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 282522500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 282522500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 282522500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114354334 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114354334 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114354334 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114354334 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114354334 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114354334 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000173 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000173 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000173 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000173 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000173 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000173 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14304.212445 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14304.212445 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14304.212445 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14304.212445 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,254 +398,258 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1810 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1810 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1810 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1810 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1810 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1810 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17859 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17859 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17859 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17859 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17859 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184851000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 184851000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184851000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 184851000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184851000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 184851000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000156 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000156 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000156 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000156 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10350.579540 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10350.579540 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10350.579540 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10350.579540 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1832 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1832 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1832 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1832 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1832 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1832 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17919 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 17919 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 17919 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 17919 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 17919 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 17919 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184521500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 184521500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184521500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 184521500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184521500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 184521500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000157 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000157 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10297.533344 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10297.533344 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1188372 # number of replacements -system.cpu.dcache.tagsinuse 4054.528843 # Cycle average of tags in use -system.cpu.dcache.total_refs 194724251 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1192468 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.295158 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1188505 # number of replacements +system.cpu.dcache.tagsinuse 4054.525384 # Cycle average of tags in use +system.cpu.dcache.total_refs 194736963 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1192601 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.287607 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4858281000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.528843 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989875 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989875 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137575577 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137575577 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52683646 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52683646 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232872 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2232872 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4054.525384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989874 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137587270 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137587270 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52684677 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52684677 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232876 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2232876 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 2232025 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 2232025 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190259223 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190259223 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190259223 # number of overall hits -system.cpu.dcache.overall_hits::total 190259223 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1266823 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1266823 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1555660 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1555660 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 190271947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190271947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190271947 # number of overall hits +system.cpu.dcache.overall_hits::total 190271947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1267361 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1267361 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1554629 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1554629 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2822483 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2822483 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2822483 # number of overall misses -system.cpu.dcache.overall_misses::total 2822483 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15537538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15537538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33101884500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33101884500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2821990 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2821990 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2821990 # number of overall misses +system.cpu.dcache.overall_misses::total 2821990 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15534754000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15534754000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33071578000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33071578000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 516500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 516500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48639422500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48639422500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48639422500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48639422500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 138842400 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 138842400 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 48606332000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48606332000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48606332000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48606332000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 138854631 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 138854631 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232913 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2232913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232917 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2232917 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193081706 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193081706 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193081706 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193081706 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009124 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009124 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028681 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028681 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 193093937 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 193093937 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 193093937 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193093937 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009127 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009127 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028662 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028662 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014618 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014618 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12264.963614 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12264.963614 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21278.354203 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21278.354203 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.014615 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014615 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014615 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014615 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12257.560395 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12257.560395 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21272.971236 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21272.971236 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17232.848701 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17232.848701 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17232.848701 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17224.133324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17224.133324 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3299000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3250000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 559 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5901.610018 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5834.829443 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1102743 # number of writebacks -system.cpu.dcache.writebacks::total 1102743 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422432 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422432 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1207529 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1207529 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1102963 # number of writebacks +system.cpu.dcache.writebacks::total 1102963 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422886 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 422886 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1206451 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1206451 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1629961 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1629961 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1629961 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1629961 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844391 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34600.099134 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4250 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4250 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34276.522033 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34276.522033 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35330.600293 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34370.284375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34390.785090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35330.600293 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34370.284375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34390.785090 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -654,69 +658,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 104388 # number of writebacks -system.cpu.l2cache.writebacks::total 104388 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3420 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53041 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 56461 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103493 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 103493 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 156534 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159954 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 156534 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159954 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110207000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1665041000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775248000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3213249000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3213249000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110207000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4878290000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4988497000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110207000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4878290000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4988497000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063116 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065792 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293933 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293933 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.132164 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131269 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.132164 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32224.269006 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31391.583869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31442.021927 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 104381 # number of writebacks +system.cpu.l2cache.writebacks::total 104381 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 25 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 25 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3409 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53049 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 56458 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 103480 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 103480 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3409 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 156529 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159938 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3409 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 156529 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159938 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 109839000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1666010000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775849000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3212774500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3212774500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 109839000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4878784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4988623500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 109839000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4878784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4988623500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063119 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.153846 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293856 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293856 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131250 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132130 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.190852 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131250 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132130 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32220.299208 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31405.116025 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31454.337738 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.983922 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.983922 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32224.269006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31164.411566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31187.072533 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.298995 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.298995 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index c2c9b6670..6f010c94a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,137 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.433562 # Number of seconds simulated -sim_ticks 433562236500 # Number of ticks simulated -final_tick 433562236500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.433409 # Number of seconds simulated +sim_ticks 433408519000 # Number of ticks simulated +final_tick 433408519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69861 # Simulator instruction rate (inst/s) -host_op_rate 129182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36630948 # Simulator tick rate (ticks/s) -host_mem_usage 312956 # Number of bytes of host memory used -host_seconds 11835.95 # Real time elapsed on the host +host_inst_rate 113614 # Simulator instruction rate (inst/s) +host_op_rate 210085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59550946 # Simulator tick rate (ticks/s) +host_mem_usage 266596 # Number of bytes of host memory used +host_seconds 7277.95 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 223808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 27615936 # Number of bytes read from this memory -system.physmem.bytes_read::total 27839744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 20802240 # Number of bytes written to this memory -system.physmem.bytes_written::total 20802240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 431499 # Number of read requests responded to by this memory -system.physmem.num_reads::total 434996 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 325035 # Number of write requests responded to by this memory -system.physmem.num_writes::total 325035 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 516207 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 63695437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64211644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516207 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 47979824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 47979824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 47979824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 63695437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 112191469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 223616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 27616960 # Number of bytes read from this memory +system.physmem.bytes_read::total 27840576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 223616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 223616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 20804096 # Number of bytes written to this memory +system.physmem.bytes_written::total 20804096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 431515 # Number of read requests responded to by this memory +system.physmem.num_reads::total 435009 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 325064 # Number of write requests responded to by this memory +system.physmem.num_writes::total 325064 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 515947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 63720390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64236338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 515947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 515947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 48001124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48001124 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48001124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 515947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 63720390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 112237462 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 867124474 # number of cpu cycles simulated +system.cpu.numCycles 866817039 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 221451605 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 221451605 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 14391219 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 156554468 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 152744780 # Number of BTB hits +system.cpu.BPredUnit.lookups 221487081 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 221487081 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 14390308 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 156608955 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 152775295 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 187033735 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1232378576 # Number of instructions fetch has processed -system.cpu.fetch.Branches 221451605 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 152744780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 382759458 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 92090467 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 211510860 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30313 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 293412 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 179381043 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 4119516 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 859080204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.662810 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.408007 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 187015787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1232613370 # Number of instructions fetch has processed +system.cpu.fetch.Branches 221487081 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 152775295 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 382812407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 92129156 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 211136743 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29595 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 290923 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 179403606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 4116177 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 858776870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.664123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.408324 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 480734760 55.96% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25482181 2.97% 58.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28110276 3.27% 62.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 29422032 3.42% 65.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 18933642 2.20% 67.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 25065200 2.92% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31695568 3.69% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30727505 3.58% 78.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 188909040 21.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 480379655 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25485451 2.97% 58.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28110483 3.27% 62.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 29418527 3.43% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 18947498 2.21% 67.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 25073247 2.92% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31697541 3.69% 74.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30731731 3.58% 78.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 188932737 22.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 859080204 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.255386 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.421225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 243920658 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 168382016 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 324921479 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44403625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 77452426 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2234163398 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 77452426 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 277622568 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38425038 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15999 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 333490253 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 132073920 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2182629484 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24122 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19618394 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 98320386 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 151 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2282631567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5519360713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5519123398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 237315 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 858776870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255518 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.421999 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 243893330 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 168016637 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 325049297 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44326191 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 77491415 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2234477290 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 77491415 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 277619036 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38518487 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 15798 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 333479611 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 131652523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2182901177 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23899 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 19427368 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 98042792 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 161 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2282806171 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5519898710 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5519661560 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 237150 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040851 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 668590716 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1589 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1547 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 322287185 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528399687 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210789135 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 202484637 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58642789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2088380391 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24636 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1835578469 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 977153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 553508636 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 915245477 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 859080204 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.136679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.890485 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 668765320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1577 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 321506074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 528464573 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210836617 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 202710665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58518610 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2088631495 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25170 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1835731702 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 979947 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 553767245 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 915534947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24617 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 858776870 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.137612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.891337 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 233267501 27.15% 27.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 144027396 16.77% 43.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 136780566 15.92% 59.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 136553598 15.90% 75.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 99295309 11.56% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 59689212 6.95% 94.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35426860 4.12% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12177405 1.42% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1862357 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 233191073 27.15% 27.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 144020170 16.77% 43.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 136609479 15.91% 59.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 135995630 15.84% 75.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 99689263 11.61% 87.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 59771994 6.96% 94.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 35471375 4.13% 98.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12162676 1.42% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1865210 0.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 859080204 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 858776870 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5022876 32.65% 32.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5023267 32.65% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.65% # attempts to use FU when none available @@ -160,12 +161,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.65% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.65% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7731976 50.26% 82.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2628669 17.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7736612 50.28% 82.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2627522 17.08% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2701218 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1210723498 65.96% 66.11% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2697797 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1210853930 65.96% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.11% # Type of FU issued @@ -194,84 +195,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.11% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 444235410 24.20% 90.31% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 177918343 9.69% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 444242795 24.20% 90.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 177937180 9.69% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1835578469 # Type of FU issued -system.cpu.iq.rate 2.116857 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15383521 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008381 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4546556112 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2642088218 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1793025560 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 41704 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 79014 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 9750 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1848241436 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 19336 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 170057316 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1835731702 # Type of FU issued +system.cpu.iq.rate 2.117785 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15387401 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4546566873 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2642600298 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1793170888 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 40749 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 78738 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 9468 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1848402423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 18883 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 170058795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144297531 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 517217 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 266012 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61629484 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 144362417 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 511205 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 267668 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61676904 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10771 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 10972 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 77452426 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5095399 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 776506 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2088405027 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2538461 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528399687 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210789669 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5336 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 420481 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70453 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 266012 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10035135 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4886780 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 14921915 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805657318 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 435939313 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29921151 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 77491415 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5069554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 791692 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2088656665 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2509040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 528464573 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210837089 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 437341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70182 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 267668 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10030872 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4891333 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 14922205 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1805797916 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 435944125 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29933786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 608546299 # number of memory reference insts executed -system.cpu.iew.exec_branches 171183701 # Number of branches executed -system.cpu.iew.exec_stores 172606986 # Number of stores executed -system.cpu.iew.exec_rate 2.082351 # Inst execution rate -system.cpu.iew.wb_sent 1800375599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1793035310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1362115146 # num instructions producing a value -system.cpu.iew.wb_consumers 1993206857 # num instructions consuming a value +system.cpu.iew.exec_refs 608566280 # number of memory reference insts executed +system.cpu.iew.exec_branches 171216670 # Number of branches executed +system.cpu.iew.exec_stores 172622155 # Number of stores executed +system.cpu.iew.exec_rate 2.083252 # Inst execution rate +system.cpu.iew.wb_sent 1800513420 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1793180356 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1362010404 # num instructions producing a value +system.cpu.iew.wb_consumers 1993207324 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.067795 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.683379 # average fanout of values written-back +system.cpu.iew.wb_rate 2.068695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.683326 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 559448088 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 559701427 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14421135 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 781627778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.956160 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.445660 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14419517 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 781285455 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.957017 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.446096 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 285492936 36.53% 36.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197198069 25.23% 61.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62579121 8.01% 69.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 91937051 11.76% 81.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26882169 3.44% 84.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 29023123 3.71% 88.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9810981 1.26% 89.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10323566 1.32% 91.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 68380762 8.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 285259296 36.51% 36.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 196991997 25.21% 61.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 62815706 8.04% 69.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 91733389 11.74% 81.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26919948 3.45% 84.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 29020227 3.71% 88.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9830313 1.26% 89.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10314314 1.32% 91.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 68400265 8.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 781627778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 781285455 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -282,69 +283,69 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317557 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 68380762 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 68400265 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2801683803 # The number of ROB reads -system.cpu.rob.rob_writes 4254544815 # The number of ROB writes -system.cpu.timesIdled 198794 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8044270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2801575316 # The number of ROB reads +system.cpu.rob.rob_writes 4255093941 # The number of ROB writes +system.cpu.timesIdled 198389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8040169 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988699 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.048674 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.048674 # CPI: Total CPI of All Threads -system.cpu.ipc 0.953585 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.953585 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3391389205 # number of integer regfile reads -system.cpu.int_regfile_writes 1872893526 # number of integer regfile writes -system.cpu.fp_regfile_reads 9748 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 993246616 # number of misc regfile reads -system.cpu.icache.replacements 5750 # number of replacements -system.cpu.icache.tagsinuse 1040.901542 # Cycle average of tags in use -system.cpu.icache.total_refs 179166863 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7354 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 24363.185069 # Average number of references to valid blocks. +system.cpu.cpi 1.048302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.048302 # CPI: Total CPI of All Threads +system.cpu.ipc 0.953923 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.953923 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3391505058 # number of integer regfile reads +system.cpu.int_regfile_writes 1872959305 # number of integer regfile writes +system.cpu.fp_regfile_reads 9467 # number of floating regfile reads +system.cpu.fp_regfile_writes 1 # number of floating regfile writes +system.cpu.misc_regfile_reads 993321385 # number of misc regfile reads +system.cpu.icache.replacements 5754 # number of replacements +system.cpu.icache.tagsinuse 1042.434990 # Cycle average of tags in use +system.cpu.icache.total_refs 179199016 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 7367 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 24324.557622 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1040.901542 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.508253 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.508253 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 179183149 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179183149 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179183149 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179183149 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179183149 # number of overall hits -system.cpu.icache.overall_hits::total 179183149 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 197894 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 197894 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 197894 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 197894 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 197894 # number of overall misses -system.cpu.icache.overall_misses::total 197894 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1518962500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1518962500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1518962500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1518962500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1518962500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1518962500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 179381043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 179381043 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 179381043 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 179381043 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179381043 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179381043 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001103 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001103 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001103 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001103 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001103 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7675.636957 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7675.636957 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7675.636957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7675.636957 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7675.636957 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1042.434990 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.509001 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.509001 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 179215714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 179215714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 179215714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 179215714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 179215714 # number of overall hits +system.cpu.icache.overall_hits::total 179215714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 187892 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 187892 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 187892 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 187892 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 187892 # number of overall misses +system.cpu.icache.overall_misses::total 187892 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1425771000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1425771000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1425771000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1425771000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1425771000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1425771000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 179403606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 179403606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 179403606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 179403606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 179403606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 179403606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001047 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001047 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001047 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001047 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001047 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001047 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7588.247504 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 7588.247504 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 7588.247504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 7588.247504 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 7588.247504 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1612 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1612 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1612 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1612 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1612 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1612 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 196282 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 196282 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 196282 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 196282 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 196282 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 196282 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 850572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 850572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 850572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 850572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 850572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 850572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001094 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001094 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001094 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001094 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4333.418245 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4333.418245 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4333.418245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4333.418245 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1602 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1602 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1602 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1602 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1602 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1602 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 186290 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 186290 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 186290 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 186290 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 186290 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 186290 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 789947000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 789947000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 789947000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 789947000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 789947000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 789947000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001038 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001038 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001038 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001038 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4240.415481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4240.415481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4240.415481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4240.415481 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2529239 # number of replacements -system.cpu.dcache.tagsinuse 4087.824868 # Cycle average of tags in use -system.cpu.dcache.total_refs 410277951 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2533335 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 161.951716 # Average number of references to valid blocks. +system.cpu.dcache.replacements 2529214 # number of replacements +system.cpu.dcache.tagsinuse 4087.821968 # Cycle average of tags in use +system.cpu.dcache.total_refs 410284602 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2533310 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 161.955940 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1779749000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.824868 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 261532697 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 261532697 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148197019 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148197019 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 409729716 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 409729716 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 409729716 # number of overall hits -system.cpu.dcache.overall_hits::total 409729716 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2781068 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2781068 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 963182 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 963182 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3744250 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3744250 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3744250 # number of overall misses -system.cpu.dcache.overall_misses::total 3744250 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36062982500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36062982500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18107985000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18107985000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 54170967500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 54170967500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 54170967500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 54170967500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 264313765 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 264313765 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4087.821968 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998003 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998003 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 261560100 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 261560100 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148207018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148207018 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 409767118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 409767118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 409767118 # number of overall hits +system.cpu.dcache.overall_hits::total 409767118 # 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number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53391126000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53391126000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53391126000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53391126000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 264320137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 264320137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 413473966 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 413473966 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 413473966 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 413473966 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010522 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010522 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006457 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006457 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009056 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009056 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009056 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009056 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12967.314176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12967.314176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18800.169646 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 18800.169646 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14467.775255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14467.775255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14467.775255 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 413480338 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 413480338 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 413480338 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 413480338 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010442 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010442 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006390 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006390 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008980 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008980 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008980 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008980 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12918.215227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12918.215227 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18607.522375 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18607.522375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14378.659492 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.659492 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14378.659492 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,144 +450,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2304434 # number of writebacks -system.cpu.dcache.writebacks::total 2304434 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018833 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1018833 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3201 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3201 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1022034 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1022034 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1022034 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1022034 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762235 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762235 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 959981 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 959981 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2722216 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2722216 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2722216 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2722216 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12600404545 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12600404545 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15024414005 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15024414005 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27624818550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27624818550 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27624818550 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27624818550 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2304349 # number of writebacks +system.cpu.dcache.writebacks::total 2304349 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 997818 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 997818 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3197 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3197 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1001015 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1001015 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1001015 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1001015 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762219 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762219 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 949986 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 949986 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2712205 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2712205 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2712205 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2712205 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12599150566 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12599150566 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14683018004 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14683018004 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27282168570 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27282168570 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27282168570 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27282168570 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006667 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006436 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006436 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7150.240771 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7150.240771 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15650.741009 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15650.741009 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10147.915724 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10147.915724 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006369 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006369 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006559 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006559 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006559 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006559 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7149.594100 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7149.594100 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15456.036198 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15456.036198 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10059.036308 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10059.036308 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 408708 # number of replacements -system.cpu.l2cache.tagsinuse 29318.138904 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3612304 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 441048 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 8.190274 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 211122250000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21095.553590 # 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mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991855 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.271084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.271084 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.171237 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.477518 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170352 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.171237 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31932.598741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31224.426305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31235.385299 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.173043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.173043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.914186 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.914186 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31932.598741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31121.861638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31128.372894 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 95e13097c..0912a812f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.646278 # Number of seconds simulated -sim_ticks 646278131000 # Number of ticks simulated -final_tick 646278131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 646278143000 # Number of ticks simulated +final_tick 646278143000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212773 # Simulator instruction rate (inst/s) -host_op_rate 212773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75429257 # Simulator tick rate (ticks/s) -host_mem_usage 229040 # Number of bytes of host memory used -host_seconds 8568.00 # Real time elapsed on the host +host_inst_rate 208687 # Simulator instruction rate (inst/s) +host_op_rate 208687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73980757 # Simulator tick rate (ticks/s) +host_mem_usage 229204 # Number of bytes of host memory used +host_seconds 8735.76 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 191680 # Number of bytes read from this memory @@ -24,16 +24,16 @@ system.physmem.num_reads::total 1479012 # Nu system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 296591 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146167855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146464445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 146167852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146464443 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 296591 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 6624813 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 6624813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 296591 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146167855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153089259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 146167852 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 153089256 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1292556263 # number of cpu cycles simulated +system.cpu.numCycles 1292556287 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 394747270 # Number of BP lookups @@ -78,22 +78,22 @@ system.cpu.BPredUnit.BTBHits 262010178 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 57787448 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 7273 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421195056 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 421195062 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 3322341707 # Number of instructions fetch has processed system.cpu.fetch.Branches 394747270 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 319797626 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 638354680 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162914777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98034183 # Number of cycles fetch has spent blocked +system.cpu.fetch.SquashCycles 162914776 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 98034186 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9273 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 9284 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 401438115 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 8412038 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.570619 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.140035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 654074173 50.61% 50.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 654074192 50.61% 50.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 60911661 4.71% 55.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 43750931 3.39% 58.71% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 72637907 5.62% 64.33% # Number of instructions fetched each cycle (Total) @@ -105,65 +105,65 @@ system.cpu.fetch.rateDist::8 240462043 18.61% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1292428853 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1292428872 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.305400 # Number of branch fetches per cycle system.cpu.fetch.rate 2.570365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 452871359 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80658875 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 614115226 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9960098 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134823295 # Number of cycles decode is squashing +system.cpu.decode.IdleCycles 452871377 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80658879 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 614115225 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9960097 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134823294 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 34649231 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12312 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3231646724 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 3231646719 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 46688 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134823295 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 482927881 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33597057 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 134823294 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 482927898 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 33597059 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 26321 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 592678256 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48376043 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3142025534 # Number of instructions processed by rename +system.cpu.rename.RunCycles 592678255 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48376045 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3142025529 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 359 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 11387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42577596 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2088048295 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3654580538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3537192552 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 42577598 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2088048291 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3654580534 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3537192548 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 117387986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 703079225 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 703079221 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4247 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 139 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 143016933 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 739120184 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 143016934 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 739120183 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 360450433 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 67842482 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 9359459 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2647443518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 2647443516 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 119 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2196739038 # Number of instructions issued +system.cpu.iq.iqInstsIssued 2196739037 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17945817 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 824288888 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 711675230 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 824288886 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 711675229 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1292428872 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.699698 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.805222 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470829214 36.43% 36.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 470829232 36.43% 36.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 219635474 16.99% 53.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252835920 19.56% 72.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 120249082 9.30% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106312850 8.23% 90.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 252835921 19.56% 72.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120249084 9.30% 82.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 106312849 8.23% 90.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 78591497 6.08% 96.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21017975 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17286985 1.34% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21017973 1.63% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17286986 1.34% 99.56% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 5669856 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1292428853 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1292428872 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 1140834 3.16% 3.16% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available @@ -199,7 +199,7 @@ system.cpu.iq.fu_full::MemWrite 10866173 30.12% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1257954368 57.26% 57.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1257954367 57.26% 57.26% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 29223285 1.33% 58.60% # Type of FU issued @@ -232,21 +232,21 @@ system.cpu.iq.FU_type_0::MemRead 590393009 26.88% 86.18% # Ty system.cpu.iq.FU_type_0::MemWrite 303689578 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2196739038 # Type of FU issued +system.cpu.iq.FU_type_0::total 2196739037 # Type of FU issued system.cpu.iq.rate 1.699531 # Inst issue rate system.cpu.iq.fu_busy_cnt 36075558 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016422 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5585448848 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3387972541 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_reads 5585448865 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3387972537 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 2024033733 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 154479456 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 83833082 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 75371142 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2153745376 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 2153745375 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 79066468 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69378492 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 228050158 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 228050157 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2255425 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 75959 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 149655537 # Number of stores squashed @@ -255,12 +255,12 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 4423 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134823295 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4267154 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 134823294 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4267155 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 460832 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3006059050 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2702145 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 739120184 # Number of dispatched load instructions +system.cpu.iew.iewDispatchedInsts 3006059047 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2702146 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 739120183 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 360450433 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 119 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 451591 # Number of times the IQ has become full, causing a stall @@ -271,41 +271,41 @@ system.cpu.iew.predictedNotTakenIncorrect 31610 # N system.cpu.iew.branchMispredicts 27624768 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 2105923301 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 528979869 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 90815737 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 90815736 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358615413 # number of nop insts executed +system.cpu.iew.exec_nop 358615412 # number of nop insts executed system.cpu.iew.exec_refs 821261997 # number of memory reference insts executed system.cpu.iew.exec_branches 282350798 # Number of branches executed system.cpu.iew.exec_stores 292282128 # Number of stores executed system.cpu.iew.exec_rate 1.629270 # Inst execution rate system.cpu.iew.wb_sent 2102194150 # cumulative count of insts sent to commit system.cpu.iew.wb_count 2099404875 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185212781 # num instructions producing a value -system.cpu.iew.wb_consumers 1754721969 # num instructions consuming a value +system.cpu.iew.wb_producers 1185212780 # num instructions producing a value +system.cpu.iew.wb_consumers 1754721967 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.624227 # insts written-back per cycle system.cpu.iew.wb_fanout 0.675442 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 980398498 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 980398495 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 27578641 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 1157605578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.735468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.494432 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 541345046 46.76% 46.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227581474 19.66% 66.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119272187 10.30% 76.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56742029 4.90% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 51019589 4.41% 86.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24162951 2.09% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18255182 1.58% 89.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 541345066 46.76% 46.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 227581476 19.66% 66.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119272186 10.30% 76.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56742028 4.90% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 51019590 4.41% 86.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24162950 2.09% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18255180 1.58% 89.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 15605334 1.35% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103621766 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103621768 8.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1157605558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1157605578 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,12 +316,12 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103621766 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103621768 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4037733484 # The number of ROB reads -system.cpu.rob.rob_writes 6113598013 # The number of ROB writes -system.cpu.timesIdled 3574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 127410 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4037733499 # The number of ROB reads +system.cpu.rob.rob_writes 6113598006 # The number of ROB writes +system.cpu.timesIdled 3575 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 127415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated @@ -356,12 +356,12 @@ system.cpu.icache.demand_misses::cpu.inst 11347 # n system.cpu.icache.demand_misses::total 11347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11347 # number of overall misses system.cpu.icache.overall_misses::total 11347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 204563500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 204563500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 204563500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 204563500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 204563500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204562000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204562000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204562000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204562000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204562000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 401438115 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 401438115 # number of demand (read+write) accesses @@ -374,12 +374,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.980964 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18027.980964 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.980964 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18027.980964 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18027.848771 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18027.848771 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18027.848771 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18027.848771 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -446,14 +446,14 @@ system.cpu.dcache.demand_misses::cpu.data 2543931 # n system.cpu.dcache.demand_misses::total 2543931 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2543931 # number of overall misses system.cpu.dcache.overall_misses::total 2543931 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76609230000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30362374985 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106971604985 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106971604985 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106971604985 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76609210500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30362476485 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106971686985 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106971686985 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106971686985 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 458970336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -472,14 +472,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003798 system.cpu.dcache.demand_miss_rate::total 0.003798 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003798 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003798 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.875316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.875316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.193322 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.193322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.727365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42049.727365 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39728.865203 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39728.865203 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49319.358194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49319.358194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42049.759598 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42049.759598 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 174500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -506,14 +506,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1532162 system.cpu.dcache.demand_mshr_misses::total 1532162 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1532162 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1532162 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266374000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176553000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53442927000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53442927000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50266349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3176578500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 53442927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53442927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 53442927500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses @@ -522,24 +522,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.940516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44360.928401 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728670 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34415.923399 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.284511 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34880.728996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34880.728996 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1480672 # number of replacements -system.cpu.l2cache.tagsinuse 32700.801266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 32700.801233 # Cycle average of tags in use system.cpu.l2cache.total_refs 66336 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.043832 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3222.422706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 46.121130 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29432.257430 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 3222.422931 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 46.121134 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29432.257169 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.098341 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001408 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.898201 # Average percentage of cache occupancy @@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 2995 # system.cpu.l2cache.overall_misses::cpu.data 1476017 # number of overall misses system.cpu.l2cache.overall_misses::total 1479012 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 106968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399950500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 48506918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813587500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2813587500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48399927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 48506895000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2813613000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2813613000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 106968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51213538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 51320506000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 51213540000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 51320508000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 106968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51213538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 51320506000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 51213540000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 51320508000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10134 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460549 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1470683 # number of ReadReq accesses(hits+misses) @@ -604,16 +604,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_miss_rate::cpu.data 0.963356 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.958968 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35715.525876 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.594752 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.498073 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.552099 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.552099 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34346.578075 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34349.481432 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42085.933527 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42085.933527 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35715.525876 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.119342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34699.181616 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34697.120697 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34699.182968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 107500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked @@ -636,16 +636,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 system.cpu.l2cache.overall_mshr_misses::cpu.data 1476017 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1479012 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717529000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814894000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612258000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612258000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43717505000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43814870000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2612284000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2612284000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329787000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46427152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46329789000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46427154000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329787000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46427152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46329789000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46427154000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295540 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964817 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960206 # mshr miss rate for ReadReq accesses @@ -658,16 +658,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295540 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963356 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.958968 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32509.181970 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.755946 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.906338 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.071858 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.071858 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31023.738915 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31026.889342 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39074.460765 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39074.460765 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32509.181970 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.383061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.652679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31388.384416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31390.654031 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 639c0707a..6cef7cd16 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.735463 # Number of seconds simulated -sim_ticks 735462942500 # Number of ticks simulated -final_tick 735462942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.737495 # Number of seconds simulated +sim_ticks 737494828500 # Number of ticks simulated +final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115593 # Simulator instruction rate (inst/s) -host_op_rate 157422 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61409842 # Simulator tick rate (ticks/s) -host_mem_usage 243732 # Number of bytes of host memory used -host_seconds 11976.30 # Real time elapsed on the host -sim_insts 1384378705 # Number of instructions simulated -sim_ops 1885333457 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 209152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94513152 # Number of bytes read from this memory -system.physmem.bytes_read::total 94722304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 209152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3268 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476768 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480036 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128508381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128792762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5751849 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5751849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128508381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134544612 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 117861 # Simulator instruction rate (inst/s) +host_op_rate 160511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62787760 # Simulator tick rate (ticks/s) +host_mem_usage 243784 # Number of bytes of host memory used +host_seconds 11745.84 # Real time elapsed on the host +sim_insts 1384378545 # Number of instructions simulated +sim_ops 1885333297 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory +system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1470925886 # number of cpu cycles simulated +system.cpu.numCycles 1474989658 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 526944807 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 400998639 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 36103831 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 389912593 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 290078755 # Number of BTB hits +system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59371448 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2810327 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 451184041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2630280787 # Number of instructions fetch has processed -system.cpu.fetch.Branches 526944807 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 349450203 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 714901139 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 225817309 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101657894 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2270 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20337 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 420935290 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11687737 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.541647 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.159630 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed +system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 737052267 50.76% 50.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55648987 3.83% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113021811 7.78% 62.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71058557 4.89% 67.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 83474414 5.75% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 55105836 3.80% 76.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35245314 2.43% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 35853884 2.47% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 265431813 18.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1451892883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.358240 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.788180 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 498609504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80967892 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 677644967 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10558484 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 184112036 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 82169847 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15539 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3562988403 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 34450 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 184112036 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 537763866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32181538 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 530906 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 647549947 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49754590 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3439334544 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4507727 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40704108 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1637 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3357877059 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16273276362 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15612337004 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 660939358 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993153074 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1364723985 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50374 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45755 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138448530 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1057693537 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 579697033 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32301976 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40224751 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3204253855 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 55204 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2728539607 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 26296633 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1318520975 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3049786617 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 32197 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1451892883 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.879298 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913242 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 529391229 36.46% 36.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201881649 13.90% 50.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217086646 14.95% 65.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180698536 12.45% 77.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155303824 10.70% 88.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101627119 7.00% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47687061 3.28% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10818751 0.75% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7398068 0.51% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1451892883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1769730 1.85% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23897 0.03% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57017691 59.74% 61.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36624161 38.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1267852875 46.47% 46.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11249841 0.41% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876502 0.25% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5509242 0.20% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 10 0.00% 47.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23422716 0.86% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 900241539 32.99% 81.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 512011592 18.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2728539607 # Type of FU issued -system.cpu.iq.rate 1.854981 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95435479 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.034977 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6896111029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4417455828 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2500265065 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 134593180 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 105438972 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60061785 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2754719800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 69255286 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 70868561 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued +system.cpu.iq.rate 1.848489 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 426304733 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264948 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1116073 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 302700113 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 184112036 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17217570 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2222077 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3204383976 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 3801477 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1057693537 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 579697033 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 44065 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2220604 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 655 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1116073 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 37419443 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9018722 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46438165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2627591050 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846492275 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100948557 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 74917 # number of nop insts executed -system.cpu.iew.exec_refs 1329282286 # number of memory reference insts executed -system.cpu.iew.exec_branches 361424797 # Number of branches executed -system.cpu.iew.exec_stores 482790011 # Number of stores executed -system.cpu.iew.exec_rate 1.786352 # Inst execution rate -system.cpu.iew.wb_sent 2588656133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2560326850 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1477151291 # num instructions producing a value -system.cpu.iew.wb_consumers 2761912490 # num instructions consuming a value +system.cpu.iew.exec_nop 80181 # number of nop insts executed +system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed +system.cpu.iew.exec_branches 359055744 # Number of branches executed +system.cpu.iew.exec_stores 483931273 # Number of stores executed +system.cpu.iew.exec_rate 1.780217 # Inst execution rate +system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1475385900 # num instructions producing a value +system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.740623 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534829 # average fanout of values written-back +system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1319039983 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23007 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41626374 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1267780849 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.487122 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.205349 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 586908423 46.29% 46.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 318188211 25.10% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101915381 8.04% 79.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79184752 6.25% 85.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52930899 4.18% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24002778 1.89% 91.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17056118 1.35% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9057246 0.71% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78537041 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1267780849 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389721 # Number of instructions committed -system.cpu.commit.committedOps 1885344473 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384389561 # Number of instructions committed +system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385724 # Number of memory references committed -system.cpu.commit.loads 631388804 # Number of loads committed +system.cpu.commit.refs 908385660 # Number of memory references committed +system.cpu.commit.loads 631388772 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350167 # Number of branches committed +system.cpu.commit.branches 291350135 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705359 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78537041 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4393609919 # The number of ROB reads -system.cpu.rob.rob_writes 6592898385 # The number of ROB writes -system.cpu.timesIdled 1319009 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19033003 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378705 # Number of Instructions Simulated -system.cpu.committedOps 1885333457 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378705 # Number of Instructions Simulated -system.cpu.cpi 1.062517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.062517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941161 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.941161 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12954963873 # number of integer regfile reads -system.cpu.int_regfile_writes 2433899431 # number of integer regfile writes -system.cpu.fp_regfile_reads 71453474 # number of floating regfile reads -system.cpu.fp_regfile_writes 51512029 # number of floating regfile writes -system.cpu.misc_regfile_reads 4110345957 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776148 # number of misc regfile writes -system.cpu.icache.replacements 27727 # number of replacements -system.cpu.icache.tagsinuse 1657.357291 # Cycle average of tags in use -system.cpu.icache.total_refs 420895339 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29422 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14305.463225 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4384745152 # The number of ROB reads +system.cpu.rob.rob_writes 6584968170 # The number of ROB writes +system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384378545 # Number of Instructions Simulated +system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated +system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads +system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads +system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes +system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads +system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes +system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes +system.cpu.icache.replacements 27555 # number of replacements +system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use +system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1657.357291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.809256 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.809256 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 420900012 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420900012 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420900012 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420900012 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420900012 # number of overall hits -system.cpu.icache.overall_hits::total 420900012 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35278 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35278 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35278 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35278 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35278 # number of overall misses -system.cpu.icache.overall_misses::total 35278 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 347510000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 347510000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 347510000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 347510000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 347510000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420935290 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420935290 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420935290 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420935290 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420935290 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits +system.cpu.icache.overall_hits::total 417833790 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses +system.cpu.icache.overall_misses::total 35126 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9850.615114 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9850.615114 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9850.615114 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9850.615114 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,110 +399,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 933 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 933 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 933 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 933 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 933 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 933 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34345 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34345 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34345 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34345 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34345 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 217293500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 217293500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 217293500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 217293500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6326.787014 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6326.787014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6326.787014 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532802 # number of replacements -system.cpu.dcache.tagsinuse 4094.906416 # Cycle average of tags in use -system.cpu.dcache.total_refs 1033702432 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536898 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.590134 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1533020 # number of replacements +system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use +system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.906416 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 757546654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 757546654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115180 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115180 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11970 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11970 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11608 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11608 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1033661834 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1033661834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1033661834 # number of overall hits -system.cpu.dcache.overall_hits::total 1033661834 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2867388 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2867388 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 820498 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 820498 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3687886 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3687886 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3687886 # number of overall misses -system.cpu.dcache.overall_misses::total 3687886 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 99520769500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33963338500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133484108000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133484108000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133484108000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 760414042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 760414042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits +system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses +system.cpu.dcache.overall_misses::total 3304303 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11976 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11608 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1037349720 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1037349720 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003771 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003771 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000501 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003555 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003555 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003555 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003555 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34707.814045 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34707.814045 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41393.566468 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41393.566468 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 36083.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36195.291286 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36195.291286 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,142 +511,142 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108638 # number of writebacks -system.cpu.dcache.writebacks::total 108638 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1403027 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2146065 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2146065 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2146065 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464361 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77460 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77460 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541821 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50337065001 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525124500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52862189501 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52862189501 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001926 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001926 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks +system.cpu.dcache.writebacks::total 108316 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001486 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001486 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34374.764830 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32599.076943 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34285.555522 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34285.555522 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480261 # number of replacements -system.cpu.l2cache.tagsinuse 32698.232813 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88469 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513005 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.058472 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480259 # number of replacements +system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513003 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.058281 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3127.449947 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 61.048059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29509.734807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.095442 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001863 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.900566 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997871 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53654 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 79798 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108638 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108638 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3112.320696 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 61.394609 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29524.725342 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.094980 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001874 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.901023 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997877 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 25967 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53813 # 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average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3274 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1480094 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3274 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1480094 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105728000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44228314000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44334042000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152892000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049197000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049197000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105728000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46277511000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46383239000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105728000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46277511000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46383239000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963243 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.547661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32274.479804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.011141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.083330 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 52b1e9eb7..361b9fcbc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047910 # Number of seconds simulated -sim_ticks 47910283500 # Number of ticks simulated -final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047911 # Number of seconds simulated +sim_ticks 47910588500 # Number of ticks simulated +final_tick 47910588500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137428 # Simulator instruction rate (inst/s) -host_op_rate 137428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74532010 # Simulator tick rate (ticks/s) -host_mem_usage 227148 # Number of bytes of host memory used -host_seconds 642.82 # Real time elapsed on the host +host_inst_rate 102205 # Simulator instruction rate (inst/s) +host_op_rate 102205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55429613 # Simulator tick rate (ticks/s) +host_mem_usage 227308 # Number of bytes of host memory used +host_seconds 864.35 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 160515 # Nu system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10756036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 214419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225175443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10756036 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154921913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154921913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10756036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 214419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380097356 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 95820568 # number of cpu cycles simulated +system.cpu.numCycles 95821178 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups @@ -97,12 +97,12 @@ system.cpu.execution_unit.executions 44775821 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78582835 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed. -system.cpu.activity 73.356816 # Percentage of cycles cpu is active +system.cpu.timesIdled 467389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25530263 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70290915 # Number of cycles cpu stages are processed. +system.cpu.activity 73.356346 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.084678 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.084678 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921933 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.921933 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42394050 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53427128 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 55.757119 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 53163082 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42658096 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.518442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 52694545 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126633 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.007413 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 73699998 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121180 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.085899 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 49718969 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46102209 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.112755 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 85335 # number of replacements -system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1885.674638 # Cycle average of tags in use system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1885.674638 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits @@ -156,12 +156,12 @@ system.cpu.icache.demand_misses::cpu.inst 118639 # n system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses system.cpu.icache.overall_misses::total 118639 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081863500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2081863500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2081863500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2081863500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2081863500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses @@ -174,12 +174,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.884760 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17547.884760 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.884760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17547.884760 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +200,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 87381 system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1364888000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1364888000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364888000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1364888000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.963150 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.963150 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.963150 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4073.238819 # Cycle average of tags in use system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4073.238819 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits @@ -244,14 +244,14 @@ system.cpu.dcache.demand_misses::cpu.data 764068 # n system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses system.cpu.dcache.overall_misses::total 764068 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4228645000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42089863000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46318508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46318508000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46318508000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -268,20 +268,20 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.886669 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.886669 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63012.550153 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63012.550153 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60620.923792 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60620.923792 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6946123500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 55940.882990 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks @@ -304,12 +304,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 204347 system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7868977000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9805822000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9805822000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9805822000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7870166500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9807011500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9807011500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9807011500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -320,24 +320,24 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54813.807633 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47991.952414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47991.952414 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 136141 # number of replacements -system.cpu.l2cache.tagsinuse 28773.047265 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 28773.050902 # Cycle average of tags in use system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25287.688081 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1723.908362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1761.450821 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 25287.699561 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1723.905670 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1761.445671 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052609 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits @@ -367,14 +367,14 @@ system.cpu.l2cache.overall_misses::total 168567 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427362500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1541002500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 1968365000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838998500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6838998500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6840080000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6840080000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 427362500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8380001000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8807363500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8381082500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8808445000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 427362500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8380001000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8807363500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8381082500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8808445000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 87381 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 147958 # number of ReadReq accesses(hits+misses) @@ -402,14 +402,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.577822 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52195.226177 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52195.226177 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52213.702769 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52254.860085 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,14 +434,14 @@ system.cpu.l2cache.overall_mshr_misses::total 168567 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5255819000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5255819000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6437257500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6766411500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6437257500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6766411500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses @@ -456,14 +456,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40106.060375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40106.060375 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40103.775348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40140.783783 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7baadddcc..e1fb122e9 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.021620 # Number of seconds simulated -sim_ticks 21619648000 # Number of ticks simulated -final_tick 21619648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21619627000 # Number of ticks simulated +final_tick 21619627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236725 # Simulator instruction rate (inst/s) -host_op_rate 236725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64301983 # Simulator tick rate (ticks/s) -host_mem_usage 228176 # Number of bytes of host memory used -host_seconds 336.22 # Real time elapsed on the host +host_inst_rate 209503 # Simulator instruction rate (inst/s) +host_op_rate 209503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56907639 # Simulator tick rate (ticks/s) +host_mem_usage 228332 # Number of bytes of host memory used +host_seconds 379.91 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295744 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426560 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169611 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116040 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116040 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25872762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476221630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 502094391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25872762 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 343509756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 343509756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25872762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476221630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845604147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10295552 # Number of bytes read from this memory +system.physmem.bytes_read::total 10855232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160868 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169613 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116038 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116038 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25887588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 476213211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 502100799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25887588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 343504169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 343504169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25887588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 476213211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845604968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22479620 # DTB read hits -system.cpu.dtb.read_misses 218266 # DTB read misses -system.cpu.dtb.read_acv 51 # DTB read access violations -system.cpu.dtb.read_accesses 22697886 # DTB read accesses -system.cpu.dtb.write_hits 15794697 # DTB write hits -system.cpu.dtb.write_misses 42457 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15837154 # DTB write accesses -system.cpu.dtb.data_hits 38274317 # DTB hits -system.cpu.dtb.data_misses 260723 # DTB misses +system.cpu.dtb.read_hits 22478221 # DTB read hits +system.cpu.dtb.read_misses 218727 # DTB read misses +system.cpu.dtb.read_acv 49 # DTB read access violations +system.cpu.dtb.read_accesses 22696948 # DTB read accesses +system.cpu.dtb.write_hits 15797623 # DTB write hits +system.cpu.dtb.write_misses 42281 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15839904 # DTB write accesses +system.cpu.dtb.data_hits 38275844 # DTB hits +system.cpu.dtb.data_misses 261008 # DTB misses system.cpu.dtb.data_acv 51 # DTB access violations -system.cpu.dtb.data_accesses 38535040 # DTB accesses -system.cpu.itb.fetch_hits 14126097 # ITB hits -system.cpu.itb.fetch_misses 39352 # ITB misses +system.cpu.dtb.data_accesses 38536852 # DTB accesses +system.cpu.itb.fetch_hits 14126153 # ITB hits +system.cpu.itb.fetch_misses 38209 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14165449 # ITB accesses +system.cpu.itb.fetch_accesses 14164362 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43239299 # number of cpu cycles simulated +system.cpu.numCycles 43239256 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16709943 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10781072 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 476192 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12038225 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7471491 # Number of BTB hits +system.cpu.BPredUnit.lookups 16713940 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10785641 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 474517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12148042 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7471828 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1995310 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44665 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15444845 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106679218 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16709943 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9466801 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19799027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2146422 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5702055 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 320776 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 222277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.490770 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154588 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1996046 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 44341 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15442173 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106653150 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16713940 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9467874 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19795691 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2142333 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5738431 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8227 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 318072 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14126153 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 221095 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.488707 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.154001 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23030789 53.77% 53.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1545838 3.61% 57.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1407824 3.29% 60.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1518177 3.54% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4200095 9.81% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1866083 4.36% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 683567 1.60% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1088540 2.54% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7488903 17.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23059150 53.81% 53.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1544639 3.60% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1408806 3.29% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522467 3.55% 64.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4195710 9.79% 74.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1864977 4.35% 78.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685640 1.60% 79.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1085683 2.53% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7487769 17.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 42829816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.386453 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.467182 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16586159 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5216387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18831807 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 747368 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1448095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3802176 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109343 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104798684 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 306113 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1448095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17060162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2943499 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19071081 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2224009 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103374463 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 294 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 47714 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2072135 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62309566 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124647358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124190382 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 456976 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 42854841 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.386546 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.466582 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16604436 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5227614 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18845700 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 731163 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1445928 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3801623 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109086 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104782719 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304838 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1445928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17078558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2955442 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82947 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19068517 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2223449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103359605 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 254 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 47854 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2072460 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62291613 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124619411 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124164571 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 454840 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9762685 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5585 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5583 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4545963 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23367723 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16390642 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1133008 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 393146 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91432081 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5446 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89033358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 121532 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11257440 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4905922 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 863 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 42829816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.078770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.113525 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9744732 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5573 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5571 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4558890 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23363714 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16388828 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1131841 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 391237 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91420984 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89018152 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 120887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11240273 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4901766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 851 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 42854841 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.077202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.113927 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 14329925 33.46% 33.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7119620 16.62% 50.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5526453 12.90% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4793299 11.19% 74.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4689695 10.95% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2671983 6.24% 91.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950910 4.56% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1326668 3.10% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 421263 0.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 14370838 33.53% 33.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7100087 16.57% 50.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5540527 12.93% 63.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772141 11.14% 74.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4704722 10.98% 85.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2673915 6.24% 91.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1941470 4.53% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1325823 3.09% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 425318 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 42829816 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 42854841 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128939 6.83% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 795203 42.12% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 964007 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 128315 6.76% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 799448 42.10% 48.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 971123 51.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49729867 55.86% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43817 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49717774 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43792 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121200 0.14% 56.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120893 0.14% 56.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 87 0.00% 56.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122187 0.14% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38946 0.04% 56.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121944 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38928 0.04% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.22% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.22% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22972171 25.80% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16005027 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22969813 25.80% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16004865 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89033358 # Type of FU issued -system.cpu.iq.rate 2.059084 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1888149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021207 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222297193 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102291434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86992301 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609020 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 419648 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 296730 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90616918 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1450786 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89018152 # Type of FU issued +system.cpu.iq.rate 2.058735 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1898886 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021331 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222303440 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102266391 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86984314 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 607478 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 416601 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296142 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90613228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 303810 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1449481 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3091085 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5211 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17173 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1777265 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3087076 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1775451 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2461 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 40 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2459 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1448095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1762662 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92194 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100976081 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242299 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23367723 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16390642 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5446 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 53221 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 430 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17173 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250537 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173902 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 424439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88065648 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22701440 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 967710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1445928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1740049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 88499 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100965460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 244137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23363714 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16388828 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 53254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 431 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17226 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 250564 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 172705 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88055069 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22700407 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 963083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9538554 # number of nop insts executed -system.cpu.iew.exec_refs 38538948 # number of memory reference insts executed -system.cpu.iew.exec_branches 15139399 # Number of branches executed -system.cpu.iew.exec_stores 15837508 # Number of stores executed -system.cpu.iew.exec_rate 2.036704 # Inst execution rate -system.cpu.iew.wb_sent 87702246 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87289031 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33442850 # num instructions producing a value -system.cpu.iew.wb_consumers 43872911 # num instructions consuming a value +system.cpu.iew.exec_nop 9539042 # number of nop insts executed +system.cpu.iew.exec_refs 38540674 # number of memory reference insts executed +system.cpu.iew.exec_branches 15139519 # Number of branches executed +system.cpu.iew.exec_stores 15840267 # Number of stores executed +system.cpu.iew.exec_rate 2.036461 # Inst execution rate +system.cpu.iew.wb_sent 87694134 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87280456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33430607 # num instructions producing a value +system.cpu.iew.wb_consumers 43860363 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.018743 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762266 # average fanout of values written-back +system.cpu.iew.wb_rate 2.018547 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762205 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9533571 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9526459 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369490 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41381721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.134775 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.804212 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 368198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 41408913 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.133373 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.803824 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18296264 44.21% 44.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7146737 17.27% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3523583 8.51% 70.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2099457 5.07% 75.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2039541 4.93% 80.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1177840 2.85% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1135730 2.74% 85.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 713898 1.73% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5248671 12.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18342699 44.30% 44.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7125223 17.21% 61.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3513214 8.48% 69.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2087650 5.04% 75.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2070192 5.00% 80.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1179714 2.85% 82.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1132729 2.74% 85.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 709577 1.71% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5247915 12.67% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41381721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 41408913 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5248671 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5247915 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132689951 # The number of ROB reads -system.cpu.rob.rob_writes 197200056 # The number of ROB writes -system.cpu.timesIdled 24548 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 409483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132710787 # The number of ROB reads +system.cpu.rob.rob_writes 197183581 # The number of ROB writes +system.cpu.timesIdled 23387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 384415 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.543264 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.543264 # CPI: Total CPI of All Threads -system.cpu.ipc 1.840727 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.840727 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116607964 # number of integer regfile reads -system.cpu.int_regfile_writes 57862089 # number of integer regfile writes -system.cpu.fp_regfile_reads 251339 # number of floating regfile reads -system.cpu.fp_regfile_writes 241385 # number of floating regfile writes -system.cpu.misc_regfile_reads 38087 # number of misc regfile reads +system.cpu.cpi 0.543263 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.543263 # CPI: Total CPI of All Threads +system.cpu.ipc 1.840729 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.840729 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116590843 # number of integer regfile reads +system.cpu.int_regfile_writes 57851456 # number of integer regfile writes +system.cpu.fp_regfile_reads 250950 # number of floating regfile reads +system.cpu.fp_regfile_writes 240941 # number of floating regfile writes +system.cpu.misc_regfile_reads 38077 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 92930 # number of replacements -system.cpu.icache.tagsinuse 1930.212243 # Cycle average of tags in use -system.cpu.icache.total_refs 14026666 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 94978 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.683316 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18067713000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1930.212243 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942486 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942486 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14026666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14026666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14026666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14026666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14026666 # number of overall hits -system.cpu.icache.overall_hits::total 14026666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99431 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99431 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99431 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99431 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99431 # number of overall misses -system.cpu.icache.overall_misses::total 99431 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1030437000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1030437000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1030437000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1030437000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1030437000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007039 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007039 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007039 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007039 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10363.337390 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10363.337390 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10363.337390 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10363.337390 # average overall miss latency +system.cpu.icache.replacements 92836 # number of replacements +system.cpu.icache.tagsinuse 1929.378925 # Cycle average of tags in use +system.cpu.icache.total_refs 14026889 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 94884 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 147.831974 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18060721000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1929.378925 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942080 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942080 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14026889 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14026889 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14026889 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14026889 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14026889 # number of overall hits +system.cpu.icache.overall_hits::total 14026889 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99264 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99264 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99264 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99264 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99264 # number of overall misses +system.cpu.icache.overall_misses::total 99264 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1029034500 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10366.643496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +388,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4452 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4452 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4452 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4452 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4452 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94979 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 94979 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 94979 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 94979 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 94979 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 637690000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 637690000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 637690000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 637690000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006724 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006724 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006724 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006724 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6714.010465 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6714.010465 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6714.010465 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6714.010465 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4379 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4379 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4379 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4379 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4379 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4379 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94885 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006717 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006717 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006717 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6715.250040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6715.250040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6715.250040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201568 # number of replacements -system.cpu.dcache.tagsinuse 4075.950137 # Cycle average of tags in use -system.cpu.dcache.total_refs 34352337 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205664 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.031357 # Average number of references to valid blocks. +system.cpu.dcache.replacements 201660 # number of replacements +system.cpu.dcache.tagsinuse 4075.950117 # Cycle average of tags in use +system.cpu.dcache.total_refs 34352002 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205756 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.955044 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 168155000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4075.950137 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4075.950117 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.995105 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.995105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20774825 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20774825 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13577434 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13577434 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 78 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 78 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34352259 # 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number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1287631 # number of overall misses +system.cpu.dcache.overall_misses::total 1287631 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8533517000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8533517000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45981514500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45981514500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 54515031500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 54515031500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 54515031500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 54515031500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21026189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21026189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 78 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35639645 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35639645 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35639645 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35639645 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011959 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011959 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070890 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070890 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036122 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036122 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036122 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036122 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33931.077819 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33931.077819 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44365.782673 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44365.782673 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42327.750962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42327.750962 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42327.750962 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 103000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35639566 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35639566 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35639566 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35639566 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011965 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011965 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070897 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070897 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33918.886584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33918.886584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44381.773475 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44381.773475 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 42337.464305 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 42337.464305 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 96000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6058.823529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5647.058824 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166337 # number of writebacks -system.cpu.dcache.writebacks::total 166337 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 189183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892539 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 892539 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1081722 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1081722 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1081722 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62260 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6766238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6766238000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6766238000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6766238000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002961 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002961 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005771 # 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average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 166377 # number of writebacks +system.cpu.dcache.writebacks::total 166377 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 189261 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 189261 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 892614 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 892614 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1081875 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1081875 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1081875 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1081875 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62325 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62325 # 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number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 94885 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205756 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 300641 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092164 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.479743 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.245814 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913193 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.913193 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092020 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.782203 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.564161 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092020 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.782203 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.564161 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35318.764302 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34543.045804 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34718.460543 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38388.543154 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38388.543154 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37552.225386 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35318.764302 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37673.567641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37552.225386 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 34000 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913102 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.913102 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092164 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.781839 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.564171 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092164 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.781839 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.564171 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35321.326472 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34549.148801 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34723.889866 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38530.564485 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38530.564485 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37663.265787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35321.326472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37790.576746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37663.265787 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2833.333333 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2636.363636 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 116040 # number of writebacks -system.cpu.l2cache.writebacks::total 116040 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8740 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29910 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 38650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 169611 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169611 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281019000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 942134500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223153500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4629566000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4629566000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5571700500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5852719500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5571700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5852719500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480451 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 116038 # number of writebacks +system.cpu.l2cache.writebacks::total 116038 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8745 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29899 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38644 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130969 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169613 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169613 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 281196000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 941994500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223190500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4649150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 281196000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5591145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5872341000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 281196000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5591145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5872341000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.479743 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.245814 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.564161 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092020 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.564161 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32153.203661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31498.980274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31646.921087 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35350.722734 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32153.203661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34634.586097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34506.721262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913102 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.564171 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092164 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781839 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.564171 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32155.060034 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31505.886484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.792154 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35498.098787 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32155.060034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34756.104384 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34621.998314 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6fb730a89..bc1c3c499 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024460 # Number of seconds simulated -sim_ticks 24460150500 # Number of ticks simulated -final_tick 24460150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024450 # Number of seconds simulated +sim_ticks 24450292500 # Number of ticks simulated +final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167024 # Simulator instruction rate (inst/s) -host_op_rate 237012 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57603012 # Simulator tick rate (ticks/s) -host_mem_usage 242500 # Number of bytes of host memory used -host_seconds 424.63 # Real time elapsed on the host -sim_insts 70923824 # Number of instructions simulated -sim_ops 100643071 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028736 # Number of bytes read from this memory -system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417152 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125449 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84643 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84643 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13367702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 328237392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341605094 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13367702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 221468466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 221468466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13367702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 328237392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 563073559 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 166577 # Simulator instruction rate (inst/s) +host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57425524 # Simulator tick rate (ticks/s) +host_mem_usage 242552 # Number of bytes of host memory used +host_seconds 425.77 # Real time elapsed on the host +sim_insts 70924074 # Number of instructions simulated +sim_ops 100643321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory +system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48920302 # number of cpu cycles simulated +system.cpu.numCycles 48900586 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16960531 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12985874 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 661473 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11570513 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7976664 # Number of BTB hits +system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1883015 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 115088 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12843999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87580035 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16960531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9859679 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21787094 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2782746 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10982319 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 606 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12079139 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582724 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336366 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25881368 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2178299 4.57% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2007274 4.21% 63.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2021463 4.24% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1548956 3.25% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1412983 2.97% 73.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 995678 2.09% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1240946 2.60% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10360054 21.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47647021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346697 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.790259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15031484 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9298191 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19969978 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1421734 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1925634 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3462876 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109476 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120212842 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 378015 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1925634 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16795731 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2963104 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 805180 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19544890 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5612482 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117675747 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12709 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4780104 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 263 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117787272 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541948309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541940540 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99158584 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18628688 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37002 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 36987 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13169886 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30082364 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22781735 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3607820 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4315548 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113341575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51734 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108469975 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 351751 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12575588 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 30093615 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14709 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47647021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.276532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995144 # Number of insts issued each cycle +system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11903537 24.98% 24.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8354851 17.53% 42.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7454693 15.65% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7158692 15.02% 73.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5519097 11.58% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3907609 8.20% 92.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1895733 3.98% 96.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 881641 1.85% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571168 1.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47647021 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112989 4.45% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1419251 55.85% 60.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1008989 39.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57363382 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91507 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 228 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,158 +239,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29217041 26.94% 79.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21797810 20.10% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108469975 # Type of FU issued -system.cpu.iq.rate 2.217279 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2541231 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023428 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 267479180 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125995514 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106424512 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 773 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1272 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 187 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 111010818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 388 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2214998 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued +system.cpu.iq.rate 2.217820 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2772017 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7458 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2222758 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 51 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1925634 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 929341 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37355 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113473181 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 343640 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30082364 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22781735 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35157 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2560 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3541 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 428613 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 264355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 692968 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107247329 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28841677 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1222646 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79872 # number of nop insts executed -system.cpu.iew.exec_refs 50315882 # number of memory reference insts executed -system.cpu.iew.exec_branches 14663606 # Number of branches executed -system.cpu.iew.exec_stores 21474205 # Number of stores executed -system.cpu.iew.exec_rate 2.192287 # Inst execution rate -system.cpu.iew.wb_sent 106761196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106424699 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53424049 # num instructions producing a value -system.cpu.iew.wb_consumers 103788661 # num instructions consuming a value +system.cpu.iew.exec_nop 80145 # number of nop insts executed +system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed +system.cpu.iew.exec_branches 14661458 # Number of branches executed +system.cpu.iew.exec_stores 21477017 # Number of stores executed +system.cpu.iew.exec_rate 2.193053 # Inst execution rate +system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53411369 # num instructions producing a value +system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.175471 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514739 # average fanout of values written-back +system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12825262 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37025 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 616891 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45721388 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201347 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.733819 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16264410 35.57% 35.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11914734 26.06% 61.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3626051 7.93% 69.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2926022 6.40% 75.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880797 4.11% 80.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1911030 4.18% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 689200 1.51% 85.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 582969 1.28% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5926175 12.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45721388 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929376 # Number of instructions committed -system.cpu.commit.committedOps 100648623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929626 # Number of instructions committed +system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869324 # Number of memory references committed -system.cpu.commit.loads 27310347 # Number of loads committed +system.cpu.commit.refs 47869424 # Number of memory references committed +system.cpu.commit.loads 27310397 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671866 # Number of branches committed +system.cpu.commit.branches 13671916 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91485735 # Number of committed integer instructions. +system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5926175 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153243799 # The number of ROB reads -system.cpu.rob.rob_writes 228884039 # The number of ROB writes -system.cpu.timesIdled 52429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1273281 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70923824 # Number of Instructions Simulated -system.cpu.committedOps 100643071 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70923824 # Number of Instructions Simulated -system.cpu.cpi 0.689758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.689758 # CPI: Total CPI of All Threads -system.cpu.ipc 1.449783 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.449783 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516242048 # number of integer regfile reads -system.cpu.int_regfile_writes 104369908 # number of integer regfile writes -system.cpu.fp_regfile_reads 886 # number of floating regfile reads -system.cpu.fp_regfile_writes 750 # number of floating regfile writes -system.cpu.misc_regfile_reads 146091713 # number of misc regfile reads -system.cpu.misc_regfile_writes 38318 # number of misc regfile writes -system.cpu.icache.replacements 30244 # number of replacements -system.cpu.icache.tagsinuse 1815.033473 # Cycle average of tags in use -system.cpu.icache.total_refs 12045499 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32282 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 373.133604 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 153192367 # The number of ROB reads +system.cpu.rob.rob_writes 228820850 # The number of ROB writes +system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924074 # Number of Instructions Simulated +system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated +system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads +system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516213591 # number of integer regfile reads +system.cpu.int_regfile_writes 104366681 # number of integer regfile writes +system.cpu.fp_regfile_reads 794 # number of floating regfile reads +system.cpu.fp_regfile_writes 662 # number of floating regfile writes +system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads +system.cpu.misc_regfile_writes 38418 # number of misc regfile writes +system.cpu.icache.replacements 30034 # number of replacements +system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use +system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.033473 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886247 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886247 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12045501 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12045501 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12045501 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12045501 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12045501 # number of overall hits -system.cpu.icache.overall_hits::total 12045501 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33638 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33638 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33638 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33638 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33638 # number of overall misses -system.cpu.icache.overall_misses::total 33638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406685000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406685000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406685000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406685000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406685000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12079139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12079139 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12079139 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12079139 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12079139 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002785 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002785 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002785 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002785 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002785 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12090.046971 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12090.046971 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12090.046971 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12090.046971 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits +system.cpu.icache.overall_hits::total 12025773 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses +system.cpu.icache.overall_misses::total 33450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1313 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1313 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1313 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1313 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1313 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32325 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32325 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32325 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32325 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32325 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 274223500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 274223500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274223500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 274223500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002676 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002676 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002676 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8483.325599 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8483.325599 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8483.325599 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158501 # number of replacements -system.cpu.dcache.tagsinuse 4071.855185 # Cycle average of tags in use -system.cpu.dcache.total_refs 44605412 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162597 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.331089 # Average number of references to valid blocks. +system.cpu.dcache.replacements 158627 # number of replacements +system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use +system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.855185 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994105 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26278291 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26278291 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18287500 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18287500 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20317 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20317 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19158 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19158 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44565791 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44565791 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44565791 # number of overall hits -system.cpu.dcache.overall_hits::total 44565791 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 106674 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 106674 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1562401 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1562401 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1669075 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1669075 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1669075 # number of overall misses -system.cpu.dcache.overall_misses::total 1669075 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2574319000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 63349260500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 629500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 65923579500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 65923579500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 65923579500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26384965 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26384965 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26277362 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26277362 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285328 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285328 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20388 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20388 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19208 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19208 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44562690 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44562690 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44562690 # number of overall hits +system.cpu.dcache.overall_hits::total 44562690 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 106921 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 106921 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1564573 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1564573 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1671494 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1671494 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1671494 # number of overall misses +system.cpu.dcache.overall_misses::total 1671494 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2586655500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63403235500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 586000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 65989891000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 65989891000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 65989891000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26384283 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26384283 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20360 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19158 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46234866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46234866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46234866 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46234866 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004043 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078711 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002112 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036100 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036100 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036100 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036100 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24132.581510 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24132.581510 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40546.095721 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40546.095721 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14639.534884 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39497.074427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39497.074427 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 202500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128059 # number of writebacks -system.cpu.dcache.writebacks::total 128059 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51068 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51068 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1455366 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1506434 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1506434 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1506434 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55606 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55606 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107035 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107035 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162641 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162641 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 982100000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3836030000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4818130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4818130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002107 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003518 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003518 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17661.763119 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35839.024618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29624.325969 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29624.325969 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks +system.cpu.dcache.writebacks::total 128131 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97988 # number of replacements -system.cpu.l2cache.tagsinuse 28616.670846 # Cycle average of tags in use -system.cpu.l2cache.total_refs 87010 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128775 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.675675 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 98022 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3994023000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4157964000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163941000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3994023000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4157964000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416346 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321544 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.840909 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.840909 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5133 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130595 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5133 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130595 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164656500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758645000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 923301500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1434000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1434000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164656500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4004770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4169427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164656500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4004770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4169427000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415637 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.322251 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807018 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807018 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955972 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955972 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.669971 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.158301 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771533 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.669971 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32088.667058 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32536.865762 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32455.800616 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31679.731407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31679.731407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32088.667058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31837.822541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31847.638597 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.670430 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.160056 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771016 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.670430 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.024547 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32769.426807 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32643.950643 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31173.913043 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31728.020447 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.024547 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31920.186989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31926.390750 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index def42a9fe..0d873282b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.996061 # Number of seconds simulated -sim_ticks 996061088500 # Number of ticks simulated -final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.996063 # Number of seconds simulated +sim_ticks 996062814500 # Number of ticks simulated +final_tick 996062814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139633 # Simulator instruction rate (inst/s) -host_op_rate 139633 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76428343 # Simulator tick rate (ticks/s) -host_mem_usage 218940 # Number of bytes of host memory used -host_seconds 13032.61 # Real time elapsed on the host +host_inst_rate 142352 # Simulator instruction rate (inst/s) +host_op_rate 142352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 77916645 # Simulator tick rate (ticks/s) +host_mem_usage 219096 # Number of bytes of host memory used +host_seconds 12783.70 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -24,32 +24,32 @@ system.physmem.num_reads::total 2150541 # Nu system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138123466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138178659 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67370273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67370273 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138123466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205548932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444620723 # DTB read hits +system.cpu.dtb.read_hits 444620890 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449517801 # DTB read accesses +system.cpu.dtb.read_accesses 449517968 # DTB read accesses system.cpu.dtb.write_hits 160920434 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 162621738 # DTB write accesses -system.cpu.dtb.data_hits 605541157 # DTB hits +system.cpu.dtb.data_hits 605541324 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612139539 # DTB accesses +system.cpu.dtb.data_accesses 612139706 # DTB accesses system.cpu.itb.fetch_hits 232151959 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1992122178 # number of cpu cycles simulated +system.cpu.numCycles 1992125630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups @@ -80,9 +80,9 @@ system.cpu.branch_predictor.RASInCorrect 6 # Nu system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 1669698372 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3045900989 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File @@ -93,16 +93,16 @@ system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed. +system.cpu.execution_unit.executions 1139625100 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1749884347 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed. -system.cpu.activity 79.160383 # Percentage of cycles cpu is active +system.cpu.timesIdled 7972692 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415154081 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576971549 # Number of cycles cpu stages are processed. +system.cpu.activity 79.160246 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,34 +114,34 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.094707 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads -system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.094707 # CPI: Total CPI of All Threads +system.cpu.ipc 0.913487 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.913487 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 801360547 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190765083 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.773594 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1059717687 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932407943 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.804676 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1018191600 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 48.889187 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1582470698 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 20.563710 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 969332524 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022793106 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.341797 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use +system.cpu.icache.tagsinuse 666.783134 # Cycle average of tags in use system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 666.783134 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits @@ -219,39 +219,39 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107309 # number of replacements -system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use -system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9107311 # number of replacements +system.cpu.dcache.tagsinuse 4082.354222 # Cycle average of tags in use +system.cpu.dcache.total_refs 595073825 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111407 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310860 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4082.354222 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595073835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595073835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595073835 # number of overall hits -system.cpu.dcache.overall_hits::total 595073835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2926102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2926102 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10250330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10250330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10250330 # number of overall misses -system.cpu.dcache.overall_misses::total 10250330 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 166496556500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 437271433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157802392 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157802392 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595073825 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595073825 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595073825 # number of overall hits +system.cpu.dcache.overall_hits::total 595073825 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324230 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324230 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2926110 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2926110 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10250340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10250340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10250340 # number of overall misses +system.cpu.dcache.overall_misses::total 10250340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 166497124500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130098294500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296595419000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296595419000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296595419000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -268,48 +268,48 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.372481 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.372481 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44461.176955 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44461.176955 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28935.178638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28935.178638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78626000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8150818500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14909 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5273.727279 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39101.656496 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks -system.cpu.dcache.writebacks::total 3389633 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3389635 # number of writebacks +system.cpu.dcache.writebacks::total 3389635 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1036985 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1138933 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1138933 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1138933 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111405 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111405 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111405 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71711487500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212649723000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212649723000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111407 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111407 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111407 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938792000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71755618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212694410500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212694410500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212694410500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,38 +318,38 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.440450 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37983.520678 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23343.750367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23343.750367 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2133758 # number of replacements -system.cpu.l2cache.tagsinuse 30551.127244 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448350 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 30551.128505 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8448354 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 2163449 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905038 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 184402684000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14423.839124 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.322166 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16092.965953 # Average occupied blocks per requestor +system.cpu.l2cache.avg_refs 3.905040 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 184403463000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14423.846214 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.322158 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16092.960133 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389633 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389633 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5860989 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860989 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389635 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389635 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 6961723 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 6961723 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 6961723 # number of overall hits -system.cpu.l2cache.overall_hits::total 6961723 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.data 6961725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6961725 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6961725 # number of overall hits +system.cpu.l2cache.overall_hits::total 6961725 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1360852 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 1361711 # number of ReadReq misses @@ -362,29 +362,29 @@ system.cpu.l2cache.overall_misses::cpu.inst 859 # system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71425674500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71471834500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41981087000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41981087000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71427566000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71473726000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42035467500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 42035467500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 113406761500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 113452921500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 113463033500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113509193500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 113452921500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 113463033500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113509193500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221839 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389633 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389635 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389635 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111405 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112264 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111407 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112266 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111405 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112264 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111407 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112266 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses @@ -397,21 +397,21 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52487.387313 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52488.175538 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53288.373287 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53288.373287 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52755.525935 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52781.692374 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3381000 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.310678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52781.692374 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3730000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 111 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 142 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26267.605634 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -429,16 +429,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54780311000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54816009000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32410594000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54782223000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54817921000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32465310500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32465310500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87190905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87226603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87247533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87283231500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87190905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87226603000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87247533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87283231500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses @@ -451,16 +451,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40255.827232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40256.648437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41156.282723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41156.282723 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40586.251129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40586.639129 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 24a60df2f..693f470b9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.621255 # Number of seconds simulated -sim_ticks 621254733000 # Number of ticks simulated -final_tick 621254733000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.621337 # Number of seconds simulated +sim_ticks 621337354500 # Number of ticks simulated +final_tick 621337354500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 206958 # Simulator instruction rate (inst/s) -host_op_rate 206958 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74061263 # Simulator tick rate (ticks/s) -host_mem_usage 219968 # Number of bytes of host memory used -host_seconds 8388.39 # Real time elapsed on the host +host_inst_rate 185902 # Simulator instruction rate (inst/s) +host_op_rate 185902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66535120 # Simulator tick rate (ticks/s) +host_mem_usage 220128 # Number of bytes of host memory used +host_seconds 9338.49 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138177216 # Number of bytes read from this memory -system.physmem.bytes_read::total 138239104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208512 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2159019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159986 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050133 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050133 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 99618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 222416359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 222515977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 99618 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 108181891 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 108181891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 99618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 222416359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 330697869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 62208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138182080 # Number of bytes read from this memory +system.physmem.bytes_read::total 138244288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67208384 # Number of bytes written to this memory +system.physmem.bytes_written::total 67208384 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 972 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2159095 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2160067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050131 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050131 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 100120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 222394612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 222494732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 108167300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 108167300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 100120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 222394612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 330662032 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 614267388 # DTB read hits -system.cpu.dtb.read_misses 10994218 # DTB read misses +system.cpu.dtb.read_hits 614254083 # DTB read hits +system.cpu.dtb.read_misses 10995703 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625261606 # DTB read accesses -system.cpu.dtb.write_hits 208720588 # DTB write hits -system.cpu.dtb.write_misses 6852950 # DTB write misses +system.cpu.dtb.read_accesses 625249786 # DTB read accesses +system.cpu.dtb.write_hits 208699163 # DTB write hits +system.cpu.dtb.write_misses 6860235 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 215573538 # DTB write accesses -system.cpu.dtb.data_hits 822987976 # DTB hits -system.cpu.dtb.data_misses 17847168 # DTB misses +system.cpu.dtb.write_accesses 215559398 # DTB write accesses +system.cpu.dtb.data_hits 822953246 # DTB hits +system.cpu.dtb.data_misses 17855938 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 840835144 # DTB accesses -system.cpu.itb.fetch_hits 402675877 # ITB hits -system.cpu.itb.fetch_misses 58 # ITB misses +system.cpu.dtb.data_accesses 840809184 # DTB accesses +system.cpu.itb.fetch_hits 402673269 # ITB hits +system.cpu.itb.fetch_misses 61 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402675935 # ITB accesses +system.cpu.itb.fetch_accesses 402673330 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,145 +67,145 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1242509467 # number of cpu cycles simulated +system.cpu.numCycles 1242674710 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 383372990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 295235565 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 19006052 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 268408458 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 264104025 # Number of BTB hits +system.cpu.BPredUnit.lookups 383387811 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 295251517 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 19004234 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 268604084 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 264111879 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25197943 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6076 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 414160425 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3172269212 # Number of instructions fetch has processed -system.cpu.fetch.Branches 383372990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 289301968 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 579083206 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 137694854 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132940581 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1360 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402675877 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10477889 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.562369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.158541 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25192938 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6291 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 414146940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3172273422 # Number of instructions fetch has processed +system.cpu.fetch.Branches 383387811 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 289304817 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 579090604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 137696439 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133107618 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1380 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 402673269 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10484478 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.562032 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.158458 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 658938796 53.23% 53.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43587849 3.52% 56.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22400320 1.81% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 41027424 3.31% 61.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127967453 10.34% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63937343 5.16% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40820174 3.30% 80.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30420264 2.46% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 208922379 16.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 659096036 53.23% 53.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43594264 3.52% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22394894 1.81% 58.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 41029945 3.31% 61.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 127979061 10.34% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63938505 5.16% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40814246 3.30% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30412222 2.46% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 208927467 16.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1238022002 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.308547 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.553115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 444879640 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117490931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 546452553 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17363359 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 111835519 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60534072 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 962 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3092225969 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2145 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 111835519 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 466447238 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 65379308 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540801711 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53552759 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3009893694 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 588891 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2795172 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 47908313 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2251120190 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3888621958 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3887220740 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1401218 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1238186640 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.308518 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.552779 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 444874368 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117661314 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 546409633 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17402131 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 111839194 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60535765 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 960 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3092199728 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2107 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 111839194 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 466426212 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 65454708 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5539 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540814331 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53646656 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3009948527 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 590628 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2809331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 47992017 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2251177447 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3888711604 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3887318453 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1393151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 874917227 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 215 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112891088 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679356489 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 252372715 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62271668 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36485662 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2703868851 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 183 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2499086402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3468008 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 959949757 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 407382923 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1238022002 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.960549 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 874974484 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 208 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 207 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112977902 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679363507 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 252361148 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 62396219 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36704407 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2703896552 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2499071963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3469199 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 959964040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 407445563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1238186640 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.018332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.960312 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 396920026 32.06% 32.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 203237579 16.42% 48.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185771607 15.01% 63.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153281748 12.38% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136530779 11.03% 86.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 79975547 6.46% 93.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 62882805 5.08% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14212604 1.15% 99.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5209307 0.42% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 396950099 32.06% 32.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203265879 16.42% 48.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185984424 15.02% 63.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153264847 12.38% 75.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136492690 11.02% 86.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79936535 6.46% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62863067 5.08% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14221934 1.15% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5207165 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1238022002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1238186640 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1901972 10.18% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12247269 65.56% 75.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4530432 24.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1904668 10.20% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12253005 65.59% 75.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4524321 24.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1633606519 65.37% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1633622343 65.37% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 295 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 168 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 36 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 285 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 166 0.00% 65.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 37 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.37% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.37% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 642839630 25.72% 91.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 222639616 8.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 642829515 25.72% 91.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 222619482 8.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2499086402 # Type of FU issued -system.cpu.iq.rate 2.011322 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18679673 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007475 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6256352202 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3662566047 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2395383662 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1990285 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1357397 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 872084 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2516787863 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 978212 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57513083 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2499071963 # Type of FU issued +system.cpu.iq.rate 2.011043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18681994 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007476 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6256498920 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3662616880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2395384352 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1982839 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1348326 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869815 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2516779289 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974668 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57504336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234760826 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 254713 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 106352 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 91644213 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 234767844 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 254077 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 105937 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 91632646 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 271 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 267185 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 220 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 267187 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 111835519 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23640124 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1166146 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2847163562 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17865598 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679356489 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 252372715 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 183 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 265739 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14899 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 106352 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13291147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8879247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22170394 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2446896238 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625263073 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 52190164 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 111839194 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23661056 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1167024 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2847195647 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17872608 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679363507 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 252361148 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 180 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 266250 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15108 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 105937 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13288388 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8880688 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22169076 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2446901289 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625251329 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 52170674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 143294528 # number of nop insts executed -system.cpu.iew.exec_refs 840836661 # number of memory reference insts executed -system.cpu.iew.exec_branches 299907540 # Number of branches executed -system.cpu.iew.exec_stores 215573588 # Number of stores executed -system.cpu.iew.exec_rate 1.969318 # Inst execution rate -system.cpu.iew.wb_sent 2424978134 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2396255746 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1371174091 # num instructions producing a value -system.cpu.iew.wb_consumers 1736703047 # num instructions consuming a value +system.cpu.iew.exec_nop 143298915 # number of nop insts executed +system.cpu.iew.exec_refs 840810767 # number of memory reference insts executed +system.cpu.iew.exec_branches 299911480 # Number of branches executed +system.cpu.iew.exec_stores 215559438 # Number of stores executed +system.cpu.iew.exec_rate 1.969060 # Inst execution rate +system.cpu.iew.wb_sent 2424991603 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2396254167 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1371180261 # num instructions producing a value +system.cpu.iew.wb_consumers 1736709964 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.928561 # insts written-back per cycle +system.cpu.iew.wb_rate 1.928304 # insts written-back per cycle system.cpu.iew.wb_fanout 0.789527 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 793041487 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 793091861 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 19005172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1126186483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.615878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.496171 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 19003362 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1126347446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.615647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.496030 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 601057240 53.37% 53.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181431262 16.11% 69.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 90818871 8.06% 77.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53582935 4.76% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36462614 3.24% 85.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28190767 2.50% 88.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22584019 2.01% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22816288 2.03% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89242487 7.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 601147369 53.37% 53.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181479999 16.11% 69.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90892282 8.07% 77.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53587955 4.76% 82.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36442488 3.24% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28128451 2.50% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22594945 2.01% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22821835 2.03% 92.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 89252122 7.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1126186483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1126347446 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89242487 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 89252122 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3563986409 # The number of ROB reads -system.cpu.rob.rob_writes 5337596119 # The number of ROB writes -system.cpu.timesIdled 386257 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4487465 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3564188111 # The number of ROB reads +system.cpu.rob.rob_writes 5337700893 # The number of ROB writes +system.cpu.timesIdled 386272 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4488070 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.715713 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.715713 # CPI: Total CPI of All Threads -system.cpu.ipc 1.397208 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.397208 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3289961910 # number of integer regfile reads -system.cpu.int_regfile_writes 1921843103 # number of integer regfile writes -system.cpu.fp_regfile_reads 52840 # number of floating regfile reads -system.cpu.fp_regfile_writes 576 # number of floating regfile writes +system.cpu.cpi 0.715808 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.715808 # CPI: Total CPI of All Threads +system.cpu.ipc 1.397022 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.397022 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3289961218 # number of integer regfile reads +system.cpu.int_regfile_writes 1921862672 # number of integer regfile writes +system.cpu.fp_regfile_reads 50916 # number of floating regfile reads +system.cpu.fp_regfile_writes 565 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 769.288412 # Cycle average of tags in use -system.cpu.icache.total_refs 402674417 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 967 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 416416.149948 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 773.343215 # Cycle average of tags in use +system.cpu.icache.total_refs 402671818 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 414271.417695 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 769.288412 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.375629 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.375629 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402674417 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402674417 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402674417 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402674417 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402674417 # number of overall hits -system.cpu.icache.overall_hits::total 402674417 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1460 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1460 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1460 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1460 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1460 # number of overall misses -system.cpu.icache.overall_misses::total 1460 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51984000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51984000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51984000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51984000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51984000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402675877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402675877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402675877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402675877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402675877 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 773.343215 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.377609 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.377609 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 402671818 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 402671818 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 402671818 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 402671818 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 402671818 # number of overall hits +system.cpu.icache.overall_hits::total 402671818 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1451 # number of overall misses +system.cpu.icache.overall_misses::total 1451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 52415500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 52415500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 52415500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 52415500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 52415500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 402673269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 402673269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 402673269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 402673269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 402673269 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35605.479452 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35605.479452 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35605.479452 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35605.479452 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36123.707788 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36123.707788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36123.707788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36123.707788 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,301 +388,301 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 493 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 493 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 493 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 493 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 493 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 493 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 967 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 967 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 967 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 967 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 967 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 967 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36487500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36487500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36487500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36487500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 479 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 479 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 479 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 479 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 479 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 479 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36902500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36902500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36902500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36902500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36902500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36902500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37732.678387 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37732.678387 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37732.678387 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37965.534979 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37965.534979 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37965.534979 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9177386 # number of replacements -system.cpu.dcache.tagsinuse 4086.021231 # Cycle average of tags in use -system.cpu.dcache.total_refs 702056589 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9181482 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.464408 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9177741 # number of replacements +system.cpu.dcache.tagsinuse 4086.022558 # Cycle average of tags in use +system.cpu.dcache.total_refs 702049039 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9181837 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.460630 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5710472000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4086.021231 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4086.022558 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 546233301 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 546233301 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155823284 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155823284 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 702056585 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 702056585 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 702056585 # number of overall hits -system.cpu.dcache.overall_hits::total 702056585 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10361176 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10361176 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4905218 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4905218 # number of WriteReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 546225954 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 546225954 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155823082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155823082 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 702049036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 702049036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 702049036 # number of overall hits +system.cpu.dcache.overall_hits::total 702049036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10364055 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10364055 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4905420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4905420 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15266394 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15266394 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15266394 # number of overall misses -system.cpu.dcache.overall_misses::total 15266394 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 211386484000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 166231514528 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 71000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377617998528 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377617998528 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377617998528 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 556594477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 556594477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15269475 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15269475 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15269475 # number of overall misses +system.cpu.dcache.overall_misses::total 15269475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 211607642000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 166442600009 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 65000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 378050242009 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 378050242009 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 378050242009 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 556590009 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 556590009 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 717322979 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 717322979 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 717322979 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 717322979 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.018615 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20401.784894 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20401.784894 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33888.710864 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33888.710864 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24735.245175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.245175 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24735.245175 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 705051055 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1696782500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 102430 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65119 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6883.247633 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26056.642455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 717318511 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 717318511 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 717318511 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 717318511 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.018621 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030520 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.400000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021287 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021287 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021287 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021287 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20417.456488 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20417.456488 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33930.346435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33930.346435 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 32500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 32500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24758.561903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24758.561903 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 705064541 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1696790500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 102448 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65121 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6882.169891 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26055.965050 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3417165 # number of writebacks -system.cpu.dcache.writebacks::total 3417165 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3063278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021635 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3021635 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3417249 # number of writebacks +system.cpu.dcache.writebacks::total 3417249 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3065881 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3021758 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3021758 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6084913 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6084913 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6084913 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6084913 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7297898 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7297898 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883583 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883583 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 6087639 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6087639 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6087639 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6087639 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7298174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7298174 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883662 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883662 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9181481 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9181481 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9181481 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9181481 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97194400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 97194400500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53824994530 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53824994530 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9181836 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9181836 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9181836 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 97342451000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53846535513 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 53846535513 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151019395030 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151019395030 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151019395030 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151019395030 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151188986513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151188986513 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151188986513 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151188986513 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013112 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012800 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012800 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012800 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13318.136332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13318.136332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28575.854916 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28575.854916 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13337.918636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13337.918636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28586.092151 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28586.092151 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16448.260910 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16448.260910 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16448.260910 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16448.260910 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16466.095290 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16466.095290 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143567 # number of replacements -system.cpu.l2cache.tagsinuse 30910.999406 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8542221 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173263 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930597 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 109501601000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14438.768585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 29.814922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16442.415898 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000910 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943329 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5921293 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5921293 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3417165 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3417165 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101170 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101170 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7022463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7022463 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7022463 # number of overall hits -system.cpu.l2cache.overall_hits::total 7022463 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376593 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377560 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782426 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782426 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 967 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2159019 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159986 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 967 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2159019 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159986 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35122000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48976797500 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188629 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415389 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415389 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188748 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415341 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235149 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235230 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33157.704240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32715.872085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32716.069888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235229 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33409.979424 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32513.735092 # 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Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 13d5bc965..7bf311873 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479151 # Number of seconds simulated -sim_ticks 479150606000 # Number of ticks simulated -final_tick 479150606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.479223 # Number of seconds simulated +sim_ticks 479223482000 # Number of ticks simulated +final_tick 479223482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194711 # Simulator instruction rate (inst/s) -host_op_rate 217215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60402792 # Simulator tick rate (ticks/s) -host_mem_usage 234724 # Number of bytes of host memory used -host_seconds 7932.59 # Real time elapsed on the host +host_inst_rate 194014 # Simulator instruction rate (inst/s) +host_op_rate 216437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60195599 # Simulator tick rate (ticks/s) +host_mem_usage 234776 # Number of bytes of host memory used +host_seconds 7961.11 # Real time elapsed on the host sim_insts 1544563028 # Number of instructions simulated sim_ops 1723073840 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156296384 # Number of bytes read from this memory -system.physmem.bytes_read::total 156344896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71934976 # Number of bytes written to this memory -system.physmem.bytes_written::total 71934976 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2442889 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1123984 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1123984 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326194691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326295937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101246 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150130199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150130199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326194691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476426136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156331072 # Number of bytes read from this memory +system.physmem.bytes_read::total 156379520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71949824 # Number of bytes written to this memory +system.physmem.bytes_written::total 71949824 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2442673 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124216 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124216 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 101097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326217470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 326318567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 150138352 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 150138352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326217470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 476456920 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958301213 # number of cpu cycles simulated +system.cpu.numCycles 958446965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302333500 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248015603 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16105989 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 168718741 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157776197 # Number of BTB hits +system.cpu.BPredUnit.lookups 302424004 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248121310 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16111337 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 166375993 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 157791713 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18362417 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295110918 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2170236667 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302333500 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176138614 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431684517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85621855 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155290774 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 58 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285908690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5538082 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.537566 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.220819 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 18325977 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 236 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295072409 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2170601008 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302424004 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176117690 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 431730569 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85674794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155376778 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285867319 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5539236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.537748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.221191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519133170 54.60% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23531871 2.47% 57.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38842821 4.09% 61.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47928811 5.04% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41274787 4.34% 70.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47187627 4.96% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39143273 4.12% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18340446 1.93% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175434805 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519225507 54.60% 54.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23584051 2.48% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38809935 4.08% 61.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47901977 5.04% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 41256448 4.34% 70.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47147738 4.96% 75.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39135623 4.12% 79.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18358633 1.93% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175535995 18.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950817611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315489 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264671 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327140938 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132753088 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402950990 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19241929 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68730666 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46279846 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2359084469 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2481 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68730666 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349892865 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63780880 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14141 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397813217 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70585842 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300380626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28739 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5556251 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56445912 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275326533 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10618275091 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10618272387 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2704 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 950955907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315535 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.264706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327119471 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 132830999 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402990203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19239879 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68775355 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46282380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 697 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2359573845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2428 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68775355 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 349888082 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63823546 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14916 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397833782 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70620226 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2300864153 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28671 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5550118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56484879 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2275806889 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10620956453 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10620952653 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3800 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569006595 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155601466 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627528670 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219567806 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87006993 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68089228 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199559403 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020307102 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5002319 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472139724 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1101721580 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1355 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950817611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124810 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914497 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 569486951 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5312 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5309 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155780896 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 627644360 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219694213 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87145300 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68089448 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2199982180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1528 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020409598 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4999430 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 472571343 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1103696346 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1357 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 950955907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.124609 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914480 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272456432 28.65% 28.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 148972541 15.67% 44.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161045064 16.94% 61.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117808406 12.39% 73.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124487858 13.09% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74416152 7.83% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38351621 4.03% 98.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10558999 1.11% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2720538 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272613444 28.67% 28.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 148967706 15.67% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 160979511 16.93% 61.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117706760 12.38% 73.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124599704 13.10% 86.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74507798 7.84% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38341084 4.03% 98.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10540920 1.11% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2698980 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950817611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 950955907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 866703 3.46% 3.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4868 0.02% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18978969 75.82% 79.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5181359 20.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 849524 3.40% 3.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4750 0.02% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18987433 76.01% 79.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5139841 20.57% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236552318 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 932322 0.05% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236587791 61.20% 61.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 931138 0.05% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued @@ -233,90 +233,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 41 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 12 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588904292 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193918099 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588900248 29.15% 90.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193990319 9.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020307102 # Type of FU issued -system.cpu.iq.rate 2.108217 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25031899 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012390 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021465735 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2671886632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961215820 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045338849 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63654285 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020409598 # Type of FU issued +system.cpu.iq.rate 2.108004 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24981548 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012365 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021755668 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2672741554 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1961287360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 160 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2045390937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63645440 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141601900 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 294123 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189203 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44720760 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 141717590 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 292895 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189897 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 44847167 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1137177 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 1141778 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68730666 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28026748 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485770 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199569564 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5556141 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627528670 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219567806 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1463 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343326 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56332 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189203 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8602483 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10215552 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18818035 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990553449 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574287819 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29753653 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68775355 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28059003 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1485687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2199992043 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5558489 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 627644360 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219694213 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343629 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56102 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189897 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8602375 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10226115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18828490 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1990642810 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574277068 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29766788 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8635 # number of nop insts executed -system.cpu.iew.exec_refs 765252053 # number of memory reference insts executed -system.cpu.iew.exec_branches 238421113 # Number of branches executed -system.cpu.iew.exec_stores 190964234 # Number of stores executed -system.cpu.iew.exec_rate 2.077169 # Inst execution rate -system.cpu.iew.wb_sent 1970075771 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961215932 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296581898 # num instructions producing a value -system.cpu.iew.wb_consumers 2068899277 # num instructions consuming a value +system.cpu.iew.exec_nop 8335 # number of nop insts executed +system.cpu.iew.exec_refs 765299887 # number of memory reference insts executed +system.cpu.iew.exec_branches 238409980 # Number of branches executed +system.cpu.iew.exec_stores 191022819 # Number of stores executed +system.cpu.iew.exec_rate 2.076946 # Inst execution rate +system.cpu.iew.wb_sent 1970153008 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1961287520 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296694675 # num instructions producing a value +system.cpu.iew.wb_consumers 2069023421 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046555 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626701 # average fanout of values written-back +system.cpu.iew.wb_rate 2.046318 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626718 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476570852 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 476993558 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16105557 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882086946 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953406 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727739 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16110924 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882180553 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953199 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727625 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391458685 44.38% 44.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194911052 22.10% 66.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73858259 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35176751 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19156374 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30712442 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19230333 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11318069 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106264981 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391561558 44.39% 44.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194873977 22.09% 66.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73868669 8.37% 74.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35208101 3.99% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19136047 2.17% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30738627 3.48% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19218397 2.18% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11310881 1.28% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106264296 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882086946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 882180553 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563046 # Number of instructions committed system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -327,70 +327,70 @@ system.cpu.commit.branches 213462364 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106264981 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106264296 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975466076 # The number of ROB reads -system.cpu.rob.rob_writes 4468185114 # The number of ROB writes -system.cpu.timesIdled 802459 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7483602 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2975983074 # The number of ROB reads +system.cpu.rob.rob_writes 4469074827 # The number of ROB writes +system.cpu.timesIdled 802305 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7491058 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563028 # Number of Instructions Simulated system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated -system.cpu.cpi 0.620435 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620435 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611772 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611772 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9971004084 # number of integer regfile reads -system.cpu.int_regfile_writes 1941069131 # number of integer regfile writes -system.cpu.fp_regfile_reads 114 # number of floating regfile reads -system.cpu.fp_regfile_writes 123 # number of floating regfile writes -system.cpu.misc_regfile_reads 2910834876 # number of misc regfile reads +system.cpu.cpi 0.620530 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620530 # CPI: Total CPI of All Threads +system.cpu.ipc 1.611527 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.611527 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9971495260 # number of integer regfile reads +system.cpu.int_regfile_writes 1941105565 # number of integer regfile writes +system.cpu.fp_regfile_reads 174 # number of floating regfile reads +system.cpu.fp_regfile_writes 178 # number of floating regfile writes +system.cpu.misc_regfile_reads 2911260843 # number of misc regfile reads system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 24 # number of replacements -system.cpu.icache.tagsinuse 634.471646 # Cycle average of tags in use -system.cpu.icache.total_refs 285907562 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 789 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 362366.998733 # Average number of references to valid blocks. +system.cpu.icache.replacements 26 # number of replacements +system.cpu.icache.tagsinuse 632.958434 # Cycle average of tags in use +system.cpu.icache.total_refs 285866178 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 790 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361855.921519 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 634.471646 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.309801 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.309801 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285907562 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285907562 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285907562 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285907562 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285907562 # number of overall hits -system.cpu.icache.overall_hits::total 285907562 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1128 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1128 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1128 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1128 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1128 # number of overall misses -system.cpu.icache.overall_misses::total 1128 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40115500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40115500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40115500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40115500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40115500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285908690 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285908690 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285908690 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285908690 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285908690 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 632.958434 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.309062 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.309062 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285866178 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285866178 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285866178 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285866178 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285866178 # number of overall hits +system.cpu.icache.overall_hits::total 285866178 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses +system.cpu.icache.overall_misses::total 1141 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40467500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28839000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28839000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.499366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36505.063291 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36505.063291 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36505.063291 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 258868265000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 196333546730 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 196333546730 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 454885493493 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 454885493493 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 454885493493 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 505250585 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 505250585 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 455201811730 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 455201811730 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 455201811730 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 505245364 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 505245364 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 87 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 87 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 89 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 89 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 677836632 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 677836632 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 677836632 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 677836632 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021351 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021351 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 677831411 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677831411 # 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miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023573 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033708 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023576 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023576 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023576 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023576 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23993.859729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23993.859729 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37819.107373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37819.107373 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28468.211402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2516165984 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 147500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 424894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5921.867534 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28485.144620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2522668245 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 141500 # 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number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3474615 # number of writebacks +system.cpu.dcache.writebacks::total 3474615 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3059553 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297512 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3297512 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6356757 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6356757 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6356757 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91432769312 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215694149312 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215694149312 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015295 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015295 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6357065 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6357065 # 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average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22416.861982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22416.861982 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014197 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014197 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16100.450941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16100.450941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48332.672803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48332.672803 # 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average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39295.413239 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39295.413239 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37120.096524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37120.096524 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 30034731 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 2976 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3559 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7834.757392 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8439.092723 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1123984 # number of writebacks -system.cpu.l2cache.writebacks::total 1123984 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1124216 # number of writebacks +system.cpu.l2cache.writebacks::total 1124216 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -658,50 +658,50 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830788 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 830788 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442131 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2442889 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442131 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2442889 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25025500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52778176000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52803201500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29830819408 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29830819408 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25025500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82608995408 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82634020908 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25025500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82608995408 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82634020908 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208584 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438655 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33015.171504 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32754.153523 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32754.276252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35906.656581 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35906.656581 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611893 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1612650 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830780 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2442673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2442673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443430 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25045000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52994170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53019215500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30019129886 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25045000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83013300386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83038345386 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25045000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83013300386 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83038345386 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208541 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208618 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253888 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253888 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33084.544254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32876.977876 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32877.075311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36133.669426 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |