diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
| commit | d8f732273ecda73122ad3ba184e358ed265fa875 (patch) | |
| tree | 6ef605febd4e2299d75d76897386ff4ad7288fec /tests/long/se | |
| parent | 6fac40ceb03d4ab5b13affac3927cd876947cc78 (diff) | |
| download | gem5-d8f732273ecda73122ad3ba184e358ed265fa875.tar.xz | |
stats: Update stats for clean eviction addition
Diffstat (limited to 'tests/long/se')
| -rw-r--r-- | tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1407 | ||||
| -rw-r--r-- | tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1595 | ||||
| -rw-r--r-- | tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1144 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1630 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1632 | ||||
| -rw-r--r-- | tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1595 | ||||
| -rw-r--r-- | tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1087 |
7 files changed, 5043 insertions, 5047 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 37d15d84b..6f66b7dfa 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058174 # Number of seconds simulated -sim_ticks 58174017500 # Number of ticks simulated -final_tick 58174017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058182 # Number of seconds simulated +sim_ticks 58182114500 # Number of ticks simulated +final_tick 58182114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129950 # Simulator instruction rate (inst/s) -host_op_rate 130597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83449704 # Simulator tick rate (ticks/s) -host_mem_usage 446256 # Number of bytes of host memory used -host_seconds 697.11 # Real time elapsed on the host +host_inst_rate 128679 # Simulator instruction rate (inst/s) +host_op_rate 129320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82645168 # Simulator tick rate (ticks/s) +host_mem_usage 446228 # Number of bytes of host memory used +host_seconds 704.00 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 49984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 930560 # Number of bytes read from this memory -system.physmem.bytes_read::total 1025024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 26560 # Number of bytes written to this memory -system.physmem.bytes_written::total 26560 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14540 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16016 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 415 # Number of write requests responded to by this memory -system.physmem.num_writes::total 415 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 764603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 859215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15996145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17619962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 764603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 764603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 456561 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 456561 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 456561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 764603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 859215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15996145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18076524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16016 # Number of read requests accepted -system.physmem.writeReqs 415 # Number of write requests accepted -system.physmem.readBursts 16016 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 415 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1011776 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 13248 # Total number of bytes read from write queue -system.physmem.bytesWritten 25088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1025024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 26560 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 207 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 51456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 933184 # Number of bytes read from this memory +system.physmem.bytes_read::total 1028928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 27456 # Number of bytes written to this memory +system.physmem.bytes_written::total 27456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14581 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16077 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 429 # Number of write requests responded to by this memory +system.physmem.num_writes::total 429 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 761196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 884395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 16039018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17684610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 761196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 761196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 471898 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 471898 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 471898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 761196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 884395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 16039018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18156508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16077 # Number of read requests accepted +system.physmem.writeReqs 429 # Number of write requests accepted +system.physmem.readBursts 16077 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 429 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1014080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 14848 # Total number of bytes read from write queue +system.physmem.bytesWritten 26048 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1028928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 27456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 232 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1014 # Per bank write bursts +system.physmem.perBankRdBursts::0 1011 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts system.physmem.perBankRdBursts::2 957 # Per bank write bursts -system.physmem.perBankRdBursts::3 1028 # Per bank write bursts -system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1144 # Per bank write bursts -system.physmem.perBankRdBursts::6 1126 # Per bank write bursts -system.physmem.perBankRdBursts::7 1093 # Per bank write bursts -system.physmem.perBankRdBursts::8 1040 # Per bank write bursts +system.physmem.perBankRdBursts::3 1029 # Per bank write bursts +system.physmem.perBankRdBursts::4 1060 # Per bank write bursts +system.physmem.perBankRdBursts::5 1137 # Per bank write bursts +system.physmem.perBankRdBursts::6 1146 # Per bank write bursts +system.physmem.perBankRdBursts::7 1099 # Per bank write bursts +system.physmem.perBankRdBursts::8 1049 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 938 # Per bank write bursts -system.physmem.perBankRdBursts::11 903 # Per bank write bursts -system.physmem.perBankRdBursts::12 912 # Per bank write bursts +system.physmem.perBankRdBursts::10 940 # Per bank write bursts +system.physmem.perBankRdBursts::11 901 # Per bank write bursts +system.physmem.perBankRdBursts::12 907 # Per bank write bursts system.physmem.perBankRdBursts::13 888 # Per bank write bursts -system.physmem.perBankRdBursts::14 938 # Per bank write bursts -system.physmem.perBankRdBursts::15 925 # Per bank write bursts -system.physmem.perBankWrBursts::0 43 # Per bank write bursts +system.physmem.perBankRdBursts::14 960 # Per bank write bursts +system.physmem.perBankRdBursts::15 923 # Per bank write bursts +system.physmem.perBankWrBursts::0 29 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 7 # Per bank write bursts -system.physmem.perBankWrBursts::3 6 # Per bank write bursts -system.physmem.perBankWrBursts::4 10 # Per bank write bursts -system.physmem.perBankWrBursts::5 44 # Per bank write bursts -system.physmem.perBankWrBursts::6 74 # Per bank write bursts -system.physmem.perBankWrBursts::7 25 # Per bank write bursts -system.physmem.perBankWrBursts::8 45 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 4 # Per bank write bursts +system.physmem.perBankWrBursts::5 30 # Per bank write bursts +system.physmem.perBankWrBursts::6 102 # Per bank write bursts +system.physmem.perBankWrBursts::7 27 # Per bank write bursts +system.physmem.perBankWrBursts::8 34 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 10 # Per bank write bursts +system.physmem.perBankWrBursts::10 11 # Per bank write bursts system.physmem.perBankWrBursts::11 5 # Per bank write bursts -system.physmem.perBankWrBursts::12 11 # Per bank write bursts -system.physmem.perBankWrBursts::13 32 # Per bank write bursts -system.physmem.perBankWrBursts::14 48 # Per bank write bursts -system.physmem.perBankWrBursts::15 32 # Per bank write bursts +system.physmem.perBankWrBursts::12 6 # Per bank write bursts +system.physmem.perBankWrBursts::13 38 # Per bank write bursts +system.physmem.perBankWrBursts::14 82 # Per bank write bursts +system.physmem.perBankWrBursts::15 24 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58173860500 # Total gap between requests +system.physmem.totGap 58181957500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16016 # Read request sizes (log2) +system.physmem.readPktSize::6 16077 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 415 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 291 # What read queue length does an incoming req see +system.physmem.writePktSize::6 429 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,92 +197,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.107772 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 304.077638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 432.159932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 590 30.57% 30.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 221 11.45% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97 5.03% 47.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 3.58% 50.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 71 3.68% 54.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 49 2.54% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 51 2.64% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 42 2.18% 61.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 740 38.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1930 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 717.636364 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.597036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3209.686449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 21 95.45% 95.45% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 4.55% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 22 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.818182 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.808292 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.588490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 9.09% 9.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20 90.91% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 22 # Writes before turning the bus around for reads -system.physmem.totQLat 169690298 # Total ticks spent queuing -system.physmem.totMemAccLat 466109048 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79045000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10733.78 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 535.822406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 300.454496 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 434.844935 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 623 32.16% 32.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 199 10.27% 42.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 5.11% 47.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 70 3.61% 51.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 49 2.53% 53.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 51 2.63% 56.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 51 2.63% 58.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 2.43% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 38.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1937 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 687.695652 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 31.373989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3139.186163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.695652 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.676543 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.822125 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4 17.39% 17.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18 78.26% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 4.35% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads +system.physmem.totQLat 162696744 # Total ticks spent queuing +system.physmem.totMemAccLat 459790494 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10268.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29483.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29018.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.68 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing -system.physmem.avgWrQLen 17.30 # Average write queue length when enqueuing -system.physmem.readRowHits 14150 # Number of row buffer hits during reads -system.physmem.writeRowHits 110 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.83 # Row buffer hit rate for writes -system.physmem.avgGap 3540494.22 # Average gap between requests -system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7832160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4273500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64506000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1289520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2476215945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32730681000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39084249885 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.881619 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54439969881 # Time in different power states -system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states +system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing +system.physmem.avgWrQLen 18.75 # Average write queue length when enqueuing +system.physmem.readRowHits 14165 # Number of row buffer hits during reads +system.physmem.writeRowHits 138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.47 # Row buffer hit rate for writes +system.physmem.avgGap 3524897.46 # Average gap between requests +system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7749000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4228125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64591800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1302480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2489657400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32723562000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39091051125 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.908601 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54427806081 # Time in different power states +system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1788917619 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1808607669 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6667920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3638250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58507800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1146960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2448182205 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32755263750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39072858645 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.685955 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54482617084 # Time in different power states -system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states +system.physmem_1.actEnergy 6811560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3716625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58687200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1211760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2472306885 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32738773500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39081467850 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.744040 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54453180249 # Time in different power states +system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1747288416 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1783438751 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257086 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279263 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837830 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842064 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784394 # Number of BTB hits +system.cpu.branchPred.lookups 28257673 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279792 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837861 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842586 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784928 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513007 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513130 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75759 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -402,93 +403,93 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116348036 # number of cpu cycles simulated +system.cpu.numCycles 116364230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748817 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134985012 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257086 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860154 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114705506 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679063 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1007 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 831 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301197 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116295692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748840 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134987137 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257673 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860687 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114722877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32301983 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116313064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165803 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319035 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58725363 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13942075 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230802 7.94% 70.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34397452 29.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58742008 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13941997 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9231022 7.94% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398037 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116295692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242867 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160183 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64036145 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034290 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827292 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101248 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114428571 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996975 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827292 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15280810 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49891272 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109349 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35424705 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14762264 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110897410 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415598 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131669 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144033 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526935 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 476507 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129954934 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483266147 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119472382 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116313064 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64052748 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33035096 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558012 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101304 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114430189 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996961 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15280915 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49896712 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425336 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14773354 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898724 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415582 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11131047 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1144428 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527040 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 487812 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483272365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119474128 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22642015 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21506426 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812625 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349337 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517439 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253975 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109689181 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21506605 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812984 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349507 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 517744 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 254125 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109690412 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074699 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18656398 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41685630 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101387626 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1074735 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18657629 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41690294 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116295692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871809 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116313064 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989298 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54655211 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31361654 26.97% 73.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008607 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072409 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197497 1.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 314 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54672209 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31362113 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22008866 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7072036 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197527 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116295692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116313064 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9793566 48.69% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9793385 48.69% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available @@ -511,18 +512,18 @@ system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # at system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 14 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9616917 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703878 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9616432 47.81% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 703828 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71983899 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984128 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10709 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -547,88 +548,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 53 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343332 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049532 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343025 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049584 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387653 # Type of FU issued -system.cpu.iq.rate 0.871417 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20114424 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198391 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340259668 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128354519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625011 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101387626 # Type of FU issued +system.cpu.iq.rate 0.871295 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20113709 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198384 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340276307 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128356979 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99625202 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 453 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 114 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501841 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121501099 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290489 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 290480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336714 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4337073 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1340 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604493 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1343 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604663 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130818 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7562 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130598 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827292 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8117300 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684188 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109710095 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8118752 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684481 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109711326 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812625 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349337 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812984 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349507 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178987 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342189 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1340 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436578 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412874 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126762 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806670 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260891 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 179113 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342349 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1343 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436660 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849532 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100126680 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806374 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1260946 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28724538 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624131 # Number of branches executed -system.cpu.iew.exec_stores 4917868 # Number of stores executed -system.cpu.iew.exec_rate 0.860580 # Inst execution rate -system.cpu.iew.wb_sent 99709725 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625125 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703453 # num instructions producing a value -system.cpu.iew.wb_consumers 95545682 # num instructions consuming a value +system.cpu.iew.exec_refs 28724279 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624229 # Number of branches executed +system.cpu.iew.exec_stores 4917905 # Number of stores executed +system.cpu.iew.exec_rate 0.860459 # Inst execution rate +system.cpu.iew.wb_sent 99709898 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99625314 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703303 # num instructions producing a value +system.cpu.iew.wb_consumers 95544285 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856268 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624868 # average fanout of values written-back +system.cpu.iew.wb_rate 0.856151 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17384546 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17385621 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825591 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113603530 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801504 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.738080 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825623 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113620717 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801382 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737978 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77180399 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18615023 16.39% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7150693 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466326 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641860 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544762 0.48% 95.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 180030 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120085 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77197638 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18614899 16.38% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7150727 6.29% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3466583 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1641577 1.44% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 544810 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704355 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 179975 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120153 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113603530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113620717 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,78 +675,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120085 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217915896 # The number of ROB reads -system.cpu.rob.rob_writes 219569120 # The number of ROB writes -system.cpu.timesIdled 587 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52344 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120153 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217934090 # The number of ROB reads +system.cpu.rob.rob_writes 219571457 # The number of ROB writes +system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51166 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284339 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778610 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778610 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111439 # number of integer regfile reads -system.cpu.int_regfile_writes 58700930 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads -system.cpu.fp_regfile_writes 95 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063438 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693153 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414947 # number of misc regfile reads +system.cpu.cpi 1.284518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284518 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778502 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778502 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111423 # number of integer regfile reads +system.cpu.int_regfile_writes 58700979 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 92 # number of floating regfile writes +system.cpu.cc_regfile_reads 369063033 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693305 # number of cc regfile writes +system.cpu.misc_regfile_reads 28414934 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470195 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.789215 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18252015 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336317 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35049500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.789215 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999588 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999588 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470204 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.787652 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18251843 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470716 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336280 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.787652 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908703 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908703 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889937 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889937 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353797 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353797 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61908596 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61908596 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13889769 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13889769 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353793 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353793 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243734 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243734 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244256 # number of overall hits -system.cpu.dcache.overall_hits::total 18244256 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585777 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585777 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381184 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381184 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18243562 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18243562 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18244084 # number of overall hits +system.cpu.dcache.overall_hits::total 18244084 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585887 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585887 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381188 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381188 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9966961 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9966961 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9966968 # number of overall misses -system.cpu.dcache.overall_misses::total 9966968 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88717689000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88717689000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3954782792 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3954782792 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967075 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967075 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967082 # number of overall misses +system.cpu.dcache.overall_misses::total 9967082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721516500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88721516500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4007000296 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4007000296 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92672471792 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92672471792 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92672471792 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92672471792 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475714 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92728516796 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92728516796 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92728516796 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92728516796 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23475656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23475656 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -754,298 +755,298 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210695 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210695 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211224 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211224 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080504 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28210637 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28210637 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28211166 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28211166 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408333 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408333 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080505 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080505 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353304 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353304 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353298 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353298 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.138003 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.138003 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10374.996831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10374.996831 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353309 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353309 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.431083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.431083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.874183 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.874183 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9297.966731 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9297.966731 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9297.960201 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9297.960201 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 330068 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 99317 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121445 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12837 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717839 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.736777 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.483399 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9303.483399 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.476865 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9303.476865 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329940 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 111027 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121461 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716427 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.648310 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5436552 # number of writebacks -system.cpu.dcache.writebacks::total 5436552 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337556 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337556 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158702 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5432438 # number of writebacks +system.cpu.dcache.writebacks::total 5432438 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337660 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337660 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158703 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158703 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496258 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248221 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248221 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222482 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222482 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496363 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496363 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496363 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496363 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248227 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248227 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470703 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470703 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470707 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470707 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43246268500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43246268500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2278267197 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2278267197 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470712 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470712 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470716 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470716 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43248007500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43248007500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2284927222 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2284927222 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45524535697 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45524535697 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45524750197 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45524750197 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532934722 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45532934722 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45533149222 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45533149222 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223560 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223560 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193924 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193924 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.176719 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.176719 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10240.231556 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10240.231556 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.498648 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.498648 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.028191 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.028191 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8321.514748 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8321.514748 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8321.547873 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8321.547873 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.036329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.036329 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.069452 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.069452 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.509106 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300030 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.507566 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32300812 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35494.538462 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35495.397802 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.509106 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836932 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836932 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.507566 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64603278 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64603278 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300030 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300030 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300030 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300030 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300030 # number of overall hits -system.cpu.icache.overall_hits::total 32300030 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses -system.cpu.icache.overall_misses::total 1154 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61388483 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61388483 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61388483 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61388483 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61388483 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61388483 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32301184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32301184 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32301184 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32301184 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32301184 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32301184 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64604850 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64604850 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32300812 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32300812 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32300812 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32300812 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32300812 # number of overall hits +system.cpu.icache.overall_hits::total 32300812 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61588984 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61588984 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61588984 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61588984 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61588984 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61588984 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32301970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32301970 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32301970 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32301970 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53196.259099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53196.259099 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53196.259099 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 19635 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 227 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53185.651123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53185.651123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53185.651123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53185.651123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53185.651123 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19024 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.497797 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.551111 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50524487 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50524487 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50524487 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50524487 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50524487 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50524487 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49864488 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49864488 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49864488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49864488 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49864488 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49864488 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55521.414286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55521.414286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55521.414286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55521.414286 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54796.140659 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54796.140659 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54796.140659 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54796.140659 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4525641 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296015 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 665258 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4982376 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5297288 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273784 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15178 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11058.580214 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 574.634156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 222.368326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 216.541992 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.674962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035073 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.013572 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013217 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.736824 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 275 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15165 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 972 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13076 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # 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number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 996 # number of overall misses -system.cpu.l2cache.overall_misses::total 1693 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 35228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48202000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48202000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30204500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30204500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48202000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 65432500 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 238 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 966 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016785 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.925598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 175272448 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 175272448 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 5432438 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5432438 # 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number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 504 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 693 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 693 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 553 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 553 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 693 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1057 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1750 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 693 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1057 # number of overall misses +system.cpu.l2cache.overall_misses::total 1750 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 42131500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 42131500 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64481.368564 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63229.496403 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65595.390525 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 42541.593841 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44033.421707 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.004056 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41019.803691 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96347.507331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96347.507331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62579.479769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62579.479769 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56055.075594 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56055.075594 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68257.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62579.479769 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73144.278607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41019.803691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42855.849908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5245099 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5436967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 31344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22118 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226518 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5245116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5432867 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 35515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226510 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244206 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408733 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410992 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698064576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 698122816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22698 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10964961 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.002070 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045451 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697801856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 697860096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 23225 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10965506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.002118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045973 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10942263 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 22698 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 10942281 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 23225 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10964961 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10907683500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 10965506 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10903578500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1366996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206064991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206077992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15676 # Transaction distribution -system.membus.trans_dist::Writeback 415 # Transaction distribution -system.membus.trans_dist::CleanEvict 117 # Transaction distribution -system.membus.trans_dist::ReadExReq 340 # Transaction distribution -system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15676 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32564 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32564 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1051584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1051584 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15736 # Transaction distribution +system.membus.trans_dist::Writeback 429 # Transaction distribution +system.membus.trans_dist::CleanEvict 169 # Transaction distribution +system.membus.trans_dist::ReadExReq 341 # Transaction distribution +system.membus.trans_dist::ReadExResp 341 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15736 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32752 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32752 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1056384 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16548 # Request fanout histogram +system.membus.snoop_fanout::samples 16675 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16548 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16675 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16548 # Request fanout histogram -system.membus.reqLayer0.occupancy 27912645 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16675 # Request fanout histogram +system.membus.reqLayer0.occupancy 28309413 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83778508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 84107303 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 7cef0aacd..c93b4b47a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233283 # Number of seconds simulated -sim_ticks 233282768000 # Number of ticks simulated -final_tick 233282768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233332 # Number of seconds simulated +sim_ticks 233331881000 # Number of ticks simulated +final_tick 233331881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136250 # Simulator instruction rate (inst/s) -host_op_rate 147606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62910352 # Simulator tick rate (ticks/s) -host_mem_usage 320784 # Number of bytes of host memory used -host_seconds 3708.18 # Real time elapsed on the host +host_inst_rate 137799 # Simulator instruction rate (inst/s) +host_op_rate 149285 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63638999 # Simulator tick rate (ticks/s) +host_mem_usage 320760 # Number of bytes of host memory used +host_seconds 3666.49 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 683136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9221056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16463744 # Number of bytes read from this memory -system.physmem.bytes_read::total 26367936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 683136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 683136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18705728 # Number of bytes written to this memory -system.physmem.bytes_written::total 18705728 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144079 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257246 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411999 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292277 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292277 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2928360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39527377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70574197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113029935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2928360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2928360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80184782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80184782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80184782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2928360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39527377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70574197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193214717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411999 # Number of read requests accepted -system.physmem.writeReqs 292277 # Number of write requests accepted -system.physmem.readBursts 411999 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292277 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26229824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138112 # Total number of bytes read from write queue -system.physmem.bytesWritten 18703872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26367936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18705728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2158 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 689792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9194752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16497856 # Number of bytes read from this memory +system.physmem.bytes_read::total 26382400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 689792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 689792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18714240 # Number of bytes written to this memory +system.physmem.bytes_written::total 18714240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10778 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257779 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412225 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292410 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292410 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2956270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39406325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70705537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 113068132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2956270 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2956270 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80204385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80204385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80204385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2956270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39406325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70705537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193272517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412225 # Number of read requests accepted +system.physmem.writeReqs 292410 # Number of write requests accepted +system.physmem.readBursts 412225 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292410 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26244608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 137792 # Total number of bytes read from write queue +system.physmem.bytesWritten 18711808 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26382400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18714240 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 7 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26728 # Per bank write bursts -system.physmem.perBankRdBursts::1 25477 # Per bank write bursts -system.physmem.perBankRdBursts::2 25253 # Per bank write bursts -system.physmem.perBankRdBursts::3 24678 # Per bank write bursts -system.physmem.perBankRdBursts::4 27151 # Per bank write bursts -system.physmem.perBankRdBursts::5 26546 # Per bank write bursts -system.physmem.perBankRdBursts::6 25195 # Per bank write bursts -system.physmem.perBankRdBursts::7 24195 # Per bank write bursts -system.physmem.perBankRdBursts::8 25840 # Per bank write bursts -system.physmem.perBankRdBursts::9 24882 # Per bank write bursts -system.physmem.perBankRdBursts::10 24886 # Per bank write bursts -system.physmem.perBankRdBursts::11 26093 # Per bank write bursts -system.physmem.perBankRdBursts::12 26302 # Per bank write bursts -system.physmem.perBankRdBursts::13 26067 # Per bank write bursts -system.physmem.perBankRdBursts::14 24895 # Per bank write bursts -system.physmem.perBankRdBursts::15 25653 # Per bank write bursts -system.physmem.perBankWrBursts::0 18973 # Per bank write bursts -system.physmem.perBankWrBursts::1 18287 # Per bank write bursts -system.physmem.perBankWrBursts::2 17868 # Per bank write bursts -system.physmem.perBankWrBursts::3 17935 # Per bank write bursts -system.physmem.perBankWrBursts::4 18795 # Per bank write bursts -system.physmem.perBankWrBursts::5 18319 # Per bank write bursts -system.physmem.perBankWrBursts::6 17931 # Per bank write bursts -system.physmem.perBankWrBursts::7 17655 # Per bank write bursts -system.physmem.perBankWrBursts::8 18179 # Per bank write bursts -system.physmem.perBankWrBursts::9 17927 # Per bank write bursts -system.physmem.perBankWrBursts::10 17987 # Per bank write bursts -system.physmem.perBankWrBursts::11 18662 # Per bank write bursts -system.physmem.perBankWrBursts::12 18697 # Per bank write bursts -system.physmem.perBankWrBursts::13 18344 # Per bank write bursts -system.physmem.perBankWrBursts::14 18231 # Per bank write bursts -system.physmem.perBankWrBursts::15 18458 # Per bank write bursts +system.physmem.perBankRdBursts::0 26528 # Per bank write bursts +system.physmem.perBankRdBursts::1 25539 # Per bank write bursts +system.physmem.perBankRdBursts::2 25303 # Per bank write bursts +system.physmem.perBankRdBursts::3 24713 # Per bank write bursts +system.physmem.perBankRdBursts::4 27194 # Per bank write bursts +system.physmem.perBankRdBursts::5 26607 # Per bank write bursts +system.physmem.perBankRdBursts::6 24941 # Per bank write bursts +system.physmem.perBankRdBursts::7 24442 # Per bank write bursts +system.physmem.perBankRdBursts::8 25767 # Per bank write bursts +system.physmem.perBankRdBursts::9 24723 # Per bank write bursts +system.physmem.perBankRdBursts::10 25091 # Per bank write bursts +system.physmem.perBankRdBursts::11 26187 # Per bank write bursts +system.physmem.perBankRdBursts::12 26462 # Per bank write bursts +system.physmem.perBankRdBursts::13 26013 # Per bank write bursts +system.physmem.perBankRdBursts::14 25052 # Per bank write bursts +system.physmem.perBankRdBursts::15 25510 # Per bank write bursts +system.physmem.perBankWrBursts::0 18779 # Per bank write bursts +system.physmem.perBankWrBursts::1 18326 # Per bank write bursts +system.physmem.perBankWrBursts::2 18027 # Per bank write bursts +system.physmem.perBankWrBursts::3 17939 # Per bank write bursts +system.physmem.perBankWrBursts::4 18703 # Per bank write bursts +system.physmem.perBankWrBursts::5 18353 # Per bank write bursts +system.physmem.perBankWrBursts::6 17755 # Per bank write bursts +system.physmem.perBankWrBursts::7 17808 # Per bank write bursts +system.physmem.perBankWrBursts::8 18074 # Per bank write bursts +system.physmem.perBankWrBursts::9 17824 # Per bank write bursts +system.physmem.perBankWrBursts::10 18093 # Per bank write bursts +system.physmem.perBankWrBursts::11 18724 # Per bank write bursts +system.physmem.perBankWrBursts::12 18814 # Per bank write bursts +system.physmem.perBankWrBursts::13 18339 # Per bank write bursts +system.physmem.perBankWrBursts::14 18411 # Per bank write bursts +system.physmem.perBankWrBursts::15 18403 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233282750000 # Total gap between requests +system.physmem.totGap 233331863000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411999 # Read request sizes (log2) +system.physmem.readPktSize::6 412225 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292277 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292410 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 311682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 306889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.413224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.997180 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.093051 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184151 60.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 82036 26.73% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16582 5.40% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7394 2.41% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4756 1.55% 96.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2254 0.73% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1661 0.54% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1625 0.53% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6430 2.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 306889 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.673001 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.829793 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17311 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 307255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.312346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.902161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.114345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184693 60.11% 60.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81851 26.64% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16642 5.42% 92.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7320 2.38% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4729 1.54% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2259 0.74% 96.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1737 0.57% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1607 0.52% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6417 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307255 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.664070 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.589701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17327 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17312 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.881238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.838780 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.240848 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10485 60.56% 60.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 306 1.77% 62.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5502 31.78% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 671 3.88% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 134 0.77% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 74 0.43% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 42 0.24% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 45 0.26% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 29 0.17% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.08% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17328 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17328 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.872807 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.831610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.219578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10506 60.63% 60.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 279 1.61% 62.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5596 32.29% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 616 3.55% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 141 0.81% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 60 0.35% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 44 0.25% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 41 0.24% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 25 0.14% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.04% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17312 # Writes before turning the bus around for reads -system.physmem.totQLat 9036310212 # Total ticks spent queuing -system.physmem.totMemAccLat 16720828962 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2049205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22048.33 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17328 # Writes before turning the bus around for reads +system.physmem.totQLat 9022211140 # Total ticks spent queuing +system.physmem.totMemAccLat 16711061140 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2050360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22001.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40798.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40751.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 113.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.78 # Average write queue length when enqueuing -system.physmem.readRowHits 299552 # Number of row buffer hits during reads -system.physmem.writeRowHits 95641 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 331237.68 # Average gap between requests -system.physmem.pageHitRate 56.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1156763160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 631170375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1600435200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 944401680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74473770375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74637909000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168680907390 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.094931 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 123643637069 # Time in different power states -system.physmem_0.memoryStateTime::REF 7789600000 # Time in different power states +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.59 # Average write queue length when enqueuing +system.physmem.readRowHits 299444 # Number of row buffer hits during reads +system.physmem.writeRowHits 95740 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.74 # Row buffer hit rate for writes +system.physmem.avgGap 331138.62 # Average gap between requests +system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1156823640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631203375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1601035800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 944071200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75187551735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74044498500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168805201770 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.458661 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 122654182736 # Time in different power states +system.physmem_0.memoryStateTime::REF 7791420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 101845250931 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102885452264 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1163007720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 634577625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1595802000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 949158000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15236457600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74040443550 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75018020250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168637466745 # Total energy per rank (pJ) -system.physmem_1.averagePower 722.908711 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124281047938 # Time in different power states -system.physmem_1.memoryStateTime::REF 7789600000 # Time in different power states +system.physmem_1.actEnergy 1166024160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 636223500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1597377600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950499360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15240017520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74554879950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74599507500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168744529590 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.198461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123580654566 # Time in different power states +system.physmem_1.memoryStateTime::REF 7791420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101208398062 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101958813184 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175089811 # Number of BP lookups -system.cpu.branchPred.condPredicted 131337021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444155 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90376647 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83876100 # Number of BTB hits +system.cpu.branchPred.lookups 175090137 # Number of BP lookups +system.cpu.branchPred.condPredicted 131338905 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7443529 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90540858 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83879425 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.807271 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12110019 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104160 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.642622 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110692 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466565537 # number of cpu cycles simulated +system.cpu.numCycles 466663763 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7838065 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731795546 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175089811 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95986119 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450385778 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14940817 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5837 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14677 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236716672 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34578 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465715008 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.701748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179403 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7839248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731808788 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175090137 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95990117 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450472274 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14939659 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5656 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 14269 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236720425 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465801433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701462 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179511 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 93791115 20.14% 20.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132693411 28.49% 48.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57855471 12.42% 61.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181375011 38.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93869731 20.15% 20.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132699774 28.49% 48.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57852108 12.42% 61.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181379820 38.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465715008 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375274 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.568473 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32367511 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117249871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287084329 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22031549 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6981748 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050134 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496459 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715800999 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30008433 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6981748 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63425626 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54212557 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40336788 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276681526 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24076763 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686589929 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9410638 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2384158 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1669115 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1841927 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831018421 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019159141 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723918647 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465801433 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375195 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.568171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32373679 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117343382 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287062106 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22041011 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6981255 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24049971 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496386 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715809364 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30003912 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6981255 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63434666 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54211510 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40338612 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276664591 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24170799 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686600417 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340367 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9416739 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386420 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1670076 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1927738 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831025477 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019202538 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723925996 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176894670 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544698 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534992 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42289780 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143526215 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67981217 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12855514 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11197113 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668159255 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978326 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610231748 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5860169 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123786636 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319274742 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 694 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465715008 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.310312 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101358 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176901726 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544701 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534906 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42308307 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143530339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67981565 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12860716 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11266999 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668170903 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978331 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610248763 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5854866 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123798289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319264737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 699 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465801433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.310105 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101429 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148574576 31.90% 31.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101171602 21.72% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145766544 31.30% 84.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63282576 13.59% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6919220 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 490 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148653685 31.91% 31.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101184506 21.72% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145749505 31.29% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63290175 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6923088 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 474 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465715008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465801433 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71921517 52.96% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44556516 32.81% 85.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19328890 14.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71924616 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44553347 32.81% 85.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19296722 14.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413144323 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351745 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413148587 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351752 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134209580 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62526097 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134215566 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62532855 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610231748 # Type of FU issued -system.cpu.iq.rate 1.307923 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135806953 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222550 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1827845333 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794952356 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594966802 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610248763 # Type of FU issued +system.cpu.iq.rate 1.307684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135774715 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222491 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1827928247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 794975703 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594980555 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746038524 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746023301 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7273046 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7276983 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27641459 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25471 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28891 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11120740 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27645583 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25497 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28922 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11121088 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225190 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22470 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225125 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22421 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6981748 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23001930 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 919984 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672625014 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6981255 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22978687 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 924846 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672636723 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143526215 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67981217 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489784 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258650 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 525178 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28891 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821630 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731398 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7553028 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599382547 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129570228 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10849201 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143530339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67981565 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489789 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258799 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 529739 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28922 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3821583 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731049 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7552632 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599397786 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129576337 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10850977 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487433 # number of nop insts executed -system.cpu.iew.exec_refs 190523509 # number of memory reference insts executed -system.cpu.iew.exec_branches 131370037 # Number of branches executed -system.cpu.iew.exec_stores 60953281 # Number of stores executed -system.cpu.iew.exec_rate 1.284670 # Inst execution rate -system.cpu.iew.wb_sent 596261681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594966818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349901968 # num instructions producing a value -system.cpu.iew.wb_consumers 570648646 # num instructions consuming a value +system.cpu.iew.exec_nop 1487489 # number of nop insts executed +system.cpu.iew.exec_refs 190533026 # number of memory reference insts executed +system.cpu.iew.exec_branches 131372234 # Number of branches executed +system.cpu.iew.exec_stores 60956689 # Number of stores executed +system.cpu.iew.exec_rate 1.284432 # Inst execution rate +system.cpu.iew.wb_sent 596275489 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594980571 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349907425 # num instructions producing a value +system.cpu.iew.wb_consumers 570632122 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.275205 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613165 # average fanout of values written-back +system.cpu.iew.wb_rate 1.274966 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613193 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110016162 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110027797 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6955495 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448601420 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223123 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.887905 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6954955 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448686365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.222892 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.888131 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219539851 48.94% 48.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116349885 25.94% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43748468 9.75% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23302371 5.19% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11552802 2.58% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7777273 1.73% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8275373 1.84% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4252092 0.95% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13803305 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219669318 48.96% 48.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116312485 25.92% 74.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43742979 9.75% 84.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23278779 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11577691 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7777719 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8261206 1.84% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4236050 0.94% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13830138 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448601420 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448686365 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,182 +684,182 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13803305 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093501968 # The number of ROB reads -system.cpu.rob.rob_writes 1334565325 # The number of ROB writes -system.cpu.timesIdled 13884 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 850529 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13830138 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1093571715 # The number of ROB reads +system.cpu.rob.rob_writes 1334590067 # The number of ROB writes +system.cpu.timesIdled 13966 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 862330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923457 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923457 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082887 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082887 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611072880 # number of integer regfile reads -system.cpu.int_regfile_writes 328111730 # number of integer regfile writes +system.cpu.cpi 0.923652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923652 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082659 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082659 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611088796 # number of integer regfile reads +system.cpu.int_regfile_writes 328119086 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170116632 # number of cc regfile reads -system.cpu.cc_regfile_writes 376537008 # number of cc regfile writes -system.cpu.misc_regfile_reads 217962216 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170176811 # number of cc regfile reads +system.cpu.cc_regfile_writes 376539852 # number of cc regfile writes +system.cpu.misc_regfile_reads 217970841 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820796 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631791 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169351038 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821308 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.025718 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498038000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631791 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820945 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.631358 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169354520 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821457 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.023782 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498530000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.631358 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999280 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356237372 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356237372 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114646487 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114646487 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51724617 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51724617 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 356242117 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356242117 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648793 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648793 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51725790 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51725790 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166371104 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166371104 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166373887 # number of overall hits -system.cpu.dcache.overall_hits::total 166373887 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4842277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4842277 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2514689 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2514689 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166374583 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166374583 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166377369 # number of overall hits +system.cpu.dcache.overall_hits::total 166377369 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4842267 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4842267 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2513516 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2513516 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356966 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356966 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356978 # number of overall misses -system.cpu.dcache.overall_misses::total 7356978 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56244825000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56244825000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18846227941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18846227941 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1242500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1242500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75091052941 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75091052941 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75091052941 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75091052941 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119488764 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119488764 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7355783 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7355783 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7355794 # number of overall misses +system.cpu.dcache.overall_misses::total 7355794 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56187510500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56187510500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19050466441 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19050466441 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1271500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1271500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75237976941 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75237976941 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75237976941 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75237976941 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119491060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119491060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173728070 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173728070 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173730865 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173730865 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040525 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040525 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046363 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046363 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173730366 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173730366 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173733163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173733163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046341 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042347 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042347 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11615.367109 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11615.367109 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7494.456746 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7494.456746 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18825.757576 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18825.757576 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10206.796245 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10206.796245 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10206.779596 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10206.779596 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 911242 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221024 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.122819 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042340 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042340 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042340 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042340 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11603.554802 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11603.554802 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7579.210334 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7579.210334 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19265.151515 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19265.151515 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10228.411706 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10228.411706 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10228.396410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10228.396410 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 931670 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221105 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.213699 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2356243 # number of writebacks -system.cpu.dcache.writebacks::total 2356243 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540565 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540565 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995076 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1995076 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2357131 # number of writebacks +system.cpu.dcache.writebacks::total 2357131 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540406 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540406 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1993903 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1993903 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4535641 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4535641 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4535641 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4535641 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301712 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301712 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4534309 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4534309 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4534309 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4534309 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301861 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301861 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519613 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 519613 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821325 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821325 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28710026000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28710026000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4575255494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4575255494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 657000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 657000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33285281494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33285281494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33285938494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33285938494 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 674500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33307836994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 33307836994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33308511494 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 33308511494 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016241 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016241 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12473.335500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12473.335500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8805.121300 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8805.121300 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65700 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65700 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11797.748042 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11797.748042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11797.939094 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11797.939094 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.807702 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.807702 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8891.590461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8891.590461 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67450 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67450 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11805.119237 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11805.119237 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11805.316455 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11805.316455 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73477 # number of replacements -system.cpu.icache.tags.tagsinuse 466.193561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236634038 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73989 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.232683 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114977932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.193561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910534 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910534 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73454 # number of replacements +system.cpu.icache.tags.tagsinuse 466.198570 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236637753 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3199.277411 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 114991601500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.198570 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910544 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910544 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id @@ -867,203 +867,202 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 119 system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # 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number of demand (read+write) misses +system.cpu.icache.demand_misses::total 82554 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 82554 # number of overall misses +system.cpu.icache.overall_misses::total 82554 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1566745159 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1566745159 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1566745159 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1566745159 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1566745159 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1566745159 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236720307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236720307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236720307 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18723.466963 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18723.466963 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18723.466963 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 193180 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6947 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.807687 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18978.428168 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18978.428168 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18978.428168 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18978.428168 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18978.428168 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 198034 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7006 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.266343 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 32 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143669 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275571 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 430019 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 19018555494 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 19018555494 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 33500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 33500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 344223500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 344223500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 727200000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30069314994 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007043 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007043 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144288 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.145739 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060860 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060860 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053342 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145739 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050920 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148406 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69537.256777 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78794.341676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78794.341676 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66995.737705 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66995.737705 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71076.233583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71076.233583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70978.094407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66995.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71273.150333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69537.256777 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70056.196140 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148517 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69015.083205 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92483.476625 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92483.476625 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67464.514333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67464.514333 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71307.966587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71307.966587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71550.033021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67464.514333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71856.555694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69015.083205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69925.549787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2373352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2648520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 622852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 320716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2373490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2649541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 621819 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317371 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 74017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299336 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440541 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331363264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336098176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 721627 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6511219 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.110823 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.313913 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 521960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521960 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 73994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299497 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220555 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440647 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331429632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336163072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 718484 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 6508328 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.110389 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.313375 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5789625 88.92% 88.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 721594 11.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5789877 88.96% 88.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 718451 11.04% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6511219 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5251055500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6508328 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5252069500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111049948 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 111018442 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4231992466 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4232215467 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 408324 # Transaction distribution -system.membus.trans_dist::Writeback 292277 # Transaction distribution -system.membus.trans_dist::CleanEvict 103036 # Transaction distribution +system.membus.trans_dist::ReadResp 408504 # Transaction distribution +system.membus.trans_dist::Writeback 292410 # Transaction distribution +system.membus.trans_dist::CleanEvict 103085 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3675 # Transaction distribution -system.membus.trans_dist::ReadExResp 3675 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 408324 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219317 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1219317 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45073664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45073664 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3721 # Transaction distribution +system.membus.trans_dist::ReadExResp 3721 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 408504 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1219951 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1219951 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45096640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45096640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 807315 # Request fanout histogram +system.membus.snoop_fanout::samples 807723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 807315 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 807723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 807315 # Request fanout histogram -system.membus.reqLayer0.occupancy 2175050688 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 807723 # Request fanout histogram +system.membus.reqLayer0.occupancy 2173813941 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2177979128 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2179181168 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8a385b77d..c456278d9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112686 # Number of seconds simulated -sim_ticks 112686104500 # Number of ticks simulated -final_tick 112686104500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112687 # Number of seconds simulated +sim_ticks 112687034500 # Number of ticks simulated +final_tick 112687034500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125538 # Simulator instruction rate (inst/s) -host_op_rate 150722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51811162 # Simulator tick rate (ticks/s) -host_mem_usage 327864 # Number of bytes of host memory used -host_seconds 2174.94 # Real time elapsed on the host +host_inst_rate 126437 # Simulator instruction rate (inst/s) +host_op_rate 151802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52182660 # Simulator tick rate (ticks/s) +host_mem_usage 327844 # Number of bytes of host memory used +host_seconds 2159.47 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167936 # Number of bytes read from this memory -system.physmem.bytes_read::total 467904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169152 # Number of bytes read from this memory +system.physmem.bytes_read::total 468672 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1764 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2624 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7311 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1660116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1001863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1490299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4152278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1660116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1660116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1660116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1001863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1490299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4152278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7311 # Number of read requests accepted +system.physmem.num_reads::cpu.data 1757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2643 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7323 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1660102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 997879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1501078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4159059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1660102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1660102 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1660102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 997879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1501078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4159059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7323 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7311 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7323 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 467904 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 467904 # Total read bytes from the system interface side +system.physmem.bytesReadSys 468672 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -52,7 +52,7 @@ system.physmem.perBankRdBursts::3 520 # Pe system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 252 # Per bank write bursts +system.physmem.perBankRdBursts::7 251 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts system.physmem.perBankRdBursts::9 290 # Per bank write bursts system.physmem.perBankRdBursts::10 315 # Per bank write bursts @@ -60,7 +60,7 @@ system.physmem.perBankRdBursts::11 411 # Pe system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts system.physmem.perBankRdBursts::14 615 # Per bank write bursts -system.physmem.perBankRdBursts::15 542 # Per bank write bursts +system.physmem.perBankRdBursts::15 555 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112685946000 # Total gap between requests +system.physmem.totGap 112686876000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7311 # Read request sizes (log2) +system.physmem.readPktSize::6 7323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,21 +94,21 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3986 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1463 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 286 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.646672 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.022122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.529599 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 486 35.55% 35.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 298 21.80% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 139 10.17% 67.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 76 5.56% 73.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 4.61% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 51 3.73% 81.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 27 1.98% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.90% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 201 14.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1367 # Bytes accessed per row activation -system.physmem.totQLat 102208518 # Total ticks spent queuing -system.physmem.totMemAccLat 239289768 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13980.10 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.932896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 197.349943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.457617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 486 35.45% 35.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 309 22.54% 57.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 132 9.63% 67.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 75 5.47% 73.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 64 4.67% 77.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48 3.50% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 26 1.90% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.82% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 206 15.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation +system.physmem.totQLat 95174041 # Total ticks spent queuing +system.physmem.totMemAccLat 232480291 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36615000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12996.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32730.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31746.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5935 # Number of row buffer hits during reads +system.physmem.readRowHits 5943 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15413205.58 # Average gap between requests -system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined +system.physmem.avgGap 15388075.38 # Average gap between requests +system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28657200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 28641600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3231673425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64774920750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75402575040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.157389 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107755851914 # Time in different power states +system.physmem_0.actBackEnergy 3233168820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64773630750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75402764835 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.158858 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107753956620 # Time in different power states system.physmem_0.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1164613086 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1166688380 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5496120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2998875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28064400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5526360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3015375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7359880320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3295137510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64719250500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75410827725 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.230627 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107661884129 # Time in different power states +system.physmem_1.actBackEnergy 3309876000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64706325000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75412749855 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.247655 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107640832624 # Time in different power states system.physmem_1.memoryStateTime::REF 3762720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1258279621 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1279848380 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37742989 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164516 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746156 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663196 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299233 # Number of BTB hits +system.cpu.branchPred.lookups 37743135 # Number of BP lookups +system.cpu.branchPred.condPredicted 20164607 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746155 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18663607 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299273 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.691697 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223653 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.689870 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223670 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,95 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225372210 # number of cpu cycles simulated +system.cpu.numCycles 225374070 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12439138 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334051202 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37742989 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522886 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210855691 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510707 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1284 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89092155 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21708 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225054059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.800470 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12439227 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334051995 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37743135 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24522943 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210854521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510703 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2474 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89092353 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21704 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 225052883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.800484 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229411 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51374086 22.83% 22.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42891136 19.06% 41.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30054592 13.35% 55.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100734245 44.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51372314 22.83% 22.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42891452 19.06% 41.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30054577 13.35% 55.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734540 44.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225054059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167470 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.482220 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27837229 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63912010 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108618315 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23065911 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620594 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880048 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363546099 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6169805 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620594 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45200014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 17874059 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 342377 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113380979 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46636036 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355768136 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890465 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6610669 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 225052883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167469 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.482211 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27836779 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63911722 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108618516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23065273 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620593 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880055 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135197 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363544847 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170021 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620593 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45199707 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17872689 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341815 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113380410 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46637669 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355768309 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890306 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6609751 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 177931 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7803674 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21223053 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2890533 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403406015 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534023592 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350247327 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894263 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 7804271 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223751 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2890543 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403406246 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534025265 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350247395 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194894231 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31175964 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 31176195 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55505783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416404 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498336 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661010 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1846418 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252226 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 55506509 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416612 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498373 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1661373 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1847329 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353252571 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346438238 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2301579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25468650 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73725461 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 346438287 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2302047 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25468995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73729207 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225054059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539356 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099855 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 225052883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.539364 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099868 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40665072 18.07% 18.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78300215 34.79% 52.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60997700 27.10% 79.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34882254 15.50% 95.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9557051 4.25% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 642945 0.29% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8822 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40665148 18.07% 18.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78299865 34.79% 52.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60995131 27.10% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34883362 15.50% 95.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9557615 4.25% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 642958 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8804 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225054059 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 225052883 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9490410 7.63% 7.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7314 0.01% 7.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9490613 7.63% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7317 0.01% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.64% # attempts to use FU when none available @@ -488,22 +488,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.64% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255761 0.21% 7.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 126866 0.10% 7.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93218 0.07% 8.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126865 0.10% 7.95% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93219 0.07% 8.02% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 68015 0.05% 8.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 721741 0.58% 8.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683043 0.55% 9.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 721837 0.58% 8.66% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297231 0.24% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683044 0.55% 9.44% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53642366 43.14% 52.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58960700 47.42% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53642383 43.14% 52.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58959382 47.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655140 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148362 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655137 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148355 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +522,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798396 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798397 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8668155 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332481 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668117 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1592458 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930094 6.04% 44.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7182326 2.07% 46.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930149 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182320 2.07% 46.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148962 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923219 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883359 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923270 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883354 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346438238 # Type of FU issued -system.cpu.iq.rate 1.537183 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124346666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358929 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757024395 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740362 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223260150 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287554385 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127018791 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117424955 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303230405 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167554499 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5064919 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438287 # Type of FU issued +system.cpu.iq.rate 1.537170 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124345667 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358926 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 757022758 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251740405 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287554413 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127019437 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424930 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303229780 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167554174 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5064825 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13573 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10255 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122719 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684337 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13570 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10254 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122756 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155303 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607776 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155338 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607759 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620594 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118849 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332046 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281117 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620593 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118874 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 332196 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353281462 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416404 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498336 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 92416612 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498373 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 338505 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10255 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220656 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439058 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659714 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342448377 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703712 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989861 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 338656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10254 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220664 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439075 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659739 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448688 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703769 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989599 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175291126 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752707 # Number of branches executed -system.cpu.iew.exec_stores 84587414 # Number of stores executed -system.cpu.iew.exec_rate 1.519479 # Inst execution rate -system.cpu.iew.wb_sent 340943800 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340685105 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153662327 # num instructions producing a value -system.cpu.iew.wb_consumers 266738216 # num instructions consuming a value +system.cpu.iew.exec_refs 175291174 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752726 # Number of branches executed +system.cpu.iew.exec_stores 84587405 # Number of stores executed +system.cpu.iew.exec_rate 1.519468 # Inst execution rate +system.cpu.iew.wb_sent 340944051 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685332 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153662647 # num instructions producing a value +system.cpu.iew.wb_consumers 266737544 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511655 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576079 # average fanout of values written-back +system.cpu.iew.wb_rate 1.511644 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23082519 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23083260 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1611397 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221328864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481109 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.050764 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 221327720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.050757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87530154 39.55% 39.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70479011 31.84% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20814829 9.40% 80.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13433176 6.07% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8801116 3.98% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4514131 2.04% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2986629 1.35% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2449420 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10320398 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87528718 39.55% 39.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70478843 31.84% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20814822 9.40% 80.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13433890 6.07% 86.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8801339 3.98% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4513701 2.04% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2986759 1.35% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2449542 1.11% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10320106 4.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221328864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221327720 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,92 +654,92 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10320398 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561900676 # The number of ROB reads -system.cpu.rob.rob_writes 705518580 # The number of ROB writes -system.cpu.timesIdled 50864 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 318151 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10320106 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 561900565 # The number of ROB reads +system.cpu.rob.rob_writes 705520050 # The number of ROB writes +system.cpu.timesIdled 50865 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 321187 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825427 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825427 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211495 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211495 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331331443 # number of integer regfile reads -system.cpu.int_regfile_writes 136939322 # number of integer regfile writes -system.cpu.fp_regfile_reads 187108010 # number of floating regfile reads -system.cpu.fp_regfile_writes 132178699 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297132712 # number of cc regfile reads -system.cpu.cc_regfile_writes 80241070 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183128145 # number of misc regfile reads +system.cpu.cpi 0.825434 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.825434 # CPI: Total CPI of All Threads +system.cpu.ipc 1.211485 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.211485 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331332035 # number of integer regfile reads +system.cpu.int_regfile_writes 136939352 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107868 # number of floating regfile reads +system.cpu.fp_regfile_writes 132178738 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297133606 # number of cc regfile reads +system.cpu.cc_regfile_writes 80241640 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183127847 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes system.cpu.dcache.tags.replacements 1533845 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.844014 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163642665 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.843427 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163642817 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1534357 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.652275 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82317000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.844014 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999695 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999695 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 106.652374 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 82681000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336636785 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336636785 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82609327 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82609327 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941037 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941037 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70495 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70495 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 336637061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336637061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82609464 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82609464 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80941053 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80941053 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70494 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70494 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163550364 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163550364 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163620859 # number of overall hits -system.cpu.dcache.overall_hits::total 163620859 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796866 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796866 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111662 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163550517 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163550517 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163621011 # number of overall hits +system.cpu.dcache.overall_hits::total 163621011 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2796868 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2796868 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1111646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1111646 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses -system.cpu.dcache.overall_misses::total 3908546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22404027000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22404027000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8967503998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8967503998 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3908514 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3908514 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3908532 # number of overall misses +system.cpu.dcache.overall_misses::total 3908532 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22403262000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22403262000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8965991000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8965991000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31371530998 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31371530998 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31371530998 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31371530998 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85406193 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85406193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 31369253000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31369253000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31369253000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31369253000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85406332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85406332 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70513 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70513 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70512 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70512 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167458892 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167458892 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167529405 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167529405 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 167459031 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167459031 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167529543 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167529543 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032748 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.032748 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses @@ -750,38 +750,38 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.023340 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.023340 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.404145 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.404145 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8066.754102 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8066.754102 # average WriteReq miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.023330 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023330 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8010.124897 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8010.124897 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8065.509164 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8065.509164 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8026.431178 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8026.431178 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8026.394214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8026.394214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8025.877098 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8025.877098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8025.840136 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8025.840136 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1059827 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1060412 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 134751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.865077 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.869477 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483173 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483173 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891007 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891007 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483175 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1483175 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 890991 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 890991 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374180 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374180 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374180 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374180 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2374166 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2374166 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2374166 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2374166 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313693 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1313693 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses @@ -792,16 +792,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1534348 system.cpu.dcache.demand_mshr_misses::total 1534348 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1534359 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1534359 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10622731000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10622731000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1827670779 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1827670779 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10623648000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10623648000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1826747781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1826747781 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450401779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12450401779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451082779 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12451082779 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12450395781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12450395781 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12451076781 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12451076781 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -812,26 +812,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.159399 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.159399 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8282.933897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8282.933897 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8086.857432 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8086.857432 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8278.750905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8278.750905 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61909.090909 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61909.090909 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.457593 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.457593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.843253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.843253 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8114.453684 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8114.453684 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8114.839344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8114.839344 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715634 # number of replacements -system.cpu.icache.tags.tagsinuse 511.830268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88370349 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 716146 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.397113 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 324802500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.830268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999668 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999668 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715635 # number of replacements +system.cpu.icache.tags.tagsinuse 511.829472 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88370544 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716147 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.397213 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326419500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.829472 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id @@ -839,207 +839,207 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 246 system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178900425 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178900425 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88370349 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88370349 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88370349 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88370349 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88370349 # number of overall hits -system.cpu.icache.overall_hits::total 88370349 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 721790 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 721790 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 721790 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 721790 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 721790 # number of overall misses -system.cpu.icache.overall_misses::total 721790 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973224944 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5973224944 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5973224944 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5973224944 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5973224944 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5973224944 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89092139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89092139 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89092139 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89092139 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89092139 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89092139 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 178900820 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178900820 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88370544 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88370544 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88370544 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88370544 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88370544 # number of overall hits +system.cpu.icache.overall_hits::total 88370544 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721792 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721792 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721792 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721792 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721792 # number of overall misses +system.cpu.icache.overall_misses::total 721792 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5973239447 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5973239447 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5973239447 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5973239447 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5973239447 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5973239447 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89092336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89092336 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89092336 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89092336 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89092336 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89092336 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008102 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.008102 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.008102 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.008102 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008102 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008102 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.571765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8275.571765 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8275.571765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.571765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8275.571765 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62134 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8275.568927 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8275.568927 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8275.568927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8275.568927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8275.568927 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 62302 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2178 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2158 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.528007 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.870250 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5643 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 5643 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 5643 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5549831453 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5549831453 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5549831453 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5549831453 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5644 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5644 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5644 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5644 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5644 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 5644 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716148 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716148 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716148 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716148 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716148 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716148 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5551358955 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5551358955 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5551358955 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5551358955 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5551358955 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5551358955 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7749.570204 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7749.570204 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7749.570204 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7749.570204 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7751.692325 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7751.692325 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7751.692325 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7751.692325 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404667 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404963 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 238 # 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Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 527.166918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5987.985640 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3840429 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7297 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 526.302453 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.206017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.661219 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 617.502494 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 106.083671 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037689 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.364957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 494 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2575.177185 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.633084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 617.470420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.704950 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157176 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037687 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.365478 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 506 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 6791 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 772 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5749 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030151 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030884 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414490 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 68225284 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 68225284 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 68225328 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 68225328 # 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number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 712305 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits -system.cpu.l2cache.overall_hits::total 2244808 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 219874 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219874 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 712306 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 712306 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1312645 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1312645 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 712306 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1532519 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2244825 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 712306 # 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number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1059 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2936 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1854 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4790 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1838 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4774 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2936 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1854 # number of overall misses -system.cpu.l2cache.overall_misses::total 4790 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1838 # number of overall misses +system.cpu.l2cache.overall_misses::total 4774 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57082000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 57082000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 199290000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 199290000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 76381000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 76381000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 199290000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 133463000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 332753000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 199290000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 133463000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 332753000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56035500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56035500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 200811500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 200811500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77311000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 77311000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200811500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133346500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 334158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200811500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133346500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 334158000 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 966339 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 966339 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 220653 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 220653 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 715241 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 715242 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 715242 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1313704 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 1313704 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 715241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 715242 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1534357 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249598 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 715241 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2249599 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 715242 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1534357 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249598 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2249599 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003612 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003612 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003530 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003530 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004105 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004105 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000805 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000805 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000806 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000806 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004105 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.001208 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.002129 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.001198 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.002122 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004105 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.001208 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.002129 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.001198 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.002122 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23000 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71621.079046 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71621.079046 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67878.065395 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67878.065395 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72262.062441 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72262.062441 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69468.267223 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67878.065395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71986.515642 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69468.267223 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71932.605905 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71932.605905 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68396.287466 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68396.287466 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73003.777148 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73003.777148 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69995.391705 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68396.287466 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72549.782372 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69995.391705 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1048,145 +1048,145 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 57 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 48 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 48 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 33 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 33 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 90 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 90 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 103 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30350 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 30350 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30427 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 30427 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 740 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 740 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 731 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 731 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2923 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2923 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1024 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1024 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1026 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1026 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1764 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4687 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1757 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4680 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1764 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 35037 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 188993302 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1757 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30427 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35107 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180653766 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 17000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 17000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181139000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181139000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 68370000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 68370000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181139000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 118983500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 300122500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181139000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118983500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 188993302 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 489115802 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49936000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182660500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182660500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69288000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182660500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 119224000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 301884500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182660500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 119224000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180653766 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482538266 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003354 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003313 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004087 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000781 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002083 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002080 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004087 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015575 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6227.126919 # average HardPFReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015606 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5937.284846 # average HardPFReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68396.621622 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68396.621622 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61970.236059 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61970.236059 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66767.578125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66767.578125 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64032.963516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61970.236059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67450.963719 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6227.126919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13959.979507 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68311.901505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68311.901505 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62490.762915 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62490.762915 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67532.163743 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67532.163743 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64505.235043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62490.762915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67856.573705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5937.284846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13744.787820 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 2029851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029852 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1033896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31809 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716148 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313704 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122580 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6500343 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205819968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32667 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531746 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.007009 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.083423 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 205820032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32715 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4531796 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.007019 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.083485 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4499985 99.30% 99.30% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 31761 0.70% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4499987 99.30% 99.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 31809 0.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531746 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216331500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4531796 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3216332500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074485469 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1074486969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301553965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301554963 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 6571 # Transaction distribution +system.membus.trans_dist::ReadResp 6592 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 740 # Transaction distribution -system.membus.trans_dist::ReadExResp 740 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 6571 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 467904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 467904 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 731 # Transaction distribution +system.membus.trans_dist::ReadExResp 731 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14648 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 468672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7312 # Request fanout histogram +system.membus.snoop_fanout::samples 7324 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7312 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7324 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7312 # Request fanout histogram -system.membus.reqLayer0.occupancy 9348857 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7324 # Request fanout histogram +system.membus.reqLayer0.occupancy 9437390 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38261400 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 38347412 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 95f0885fc..85998f5be 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410927 # Number of seconds simulated -sim_ticks 410926760000 # Number of ticks simulated -final_tick 410926760000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.410670 # Number of seconds simulated +sim_ticks 410669815000 # Number of ticks simulated +final_tick 410669815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92513 # Simulator instruction rate (inst/s) -host_op_rate 113896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59339858 # Simulator tick rate (ticks/s) -host_mem_usage 320156 # Number of bytes of host memory used -host_seconds 6924.97 # Real time elapsed on the host +host_inst_rate 94058 # Simulator instruction rate (inst/s) +host_op_rate 115798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60293323 # Simulator tick rate (ticks/s) +host_mem_usage 320128 # Number of bytes of host memory used +host_seconds 6811.20 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7012480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12950080 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245632 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202345 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315462 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17065036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31514326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49131792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10331846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10331846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10331846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17065036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31514326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59463638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315462 # Number of read requests accepted -system.physmem.writeReqs 66338 # Number of write requests accepted -system.physmem.readBursts 315462 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66338 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 4239360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189568 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 69 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19798 # Per bank write bursts -system.physmem.perBankRdBursts::1 19540 # Per bank write bursts -system.physmem.perBankRdBursts::2 19718 # Per bank write bursts -system.physmem.perBankRdBursts::3 19803 # Per bank write bursts -system.physmem.perBankRdBursts::4 19742 # Per bank write bursts -system.physmem.perBankRdBursts::5 20227 # Per bank write bursts -system.physmem.perBankRdBursts::6 19591 # Per bank write bursts -system.physmem.perBankRdBursts::7 19445 # Per bank write bursts -system.physmem.perBankRdBursts::8 19492 # Per bank write bursts -system.physmem.perBankRdBursts::9 19431 # Per bank write bursts -system.physmem.perBankRdBursts::10 19416 # Per bank write bursts -system.physmem.perBankRdBursts::11 19789 # Per bank write bursts -system.physmem.perBankRdBursts::12 19620 # Per bank write bursts -system.physmem.perBankRdBursts::13 20020 # Per bank write bursts -system.physmem.perBankRdBursts::14 19553 # Per bank write bursts -system.physmem.perBankRdBursts::15 19966 # Per bank write bursts -system.physmem.perBankWrBursts::0 4272 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4243 # Per bank write bursts -system.physmem.perBankWrBursts::5 4228 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 232448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7026304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12953152 # Number of bytes read from this memory +system.physmem.bytes_read::total 20211904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244928 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244928 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202393 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66327 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66327 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 566022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17109375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31541524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49216921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 566022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 566022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10336596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10336596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10336596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 566022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17109375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31541524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59553517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315811 # Number of read requests accepted +system.physmem.writeReqs 66327 # Number of write requests accepted +system.physmem.readBursts 315811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66327 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20192576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4239424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20211904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244928 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 58 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19865 # Per bank write bursts +system.physmem.perBankRdBursts::1 19533 # Per bank write bursts +system.physmem.perBankRdBursts::2 19787 # Per bank write bursts +system.physmem.perBankRdBursts::3 19881 # Per bank write bursts +system.physmem.perBankRdBursts::4 19767 # Per bank write bursts +system.physmem.perBankRdBursts::5 20312 # Per bank write bursts +system.physmem.perBankRdBursts::6 19558 # Per bank write bursts +system.physmem.perBankRdBursts::7 19499 # Per bank write bursts +system.physmem.perBankRdBursts::8 19473 # Per bank write bursts +system.physmem.perBankRdBursts::9 19475 # Per bank write bursts +system.physmem.perBankRdBursts::10 19453 # Per bank write bursts +system.physmem.perBankRdBursts::11 19704 # Per bank write bursts +system.physmem.perBankRdBursts::12 19596 # Per bank write bursts +system.physmem.perBankRdBursts::13 20052 # Per bank write bursts +system.physmem.perBankRdBursts::14 19574 # Per bank write bursts +system.physmem.perBankRdBursts::15 19980 # Per bank write bursts +system.physmem.perBankWrBursts::0 4265 # Per bank write bursts +system.physmem.perBankWrBursts::1 4106 # Per bank write bursts +system.physmem.perBankWrBursts::2 4140 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4250 # Per bank write bursts +system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4093 # Per bank write bursts +system.physmem.perBankWrBursts::15 4156 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410926705500 # Total gap between requests +system.physmem.totGap 410669760500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315462 # Read request sizes (log2) +system.physmem.readPktSize::6 315811 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66338 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 125674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 115954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14051 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4043 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 985 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66327 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 122285 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 942 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 133 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,118 +197,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.487469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.645908 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.261259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54158 39.61% 39.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57478 42.03% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14696 10.75% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1431 1.05% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1373 1.00% 94.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1481 1.08% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1196 0.87% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1150 0.84% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3780 2.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136743 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4027 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 66.735038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.718214 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 464.978559 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 3992 99.13% 99.13% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 15 0.37% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 4 0.10% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 3 0.07% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-5631 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-8703 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 2 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4027 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.448969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.407245 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.299266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3382 83.98% 83.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 84.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 453 11.25% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 103 2.56% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 20 0.50% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.47% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 11 0.27% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.20% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.12% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4027 # Writes before turning the bus around for reads -system.physmem.totQLat 8985315314 # Total ticks spent queuing -system.physmem.totMemAccLat 14894396564 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28511.14 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.756150 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.878617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.405742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53923 39.46% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57606 42.15% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14740 10.79% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1412 1.03% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1397 1.02% 94.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1387 1.01% 95.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1267 0.93% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1142 0.84% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3792 2.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136666 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 73.293227 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.720611 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 661.085009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4010 99.48% 99.48% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 10 0.25% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 2 0.05% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::11264-12287 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::26624-27647 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4031 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4031 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.432895 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.394232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.238105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3399 84.32% 84.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 84.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 453 11.24% 95.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 84 2.08% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 29 0.72% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.42% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 10 0.25% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 13 0.32% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.25% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.05% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4031 # Writes before turning the bus around for reads +system.physmem.totQLat 8703208249 # Total ticks spent queuing +system.physmem.totMemAccLat 14619001999 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1577545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27584.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47261.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46334.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.46 # Data bus utilization in percentage system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing -system.physmem.readRowHits 218304 # Number of row buffer hits during reads -system.physmem.writeRowHits 26331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.73 # Row buffer hit rate for writes -system.physmem.avgGap 1076287.86 # Average gap between requests -system.physmem.pageHitRate 64.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 518260680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282781125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1231058400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 25.17 # Average write queue length when enqueuing +system.physmem.readRowHits 218486 # Number of row buffer hits during reads +system.physmem.writeRowHits 26585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.12 # Row buffer hit rate for writes +system.physmem.avgGap 1074663.50 # Average gap between requests +system.physmem.pageHitRate 64.19 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 519334200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 283366875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1233694800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216522720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96516777600 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161887922250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287492576775 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.632177 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 268678979341 # Time in different power states -system.physmem_0.memoryStateTime::REF 13721500000 # Time in different power states +system.physmem_0.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96824469870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161463849000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 287363708985 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.756123 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 267972811336 # Time in different power states +system.physmem_0.memoryStateTime::REF 13712920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128519138159 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128976939914 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 515334960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 281184750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1226448600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212712480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26839254000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96027774030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 162316872750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287419581570 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.454538 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 269400106911 # Time in different power states -system.physmem_1.memoryStateTime::REF 13721500000 # Time in different power states +system.physmem_1.actEnergy 513679320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280281375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226604600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212718960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26822471520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96486689295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 161760147750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 287302592820 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.607300 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 268468666587 # Time in different power states +system.physmem_1.memoryStateTime::REF 13712920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127799659089 # Time in different power states +system.physmem_1.memoryStateTime::ACT 128482733413 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233961600 # Number of BP lookups -system.cpu.branchPred.condPredicted 161823435 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514478 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121576875 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108260850 # Number of BTB hits +system.cpu.branchPred.lookups 234660907 # Number of BP lookups +system.cpu.branchPred.condPredicted 161885632 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514558 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 122787051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 109471469 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047239 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25036809 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300056 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.155549 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25674321 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300177 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -427,84 +425,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821853521 # number of cpu cycles simulated +system.cpu.numCycles 821339631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85352108 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200709266 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233961600 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133297659 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720636600 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063377 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2846 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85359172 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200831144 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234660907 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135145790 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 720108706 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063537 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370706156 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652600 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821526595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.826688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.166658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3327 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 371279487 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652622 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 821005776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.826136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.165203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139803220 17.02% 17.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223204281 27.17% 44.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98088574 11.94% 56.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360430520 43.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 139284134 16.97% 16.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223266821 27.19% 44.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 99362992 12.10% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359091829 43.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821526595 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.284676 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.460977 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121268240 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 161448420 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660246 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631680 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518009 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181996 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13829 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248138563 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39966565 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518009 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178275276 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80711720 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 210548 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319817 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82491225 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190650018 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25545971 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24926226 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267555 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41530027 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1673344 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225393242 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812447453 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358179782 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 821005776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285705 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.462040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121274951 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 160921163 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484660075 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38631496 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518091 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25119096 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248135517 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39967011 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518091 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178281745 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 80150846 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 211317 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82524216 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190646555 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25420306 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24957441 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267221 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41531798 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1705173 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225452951 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812557102 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358174955 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876459 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350615012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7270 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 350674721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108779302 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366116842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236096763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1776884 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5334939 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168558899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 108777970 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366242931 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095379 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1613389 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5371796 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168681315 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12359 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017090766 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18380245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379846300 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032153355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017114082 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18565562 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379968716 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032836656 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 205 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821526595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.238050 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 821005776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.238863 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084756 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263868507 32.12% 32.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227113166 27.65% 59.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217783209 26.51% 86.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96635677 11.76% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16126029 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 263349245 32.08% 32.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227125536 27.66% 59.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217733280 26.52% 86.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96668881 11.77% 98.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16128827 1.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -512,44 +510,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821526595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 821005776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63875827 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63875016 18.90% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18146 0.01% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.90% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157407577 46.57% 65.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116033793 34.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 157510134 46.60% 65.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 115986364 34.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370958 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195826 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370249 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195831 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -573,88 +571,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478994 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322082825 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215586812 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322123387 31.67% 78.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215570268 21.19% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017090766 # Type of FU issued -system.cpu.iq.rate 1.237557 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337972229 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332293 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3150183586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504870139 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934273978 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877015 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565815 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017114082 # Type of FU issued +system.cpu.iq.rate 1.238360 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338026549 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332339 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3149949023 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1505114950 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934262178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877028 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565833 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321252671 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810324 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960626 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 1321330304 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960611 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113875904 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 114001993 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18399 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107116267 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18396 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107114883 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065816 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20694 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065819 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19975 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518009 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35327000 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 41213 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168576814 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518091 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326945 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 43224 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168699230 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366116842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236096763 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366242931 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095379 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6619 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 44806 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18399 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437241 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784654 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751722 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303298002 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42339044 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 99 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 46833 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18396 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437302 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784553 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221855 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974739392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297512 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42374690 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497764632 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613642 # Number of branches executed -system.cpu.iew.exec_stores 194466630 # Number of stores executed -system.cpu.iew.exec_rate 1.186041 # Inst execution rate -system.cpu.iew.wb_sent 963724701 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960426422 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536047355 # num instructions producing a value -system.cpu.iew.wb_consumers 893284415 # num instructions consuming a value +system.cpu.iew.exec_refs 497752889 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613606 # Number of branches executed +system.cpu.iew.exec_stores 194455377 # Number of stores executed +system.cpu.iew.exec_rate 1.186768 # Inst execution rate +system.cpu.iew.wb_sent 963712681 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960414622 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536046271 # num instructions producing a value +system.cpu.iew.wb_consumers 893280305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.168610 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back +system.cpu.iew.wb_rate 1.169327 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357420349 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357416983 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500799 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770704967 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.023388 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.776993 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 770184473 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.024079 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.777435 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 432077450 56.06% 56.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174390434 22.63% 78.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936884 9.46% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32898197 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8538905 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258273 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269904 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974492 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360428 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 431571304 56.03% 56.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174376243 22.64% 78.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72936565 9.47% 88.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32893073 4.27% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8539337 1.11% 93.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14258396 1.85% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7274917 0.94% 96.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5974456 0.78% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360182 2.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770704967 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770184473 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -700,80 +698,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360428 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1894486207 # The number of ROB reads -system.cpu.rob.rob_writes 2343126387 # The number of ROB writes -system.cpu.timesIdled 647317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326926 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360182 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1893962593 # The number of ROB reads +system.cpu.rob.rob_writes 2343119332 # The number of ROB writes +system.cpu.timesIdled 647411 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 333855 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282845 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282845 # CPI: Total CPI of All Threads -system.cpu.ipc 0.779518 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.779518 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995802121 # number of integer regfile reads -system.cpu.int_regfile_writes 567908278 # number of integer regfile writes +system.cpu.cpi 1.282043 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.282043 # CPI: Total CPI of All Threads +system.cpu.ipc 0.780005 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.780005 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995778090 # number of integer regfile reads +system.cpu.int_regfile_writes 567907785 # number of integer regfile writes system.cpu.fp_regfile_reads 31889840 # number of floating regfile reads system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794438886 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898194 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817246 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794401386 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898061 # number of cc regfile writes +system.cpu.misc_regfile_reads 715805814 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933712 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414215984 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258129 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 256316000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933712 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999871 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999871 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756185 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.933524 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216512 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258266 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 256787000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.933524 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999870 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999870 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346446 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346446 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293586 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293586 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907704 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907704 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839346679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839346679 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293684 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293684 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127908123 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127908123 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414201290 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414201290 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414204447 # number of overall hits -system.cpu.dcache.overall_hits::total 414204447 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3034530 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3034530 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043773 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043773 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414201807 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414201807 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414204964 # number of overall hits +system.cpu.dcache.overall_hits::total 414204964 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3034548 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3034548 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1043354 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1043354 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4078303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4078303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078949 # number of overall misses -system.cpu.dcache.overall_misses::total 4078949 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35233063500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35233063500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9908998850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9908998850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4077902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4077902 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4078548 # number of overall misses +system.cpu.dcache.overall_misses::total 4078548 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35018337000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35018337000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10025314350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10025314350 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 188000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 188000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45142062350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45142062350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45142062350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45142062350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328116 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 45043651350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45043651350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45043651350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45043651350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328232 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328232 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -782,72 +780,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279593 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279593 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283396 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283396 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418279709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418279709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418283512 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418283512 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010488 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010488 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008094 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008094 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008091 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008091 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009750 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009750 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009752 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11610.715168 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11610.715168 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9493.442396 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9493.442396 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009749 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009749 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11539.885677 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11539.885677 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9608.737159 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9608.737159 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62666.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62666.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11068.834844 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11068.834844 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11067.081827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11067.081827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11045.790544 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11045.790544 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11044.041004 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11044.041004 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 326278 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 356457 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4730 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 67.011296 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.360888 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735190 # number of writebacks -system.cpu.dcache.writebacks::total 735190 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999322 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999322 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322910 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322910 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735102 # number of writebacks +system.cpu.dcache.writebacks::total 735102 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999338 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999338 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322490 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 322490 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1322232 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1322232 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1322232 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1322232 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035208 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959479350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959479350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6004500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6004500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29778573350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29778573350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29784577850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29784577850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -858,231 +856,231 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.980627 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.980627 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8247.313082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8247.313082 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9671.606864 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8048.358303 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8048.358303 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.358303 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8048.358303 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 80051 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 126 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3834 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.984848 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # 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number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013945 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013945 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013945 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013945 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.252121 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.252121 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.252121 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.252121 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75488.376021 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1091,153 +1089,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66338 # number of writebacks -system.cpu.l2cache.writebacks::total 66338 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1216 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1216 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7943700500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17045778133 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25229279633 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 66327 # number of writebacks +system.cpu.l2cache.writebacks::total 66327 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1069 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1069 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 9 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 955 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 955 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2024 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2033 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2024 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2033 # number of overall MSHR hits +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8960 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 8960 # number of CleanEvict MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202470 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202470 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1379 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7547443000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 244477000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7690370500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7934847500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 244477000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7690370500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16906807287 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24841654787 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001934 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001934 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053136 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053136 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014271 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039747 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001913 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001913 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000703 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053249 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053249 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014308 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000703 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039809 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84209.534253 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16781.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16781.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88480.989957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88480.989957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67606.709896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67606.709896 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72292.911552 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72292.911552 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72345.460894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67606.709896 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72498.863740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84209.534253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79956.390777 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039851 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83502.777137 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16777.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16777.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 103645.757796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 103645.757796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67311.949339 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67311.949339 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69621.362089 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69621.362089 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69961.095241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67311.949339 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70048.735722 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83502.777137 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78640.704259 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7205469 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6778838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 266094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035849 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15507443 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626416 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23133859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330854720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223480704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554335424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 565266 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16416862 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.034431 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.182334 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7205861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 801429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6779490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 246291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035851 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508607 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23134825 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330879552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554354688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 545836 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 16398212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.033285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.179381 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15851611 96.56% 96.56% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 565251 3.44% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15852393 96.67% 96.67% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 545819 3.33% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16416862 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8660995500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 16398212 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8661298500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754456946 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7755038952 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135063976 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135066975 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 314068 # Transaction distribution -system.membus.trans_dist::Writeback 66338 # Transaction distribution -system.membus.trans_dist::CleanEvict 232219 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 1394 # Transaction distribution -system.membus.trans_dist::ReadExResp 1394 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 314068 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 929513 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 929513 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 314432 # Transaction distribution +system.membus.trans_dist::Writeback 66327 # Transaction distribution +system.membus.trans_dist::CleanEvict 232586 # Transaction distribution +system.membus.trans_dist::UpgradeReq 18 # Transaction distribution +system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::ReadExReq 1379 # Transaction distribution +system.membus.trans_dist::ReadExResp 1379 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 314432 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 930571 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 930571 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24456832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24456832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 614035 # Request fanout histogram +system.membus.snoop_fanout::samples 614742 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 614035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 614742 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 614035 # Request fanout histogram -system.membus.reqLayer0.occupancy 967133123 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 614742 # Request fanout histogram +system.membus.reqLayer0.occupancy 978145707 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648308021 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1654146686 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 54ac67971..c156cc0a5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033295 # Number of seconds simulated -sim_ticks 33294994000 # Number of ticks simulated -final_tick 33294994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033333 # Number of seconds simulated +sim_ticks 33333078000 # Number of ticks simulated +final_tick 33333078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125667 # Simulator instruction rate (inst/s) -host_op_rate 160714 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59007684 # Simulator tick rate (ticks/s) -host_mem_usage 325068 # Number of bytes of host memory used -host_seconds 564.25 # Real time elapsed on the host +host_inst_rate 125008 # Simulator instruction rate (inst/s) +host_op_rate 159871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58765299 # Simulator tick rate (ticks/s) +host_mem_usage 325044 # Number of bytes of host memory used +host_seconds 567.22 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 579648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2508288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6196352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9284288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 579648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 579648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6263808 # Number of bytes written to this memory -system.physmem.bytes_written::total 6263808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9057 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39192 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96818 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145067 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97872 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97872 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17409464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75335289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 186104614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278849367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17409464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17409464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 188130624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 188130624 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 188130624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17409464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75335289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 186104614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466979991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145067 # Number of read requests accepted -system.physmem.writeReqs 97872 # Number of write requests accepted -system.physmem.readBursts 145067 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97872 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9276928 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 591360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2521216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6195328 # Number of bytes read from this memory +system.physmem.bytes_read::total 9307904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 591360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 591360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6264192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6264192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9240 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96802 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97878 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97878 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17740936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75637059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185861264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 279239259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17740936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17740936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187927200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187927200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187927200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17740936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75637059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185861264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 467166458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145436 # Number of read requests accepted +system.physmem.writeReqs 97878 # Number of write requests accepted +system.physmem.readBursts 145436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97878 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9300544 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6262080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9284288 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6263808 # Total written bytes from the system interface side +system.physmem.bytesWritten 6263104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9307904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6264192 # Total written bytes from the system interface side system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9133 # Per bank write bursts -system.physmem.perBankRdBursts::1 9402 # Per bank write bursts -system.physmem.perBankRdBursts::2 9189 # Per bank write bursts -system.physmem.perBankRdBursts::3 9501 # Per bank write bursts -system.physmem.perBankRdBursts::4 9688 # Per bank write bursts -system.physmem.perBankRdBursts::5 9749 # Per bank write bursts -system.physmem.perBankRdBursts::6 9050 # Per bank write bursts -system.physmem.perBankRdBursts::7 9017 # Per bank write bursts -system.physmem.perBankRdBursts::8 9142 # Per bank write bursts -system.physmem.perBankRdBursts::9 8554 # Per bank write bursts -system.physmem.perBankRdBursts::10 8859 # Per bank write bursts -system.physmem.perBankRdBursts::11 8689 # Per bank write bursts -system.physmem.perBankRdBursts::12 8621 # Per bank write bursts -system.physmem.perBankRdBursts::13 8707 # Per bank write bursts -system.physmem.perBankRdBursts::14 8654 # Per bank write bursts -system.physmem.perBankRdBursts::15 8997 # Per bank write bursts -system.physmem.perBankWrBursts::0 5994 # Per bank write bursts -system.physmem.perBankWrBursts::1 6239 # Per bank write bursts -system.physmem.perBankWrBursts::2 6113 # Per bank write bursts -system.physmem.perBankWrBursts::3 6223 # Per bank write bursts -system.physmem.perBankWrBursts::4 6099 # Per bank write bursts -system.physmem.perBankWrBursts::5 6360 # Per bank write bursts -system.physmem.perBankWrBursts::6 6100 # Per bank write bursts -system.physmem.perBankWrBursts::7 5988 # Per bank write bursts -system.physmem.perBankWrBursts::8 5999 # Per bank write bursts -system.physmem.perBankWrBursts::9 6164 # Per bank write bursts -system.physmem.perBankWrBursts::10 6223 # Per bank write bursts -system.physmem.perBankWrBursts::11 5911 # Per bank write bursts -system.physmem.perBankWrBursts::12 6098 # Per bank write bursts -system.physmem.perBankWrBursts::13 6094 # Per bank write bursts -system.physmem.perBankWrBursts::14 6156 # Per bank write bursts -system.physmem.perBankWrBursts::15 6084 # Per bank write bursts +system.physmem.perBankRdBursts::0 9151 # Per bank write bursts +system.physmem.perBankRdBursts::1 9416 # Per bank write bursts +system.physmem.perBankRdBursts::2 9264 # Per bank write bursts +system.physmem.perBankRdBursts::3 9524 # Per bank write bursts +system.physmem.perBankRdBursts::4 9728 # Per bank write bursts +system.physmem.perBankRdBursts::5 9774 # Per bank write bursts +system.physmem.perBankRdBursts::6 9086 # Per bank write bursts +system.physmem.perBankRdBursts::7 9016 # Per bank write bursts +system.physmem.perBankRdBursts::8 9170 # Per bank write bursts +system.physmem.perBankRdBursts::9 8620 # Per bank write bursts +system.physmem.perBankRdBursts::10 8843 # Per bank write bursts +system.physmem.perBankRdBursts::11 8715 # Per bank write bursts +system.physmem.perBankRdBursts::12 8697 # Per bank write bursts +system.physmem.perBankRdBursts::13 8672 # Per bank write bursts +system.physmem.perBankRdBursts::14 8700 # Per bank write bursts +system.physmem.perBankRdBursts::15 8945 # Per bank write bursts +system.physmem.perBankWrBursts::0 6002 # Per bank write bursts +system.physmem.perBankWrBursts::1 6227 # Per bank write bursts +system.physmem.perBankWrBursts::2 6156 # Per bank write bursts +system.physmem.perBankWrBursts::3 6165 # Per bank write bursts +system.physmem.perBankWrBursts::4 6066 # Per bank write bursts +system.physmem.perBankWrBursts::5 6338 # Per bank write bursts +system.physmem.perBankWrBursts::6 6039 # Per bank write bursts +system.physmem.perBankWrBursts::7 6021 # Per bank write bursts +system.physmem.perBankWrBursts::8 6032 # Per bank write bursts +system.physmem.perBankWrBursts::9 6183 # Per bank write bursts +system.physmem.perBankWrBursts::10 6239 # Per bank write bursts +system.physmem.perBankWrBursts::11 5928 # Per bank write bursts +system.physmem.perBankWrBursts::12 6101 # Per bank write bursts +system.physmem.perBankWrBursts::13 6124 # Per bank write bursts +system.physmem.perBankWrBursts::14 6211 # Per bank write bursts +system.physmem.perBankWrBursts::15 6029 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33294791000 # Total gap between requests +system.physmem.totGap 33332792500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145067 # Read request sizes (log2) +system.physmem.readPktSize::6 145436 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97872 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 42425 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97878 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 41531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6327 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.366717 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.599846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 238.987527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52022 58.71% 58.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22627 25.54% 84.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4475 5.05% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1626 1.84% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1127 1.27% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 853 0.96% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 741 0.84% 94.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 771 0.87% 95.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4363 4.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 88939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 174.992388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.439382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.025071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52267 58.77% 58.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22760 25.59% 84.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4436 4.99% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1732 1.95% 91.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1066 1.20% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 777 0.87% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 661 0.74% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 818 0.92% 95.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4422 4.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88939 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.519032 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.016952 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.911555 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.584503 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.105941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.238550 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.553037 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.510340 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.264183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4718 79.82% 79.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.51% 80.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 754 12.76% 93.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 178 3.01% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 93 1.57% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 63 1.07% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 39 0.66% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.30% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.22% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.555744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.266741 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4704 79.58% 79.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 36 0.61% 80.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 781 13.21% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 157 2.66% 96.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 88 1.49% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 64 1.08% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 47 0.80% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.24% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 17 0.29% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads -system.physmem.totQLat 7210112096 # Total ticks spent queuing -system.physmem.totMemAccLat 9927962096 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 724760000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49741.38 # Average queueing delay per DRAM burst +system.physmem.totQLat 7028707749 # Total ticks spent queuing +system.physmem.totMemAccLat 9753476499 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 726605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 48366.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68491.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 188.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 188.13 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 67116.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 279.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.89 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 279.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.65 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 117862 # Number of row buffer hits during reads -system.physmem.writeRowHits 36326 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.12 # Row buffer hit rate for writes -system.physmem.avgGap 137050.00 # Average gap between requests -system.physmem.pageHitRate 63.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582823800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 318271680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11786161320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9637821000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25027725510 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.712810 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15936534744 # Time in different power states -system.physmem_0.memoryStateTime::REF 1111760000 # Time in different power states +system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing +system.physmem.readRowHits 118079 # Number of row buffer hits during reads +system.physmem.writeRowHits 36164 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.95 # Row buffer hit rate for writes +system.physmem.avgGap 136994.96 # Average gap between requests +system.physmem.pageHitRate 63.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343934640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187662750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 584680200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 317610720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11782825965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9664105500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25057965135 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.742046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15979863754 # Time in different power states +system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16245984006 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16240286246 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328217400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179086875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 547723800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315763920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11208088125 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10144902750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24898385430 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.828055 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16783464024 # Time in different power states -system.physmem_1.memoryStateTime::REF 1111760000 # Time in different power states +system.physmem_1.actEnergy 328444200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179210625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 548823600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316528560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2177145360 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11298113640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10089291750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24937557735 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.129809 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16691408912 # Time in different power states +system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15399360476 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15528741088 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17206050 # Number of BP lookups -system.cpu.branchPred.condPredicted 11517760 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648066 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9347785 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7673761 # Number of BTB hits +system.cpu.branchPred.lookups 17206633 # Number of BP lookups +system.cpu.branchPred.condPredicted 11518078 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648316 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9346074 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675410 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.091758 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873139 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.124430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873047 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101552 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +411,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66589989 # number of cpu cycles simulated +system.cpu.numCycles 66666157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5006781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88183966 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17206050 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9546900 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60089478 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322083 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5010938 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88191821 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17206633 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9548457 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60137734 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322663 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13752 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22762089 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69210 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65777829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696584 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 13644 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22767110 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69105 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65830648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.695372 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296604 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20002417 30.41% 30.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8264821 12.56% 42.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9199012 13.98% 56.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28311579 43.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20050738 30.46% 30.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8265796 12.56% 43.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9200690 13.98% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28313424 43.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65777829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258388 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.324283 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8581179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19502182 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31574906 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5627602 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 491960 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179377 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170933 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101404474 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3045182 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 491960 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13335070 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5313056 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 801397 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32234531 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13601815 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99199856 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 982546 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3844821 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62523 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4317608 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5297882 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103921297 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457696388 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115410759 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65830648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258101 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.322887 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8588438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19545167 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31574635 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5630215 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492193 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3180012 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171001 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101409826 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3046686 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492193 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13345278 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5337889 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 804170 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32233077 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13618041 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99203464 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 983266 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3848076 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66970 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4316860 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5302934 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925476 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457709098 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115412648 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10292071 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12693629 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24321623 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21992796 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1398027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2340833 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98163899 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94893533 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694347 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7515835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20236855 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 735 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65777829 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.442637 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149664 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296250 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18653 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12703257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24321959 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21992794 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1408685 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2344134 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98166936 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34525 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94895750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 693672 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7518876 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20249831 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 739 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65830648 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.441513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149732 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17511633 26.62% 26.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17428256 26.50% 53.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17102675 26.00% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11682123 17.76% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2052152 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 990 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17559708 26.67% 26.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17428340 26.47% 53.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17111473 25.99% 79.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11681013 17.74% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2049145 3.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 969 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65777829 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65830648 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6715699 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 38 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11201748 37.36% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12068794 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6713649 22.39% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 39 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11199453 37.36% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12066123 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49496640 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89875 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49496629 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89874 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -561,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24065423 25.36% 77.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241557 22.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24067515 25.36% 77.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241694 22.38% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94893533 # Type of FU issued -system.cpu.iq.rate 1.425042 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29986279 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315999 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286245314 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105725496 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465397 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94895750 # Type of FU issued +system.cpu.iq.rate 1.423447 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29979264 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315918 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286294877 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105731606 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465380 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124879694 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124874896 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1364211 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1362273 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1455361 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455697 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11748 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1437058 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11776 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1437056 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140354 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 182528 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140882 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 184054 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 491960 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 620291 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 463716 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98208276 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492193 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 620956 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 467696 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98211315 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24321623 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21992796 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18601 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1628 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 459155 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11748 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302696 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221540 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524236 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93976140 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23758122 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917393 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24321959 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21992794 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18605 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1621 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463138 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11776 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302825 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221559 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93978064 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23759823 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917686 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9856 # number of nop insts executed -system.cpu.iew.exec_refs 44743070 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251776 # Number of branches executed -system.cpu.iew.exec_stores 20984948 # Number of stores executed -system.cpu.iew.exec_rate 1.411265 # Inst execution rate -system.cpu.iew.wb_sent 93586994 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465454 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44981756 # num instructions producing a value -system.cpu.iew.wb_consumers 76565949 # num instructions consuming a value +system.cpu.iew.exec_nop 9854 # number of nop insts executed +system.cpu.iew.exec_refs 44744798 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251807 # Number of branches executed +system.cpu.iew.exec_stores 20984975 # Number of stores executed +system.cpu.iew.exec_rate 1.409682 # Inst execution rate +system.cpu.iew.wb_sent 93587077 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465437 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44977935 # num instructions producing a value +system.cpu.iew.wb_consumers 76555853 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.403596 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587490 # average fanout of values written-back +system.cpu.iew.wb_rate 1.401992 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587518 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6535729 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6538600 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 478985 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64719651 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.401246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164864 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479178 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64771963 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.400114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164673 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31116285 48.08% 48.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16809912 25.97% 74.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4342534 6.71% 80.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161990 6.43% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1938865 3.00% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1263903 1.95% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 739138 1.14% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578808 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3768216 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31176340 48.13% 48.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16804620 25.94% 74.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4339366 6.70% 80.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4157771 6.42% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1944331 3.00% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1263277 1.95% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 736800 1.14% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578701 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3770757 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64719651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64771963 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3768216 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158150002 # The number of ROB reads -system.cpu.rob.rob_writes 195507605 # The number of ROB writes -system.cpu.timesIdled 23773 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 812160 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3770757 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158202644 # The number of ROB reads +system.cpu.rob.rob_writes 195513856 # The number of ROB writes +system.cpu.timesIdled 23729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 835509 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.939109 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.939109 # CPI: Total CPI of All Threads -system.cpu.ipc 1.064839 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.064839 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102273698 # number of integer regfile reads -system.cpu.int_regfile_writes 56793498 # number of integer regfile writes +system.cpu.cpi 0.940183 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940183 # CPI: Total CPI of All Threads +system.cpu.ipc 1.063623 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.063623 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102275291 # number of integer regfile reads +system.cpu.int_regfile_writes 56793629 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346096996 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804962 # number of cc regfile writes -system.cpu.misc_regfile_reads 44209976 # number of misc regfile reads +system.cpu.cc_regfile_reads 346102642 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804681 # number of cc regfile writes +system.cpu.misc_regfile_reads 44209969 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485041 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.740827 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40418511 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485553 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.242223 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152851500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.740827 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997541 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997541 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485047 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.741433 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40420740 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485559 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.245785 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 153056500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.741433 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997542 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997542 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84611501 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84611501 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21495962 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21495962 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831064 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831064 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15352 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15352 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84615723 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84615723 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21498446 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21498446 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830779 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830779 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60221 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60221 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15346 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15346 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40327026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40327026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40387214 # number of overall hits -system.cpu.dcache.overall_hits::total 40387214 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 556411 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 556411 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018837 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018837 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68667 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68667 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 574 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 574 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1575248 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575248 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643915 # number of overall misses -system.cpu.dcache.overall_misses::total 1643915 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8968261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8968261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14556255401 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14556255401 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4964500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4964500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23524516401 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23524516401 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23524516401 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23524516401 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22052373 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22052373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40329225 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40329225 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40389446 # number of overall hits +system.cpu.dcache.overall_hits::total 40389446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 556041 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 556041 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019122 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019122 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68628 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68628 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 580 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 580 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1575163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1643791 # number of overall misses +system.cpu.dcache.overall_misses::total 1643791 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8960046000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8960046000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14598887903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14598887903 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5237000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5237000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23558933903 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23558933903 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23558933903 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23558933903 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128849 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41902274 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41902274 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42031129 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42031129 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025231 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025231 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051327 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051327 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532901 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532901 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036042 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8648.954704 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8648.954704 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14933.849401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14310.056421 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 45 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3094334 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130016 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.625000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.799640 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033237 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033237 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025212 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051341 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532623 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532623 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036418 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036418 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037589 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037589 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039107 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039107 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16114.002385 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16114.002385 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14324.965905 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14324.965905 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9029.310345 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9029.310345 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14956.505392 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14956.505392 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14332.073787 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14332.073787 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3099418 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130265 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.166667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.793175 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 256956 # number of writebacks -system.cpu.dcache.writebacks::total 256956 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256971 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256971 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870307 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870307 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 574 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 574 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1127278 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1127278 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1127278 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1127278 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299440 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299440 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 261117 # number of writebacks +system.cpu.dcache.writebacks::total 261117 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256598 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2017960000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2017960000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5528206460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5528206460 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7546166460 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7546166460 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5545966465 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7559546465 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7559546465 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013577 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10664.154781 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 353 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45847164 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45847164 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22427950 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22427950 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22427950 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22427950 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22427950 # number of overall hits -system.cpu.icache.overall_hits::total 22427950 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22761962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22761962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22761962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22761962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22761962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22761962 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014674 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014674 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014674 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014674 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014674 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22766988 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22766988 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22766988 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10093.855108 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10093.855108 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10093.855108 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10093.855108 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10093.855108 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10093.855108 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 274760 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 147 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16673 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.479338 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 49 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10772 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10772 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10772 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10772 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10772 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10772 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323240 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323240 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323240 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323240 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323240 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323240 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3075719938 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3075719938 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3075719938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3075719938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3075719938 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3075719938 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014201 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014201 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014201 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014201 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 872 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 22 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2643 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12025 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 539 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 883 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002258 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.991516 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24881143 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1072,153 +1072,153 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97872 # number of writebacks -system.cpu.l2cache.writebacks::total 97872 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3181 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3181 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 46 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 46 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 128 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 128 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 650223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3129908500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10889744040 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14669875540 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8386 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8386 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9240 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9240 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 31008 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 31008 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 677751000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 677751000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 663843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 663843000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2494831000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2494831000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 663843000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3172582000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3836425000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 663843000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3172582000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10641572084 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14477997084 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.461538 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.461538 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055753 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055753 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028021 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.091722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.091722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080716 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059657 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080716 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056446 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056446 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028576 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092014 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092014 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060123 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.198705 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199213 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94583.344449 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16750 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80819.341760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80819.341760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71844.480519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71844.480519 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80457.656089 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80457.656089 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78883.599951 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71844.480519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80534.649947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94583.344449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89845.089386 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 660226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 354828 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 502259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 152780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323240 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336986 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20686336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47520576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68206912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 281979 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1898528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.148517 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.355611 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 358995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 498597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 141207 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323361 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336991 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2345887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20694144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47787264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68481408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 270774 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1887575 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.143443 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.350524 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1616565 85.15% 85.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 281963 14.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1616816 85.66% 85.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 270759 14.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1898528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1065238500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1887575 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1069525000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485020678 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485192198 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728403365 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728416355 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 136784 # Transaction distribution -system.membus.trans_dist::Writeback 97872 # Transaction distribution -system.membus.trans_dist::CleanEvict 30200 # Transaction distribution +system.membus.trans_dist::ReadResp 137050 # Transaction distribution +system.membus.trans_dist::Writeback 97878 # Transaction distribution +system.membus.trans_dist::CleanEvict 30539 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8283 # Transaction distribution -system.membus.trans_dist::ReadExResp 8283 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 136784 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 418218 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15548096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15548096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8386 # Transaction distribution +system.membus.trans_dist::ReadExResp 8386 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 137050 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 419301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 419301 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15572096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15572096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273145 # Request fanout histogram +system.membus.snoop_fanout::samples 273859 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273145 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 273859 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273145 # Request fanout histogram -system.membus.reqLayer0.occupancy 717072511 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 273859 # Request fanout histogram +system.membus.reqLayer0.occupancy 740935905 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 756625908 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 757820949 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 493c10cfc..d6d64bb1d 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770277 # Number of seconds simulated -sim_ticks 770277033000 # Number of ticks simulated -final_tick 770277033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.770368 # Number of seconds simulated +sim_ticks 770368138000 # Number of ticks simulated +final_tick 770368138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139677 # Simulator instruction rate (inst/s) -host_op_rate 150481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69657391 # Simulator tick rate (ticks/s) -host_mem_usage 313196 # Number of bytes of host memory used -host_seconds 11058.08 # Real time elapsed on the host +host_inst_rate 139680 # Simulator instruction rate (inst/s) +host_op_rate 150484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69667014 # Simulator tick rate (ticks/s) +host_mem_usage 312136 # Number of bytes of host memory used +host_seconds 11057.86 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238802560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63353600 # Number of bytes read from this memory -system.physmem.bytes_read::total 302222208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104930816 # Number of bytes written to this memory -system.physmem.bytes_written::total 104930816 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1032 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3731290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 989900 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4722222 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1639544 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1639544 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 85746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310021654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82247811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392355211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 85746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136224776 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136224776 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136224776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 85746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310021654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82247811 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528579987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4722222 # Number of read requests accepted -system.physmem.writeReqs 1639544 # Number of write requests accepted -system.physmem.readBursts 4722222 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1639544 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301770432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 451776 # Total number of bytes read from write queue -system.physmem.bytesWritten 104928448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302222208 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104930816 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7059 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 65792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238160448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63905024 # Number of bytes read from this memory +system.physmem.bytes_read::total 302131264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104870272 # Number of bytes written to this memory +system.physmem.bytes_written::total 104870272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3721257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 998516 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4720801 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1638598 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1638598 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309151477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82953877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 392190758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136130074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136130074 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136130074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309151477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82953877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 528320833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4720801 # Number of read requests accepted +system.physmem.writeReqs 1638598 # Number of write requests accepted +system.physmem.readBursts 4720801 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1638598 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301683008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448256 # Total number of bytes read from write queue +system.physmem.bytesWritten 104867648 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302131264 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104870272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7004 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 297173 # Per bank write bursts -system.physmem.perBankRdBursts::1 295012 # Per bank write bursts -system.physmem.perBankRdBursts::2 289245 # Per bank write bursts -system.physmem.perBankRdBursts::3 293018 # Per bank write bursts -system.physmem.perBankRdBursts::4 289731 # Per bank write bursts -system.physmem.perBankRdBursts::5 289594 # Per bank write bursts -system.physmem.perBankRdBursts::6 284433 # Per bank write bursts -system.physmem.perBankRdBursts::7 281274 # Per bank write bursts -system.physmem.perBankRdBursts::8 297880 # Per bank write bursts -system.physmem.perBankRdBursts::9 304149 # Per bank write bursts -system.physmem.perBankRdBursts::10 295533 # Per bank write bursts -system.physmem.perBankRdBursts::11 302217 # Per bank write bursts -system.physmem.perBankRdBursts::12 302962 # Per bank write bursts -system.physmem.perBankRdBursts::13 302377 # Per bank write bursts -system.physmem.perBankRdBursts::14 297334 # Per bank write bursts -system.physmem.perBankRdBursts::15 293231 # Per bank write bursts -system.physmem.perBankWrBursts::0 104274 # Per bank write bursts -system.physmem.perBankWrBursts::1 102166 # Per bank write bursts -system.physmem.perBankWrBursts::2 99582 # Per bank write bursts -system.physmem.perBankWrBursts::3 100201 # Per bank write bursts -system.physmem.perBankWrBursts::4 99226 # Per bank write bursts -system.physmem.perBankWrBursts::5 98958 # Per bank write bursts -system.physmem.perBankWrBursts::6 102876 # Per bank write bursts -system.physmem.perBankWrBursts::7 104542 # Per bank write bursts -system.physmem.perBankWrBursts::8 105498 # Per bank write bursts -system.physmem.perBankWrBursts::9 104632 # Per bank write bursts -system.physmem.perBankWrBursts::10 102325 # Per bank write bursts -system.physmem.perBankWrBursts::11 102766 # Per bank write bursts -system.physmem.perBankWrBursts::12 102939 # Per bank write bursts -system.physmem.perBankWrBursts::13 102535 # Per bank write bursts -system.physmem.perBankWrBursts::14 104418 # Per bank write bursts -system.physmem.perBankWrBursts::15 102569 # Per bank write bursts +system.physmem.perBankRdBursts::0 296472 # Per bank write bursts +system.physmem.perBankRdBursts::1 294660 # Per bank write bursts +system.physmem.perBankRdBursts::2 288575 # Per bank write bursts +system.physmem.perBankRdBursts::3 292960 # Per bank write bursts +system.physmem.perBankRdBursts::4 290749 # Per bank write bursts +system.physmem.perBankRdBursts::5 289530 # Per bank write bursts +system.physmem.perBankRdBursts::6 284828 # Per bank write bursts +system.physmem.perBankRdBursts::7 280913 # Per bank write bursts +system.physmem.perBankRdBursts::8 297084 # Per bank write bursts +system.physmem.perBankRdBursts::9 304004 # Per bank write bursts +system.physmem.perBankRdBursts::10 295272 # Per bank write bursts +system.physmem.perBankRdBursts::11 301446 # Per bank write bursts +system.physmem.perBankRdBursts::12 303554 # Per bank write bursts +system.physmem.perBankRdBursts::13 302544 # Per bank write bursts +system.physmem.perBankRdBursts::14 297853 # Per bank write bursts +system.physmem.perBankRdBursts::15 293353 # Per bank write bursts +system.physmem.perBankWrBursts::0 103842 # Per bank write bursts +system.physmem.perBankWrBursts::1 101847 # Per bank write bursts +system.physmem.perBankWrBursts::2 99335 # Per bank write bursts +system.physmem.perBankWrBursts::3 100097 # Per bank write bursts +system.physmem.perBankWrBursts::4 99287 # Per bank write bursts +system.physmem.perBankWrBursts::5 99035 # Per bank write bursts +system.physmem.perBankWrBursts::6 102669 # Per bank write bursts +system.physmem.perBankWrBursts::7 104576 # Per bank write bursts +system.physmem.perBankWrBursts::8 105230 # Per bank write bursts +system.physmem.perBankWrBursts::9 104522 # Per bank write bursts +system.physmem.perBankWrBursts::10 102176 # Per bank write bursts +system.physmem.perBankWrBursts::11 103126 # Per bank write bursts +system.physmem.perBankWrBursts::12 103102 # Per bank write bursts +system.physmem.perBankWrBursts::13 102725 # Per bank write bursts +system.physmem.perBankWrBursts::14 104361 # Per bank write bursts +system.physmem.perBankWrBursts::15 102627 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770276886500 # Total gap between requests +system.physmem.totGap 770367991500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4722222 # Read request sizes (log2) +system.physmem.readPktSize::6 4720801 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1639544 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2779707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1048806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 331545 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 150885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 195 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1638598 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2785137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1045602 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 327608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 232677 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 151173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 83865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 38451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 821 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 100036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 23398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 106693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 114123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 105280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,121 +197,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4293402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.726038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.887603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.441683 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3419558 79.65% 79.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676188 15.75% 95.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96097 2.24% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35320 0.82% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22691 0.53% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12222 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7184 0.17% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5103 0.12% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19039 0.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4293402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98787 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.730481 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.341812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.609970 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94999 96.17% 96.17% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1343 1.36% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 771 0.78% 98.31% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 397 0.40% 98.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 383 0.39% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 367 0.37% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 255 0.26% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 139 0.14% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 71 0.07% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 36 0.04% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 14 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3968-4095 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98787 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98787 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.596384 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.562558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.102794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72931 73.83% 73.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1712 1.73% 75.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18497 18.72% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3886 3.93% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1013 1.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 377 0.38% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 169 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 93 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 49 0.05% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 46 0.05% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 4291005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.744514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.906714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.391830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3416666 79.62% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 676199 15.76% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96816 2.26% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35217 0.82% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22960 0.54% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11971 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7013 0.16% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5097 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19066 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4291005 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98697 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.759952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.369236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.446894 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 96231 97.50% 97.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1192 1.21% 98.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 746 0.76% 99.47% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 392 0.40% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 102 0.10% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 22 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 3 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98697 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.601893 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.567781 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.107607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 72640 73.60% 73.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1756 1.78% 75.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18593 18.84% 94.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3904 3.96% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1031 1.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 392 0.40% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 184 0.19% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 91 0.09% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 55 0.06% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 17 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98787 # Writes before turning the bus around for reads -system.physmem.totQLat 131372718643 # Total ticks spent queuing -system.physmem.totMemAccLat 219782024893 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23575815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27861.76 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98697 # Writes before turning the bus around for reads +system.physmem.totQLat 131099404549 # Total ticks spent queuing +system.physmem.totMemAccLat 219483098299 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23568985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27811.85 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46611.76 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.22 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46561.85 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 391.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.13 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 392.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.12 # Data bus utilization in percentage system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 1708262 # Number of row buffer hits during reads -system.physmem.writeRowHits 352995 # Number of row buffer hits during writes +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 1707890 # Number of row buffer hits during reads +system.physmem.writeRowHits 353447 # Number of row buffer hits during writes system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes -system.physmem.avgGap 121079.10 # Average gap between requests -system.physmem.pageHitRate 32.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16098316920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8783803875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18090555600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5260230720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409970854125 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102538812000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611052888360 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.296379 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168045428834 # Time in different power states -system.physmem_0.memoryStateTime::REF 25721020000 # Time in different power states +system.physmem.writeRowHitRate 21.57 # Row buffer hit rate for writes +system.physmem.avgGap 121138.49 # Average gap between requests +system.physmem.pageHitRate 32.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16077957840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8772695250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18085189200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5253161040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 410294660580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102310835250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 611110917000 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.275483 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 167665323859 # Time in different power states +system.physmem_0.memoryStateTime::REF 25724140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 576504578166 # Time in different power states +system.physmem_0.memoryStateTime::ACT 576975365641 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16359303240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8926207125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18686249400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5363152560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 411485095035 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101210530500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612340852980 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.968472 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165832482361 # Time in different power states -system.physmem_1.memoryStateTime::REF 25721020000 # Time in different power states +system.physmem_1.actEnergy 16361828280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8927584875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18681803400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5364480960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50316417840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 411044339970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101653218750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 612349674075 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.883504 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 166565047661 # Time in different power states +system.physmem_1.memoryStateTime::REF 25724140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 578718185889 # Time in different power states +system.physmem_1.memoryStateTime::ACT 578076556839 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286281176 # Number of BP lookups -system.cpu.branchPred.condPredicted 223407845 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631280 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158010784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150352507 # Number of BTB hits +system.cpu.branchPred.lookups 286273758 # Number of BP lookups +system.cpu.branchPred.condPredicted 223402774 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14629982 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157694112 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150348271 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.153320 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641956 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.341715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640713 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -430,128 +424,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540554067 # number of cpu cycles simulated +system.cpu.numCycles 1540736277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926810 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067510841 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286281176 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166994463 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1511903145 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29287205 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 944 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656946227 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540474684 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437849 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228901 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925194 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067435227 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286273758 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166988984 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1512088964 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284609 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1031 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656921798 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 960 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1540658157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.437628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228937 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458056876 29.73% 29.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465435106 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101413024 6.58% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515569678 33.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 458280922 29.75% 29.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465413379 30.21% 59.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101412163 6.58% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515551693 33.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540474684 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185830 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.342057 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74648924 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543079640 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849978540 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58124682 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642898 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42203677 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 755 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037193143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52473156 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642898 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139724503 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462464867 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13004 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837848817 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85780595 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976362381 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26752450 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45148759 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125663 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1475660 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 24911172 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985832580 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128057886 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432844380 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1540658157 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185803 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.341849 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74641640 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 543291473 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849963258 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58120186 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641600 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202380 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 756 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037144212 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52474408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641600 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139712786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 462567620 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14938 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837837029 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 85884184 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976322026 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26747258 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45146985 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125259 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1471751 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25027790 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985779948 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127891240 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432801848 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 139 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310933635 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 310881003 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 157 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111445716 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542550479 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199301883 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26937332 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29252722 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947933921 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.tempSerializingInsts 151 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111429534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542545285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199304809 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26862690 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28866621 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947900293 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857470724 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13498979 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283901721 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647143115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857514523 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13512332 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283868093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647012526 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540474684 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150877 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1540658157 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.205663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150942 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587582159 38.14% 38.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326005186 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378227465 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219635075 14.26% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29018612 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6187 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 587771265 38.15% 38.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326011747 21.16% 59.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378176386 24.55% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219651217 14.26% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29041357 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6185 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540474684 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1540658157 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166090735 41.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2011 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191466761 47.26% 88.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47541933 11.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166072420 40.95% 40.95% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2002 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191493456 47.22% 88.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47936528 11.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138243565 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801032 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138226056 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801017 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -573,90 +567,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532113978 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186312098 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532163815 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186323583 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857470724 # Type of FU issued -system.cpu.iq.rate 1.205716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405101440 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218093 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674016313 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231848584 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805694743 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 238 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262572030 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17810782 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857514523 # Type of FU issued +system.cpu.iq.rate 1.205602 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405504406 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218305 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5674703700 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231781287 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805692489 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 241 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 71 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2263018794 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 135 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17823551 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84244145 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13196 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24454838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84238951 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66626 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13177 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24457764 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4507141 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4884537 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4548930 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4887285 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642898 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25317454 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1284847 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947934221 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641600 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25334604 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1297189 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947900591 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542550479 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199301883 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542545285 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199304809 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159143 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1124751 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13196 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7700546 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704736 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16405282 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827804607 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516933891 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29666117 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159299 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1136868 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13177 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700706 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8703944 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16404650 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827845280 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516985272 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29669243 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 698685293 # number of memory reference insts executed -system.cpu.iew.exec_branches 229544445 # Number of branches executed -system.cpu.iew.exec_stores 181751402 # Number of stores executed -system.cpu.iew.exec_rate 1.186459 # Inst execution rate -system.cpu.iew.wb_sent 1808724876 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805694813 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169261823 # num instructions producing a value -system.cpu.iew.wb_consumers 1689660637 # num instructions consuming a value +system.cpu.iew.exec_nop 82 # number of nop insts executed +system.cpu.iew.exec_refs 698740184 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542491 # Number of branches executed +system.cpu.iew.exec_stores 181754912 # Number of stores executed +system.cpu.iew.exec_rate 1.186345 # Inst execution rate +system.cpu.iew.wb_sent 1808718850 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805692560 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169243952 # num instructions producing a value +system.cpu.iew.wb_consumers 1689620594 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172107 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692010 # average fanout of values written-back +system.cpu.iew.wb_rate 1.171967 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692016 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 258006259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257974948 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630576 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1500991330 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025694 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629278 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1501179372 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.108483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.025812 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920697347 61.34% 61.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250635150 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110066020 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55280178 3.68% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29318113 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34079049 2.27% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24716376 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18134019 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58065078 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 920919616 61.35% 61.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250623048 16.70% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110074231 7.33% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55314266 3.68% 89.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29240414 1.95% 91.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34051194 2.27% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24724968 1.65% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18102388 1.21% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58129247 3.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1500991330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1501179372 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -702,76 +696,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58065078 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3364964346 # The number of ROB reads -system.cpu.rob.rob_writes 3883565961 # The number of ROB writes -system.cpu.timesIdled 839 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79383 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58129247 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3365056908 # The number of ROB reads +system.cpu.rob.rob_writes 3883498749 # The number of ROB writes +system.cpu.timesIdled 826 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78120 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997404 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997404 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002602 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002602 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175788919 # number of integer regfile reads -system.cpu.int_regfile_writes 1261560913 # number of integer regfile writes +system.cpu.cpi 0.997522 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.997522 # CPI: Total CPI of All Threads +system.cpu.ipc 1.002484 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.002484 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175832090 # number of integer regfile reads +system.cpu.int_regfile_writes 1261554579 # number of integer regfile writes system.cpu.fp_regfile_reads 42 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965670330 # number of cc regfile reads -system.cpu.cc_regfile_writes 551865131 # number of cc regfile writes -system.cpu.misc_regfile_reads 675839076 # number of misc regfile reads +system.cpu.fp_regfile_writes 53 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965806989 # number of cc regfile reads +system.cpu.cc_regfile_writes 551858746 # number of cc regfile writes +system.cpu.misc_regfile_reads 675847493 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004565 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.965160 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638055083 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005077 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.521446 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77552500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.965160 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004655 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964606 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638048144 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17005167 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.520840 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 78823500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964606 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335687503 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335687503 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469335942 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469335942 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719023 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719023 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335675523 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335675523 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469328921 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469328921 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168719105 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168719105 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638054965 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638054965 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638054965 # number of overall hits -system.cpu.dcache.overall_hits::total 638054965 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17419100 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17419100 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867024 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867024 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638048026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638048026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638048026 # number of overall hits +system.cpu.dcache.overall_hits::total 638048026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17420086 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17420086 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3866942 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3866942 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21286124 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21286124 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21286126 # number of overall misses -system.cpu.dcache.overall_misses::total 21286126 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415512136500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149273741664 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 290000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 564785878164 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 564785878164 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 564785878164 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 564785878164 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486755042 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486755042 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21287028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21287028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21287030 # number of overall misses +system.cpu.dcache.overall_misses::total 21287030 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 415615381500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 415615381500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149888945711 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149888945711 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 398000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 398000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 565504327211 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 565504327211 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 565504327211 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 565504327211 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486749007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486749007 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -780,74 +774,74 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659341089 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659341089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659341091 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659341091 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659335054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659335054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659335056 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659335056 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035789 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035789 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032284 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032284 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032284 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032284 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26533.054029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26533.051536 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20783046 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3318451 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 945637 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67068 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.977827 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49.478902 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23858.400096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23858.400096 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38761.622417 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38761.622417 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26565.677802 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26565.677802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26565.675306 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26565.675306 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20779473 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3451346 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 944816 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67198 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.993143 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51.360844 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4838877 # number of writebacks -system.cpu.dcache.writebacks::total 4838877 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151642 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151642 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1129406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4837348 # number of writebacks +system.cpu.dcache.writebacks::total 4837348 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3152457 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3152457 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1129405 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737618 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737618 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281862 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281862 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281862 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281862 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267629 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14267629 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737537 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737537 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17005076 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17005076 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17005077 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005077 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17005166 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17005166 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17005167 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17005167 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335438494000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 335438494000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116411117573 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116411117573 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451904447017 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451904515017 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451849611573 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 451849611573 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451849679573 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 451849679573 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029312 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029312 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses @@ -856,358 +850,361 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23510.458115 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23510.458115 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42524.034405 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42524.034405 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26571.314363 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26571.314363 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26571.316799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26571.316799 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 585 # number of replacements -system.cpu.icache.tags.tagsinuse 445.973645 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656944607 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612250.332712 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 582 # number of replacements +system.cpu.icache.tags.tagsinuse 445.815002 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656920172 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1070 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 613944.085981 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.973645 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871042 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871042 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 445.815002 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.870732 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.870732 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313893525 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313893525 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656944607 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656944607 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656944607 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656944607 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656944607 # number of overall hits -system.cpu.icache.overall_hits::total 656944607 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1619 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1619 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1619 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1619 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1619 # number of overall misses -system.cpu.icache.overall_misses::total 1619 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 105131986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 105131986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 105131986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 105131986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 105131986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 105131986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656946226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656946226 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656946226 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656946226 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656946226 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656946226 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313844660 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313844660 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656920172 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656920172 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656920172 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656920172 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656920172 # number of overall hits +system.cpu.icache.overall_hits::total 656920172 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1623 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1623 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1623 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1623 # number of overall misses +system.cpu.icache.overall_misses::total 1623 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 104193985 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 104193985 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 104193985 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 104193985 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 104193985 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 104193985 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656921795 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656921795 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656921795 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656921795 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656921795 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656921795 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 64936.371834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 64936.371834 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17916 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 510 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 93.312500 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 63.750000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64198.388786 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64198.388786 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64198.388786 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64198.388786 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64198.388786 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17135 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 748 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.184211 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 503 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2303 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9259 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1857 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049500 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922607 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 551304223 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 551304223 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 4837348 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 4837348 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312623157999 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72748405464 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 385439731963 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358554 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358554 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.961789 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960748 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192014 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192014 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.218848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218801 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # 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average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95406.487057 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95406.487057 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66311.770428 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66311.770428 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79944.046391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79944.046391 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84016.629278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66311.770428 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84021.520924 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72631.323770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81602.334417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 14268485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6478421 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15219349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1327311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737665 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737665 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2727 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50995885 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398013056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1398081728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6041496 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40052798 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.150838 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.357891 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 14268653 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 6475946 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 15220389 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1280497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1070 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267583 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993396 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50996114 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397921024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397989504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 5993194 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 40004669 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.149812 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.356887 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 34011302 84.92% 84.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 6041496 15.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 34011476 85.02% 85.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 5993193 14.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40052798 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21844528998 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 40004669 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21843087497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1609500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1605000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507619991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25507754991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3740347 # Transaction distribution -system.membus.trans_dist::Writeback 1639544 # Transaction distribution -system.membus.trans_dist::CleanEvict 3065371 # Transaction distribution -system.membus.trans_dist::ReadExReq 981875 # Transaction distribution -system.membus.trans_dist::ReadExResp 981875 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3740347 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14149359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14149359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407153024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 407153024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3739456 # Transaction distribution +system.membus.trans_dist::Writeback 1638598 # Transaction distribution +system.membus.trans_dist::CleanEvict 3064906 # Transaction distribution +system.membus.trans_dist::ReadExReq 981345 # Transaction distribution +system.membus.trans_dist::ReadExResp 981345 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3739456 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14145106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14145106 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407001536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407001536 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9427137 # Request fanout histogram +system.membus.snoop_fanout::samples 9424305 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9427137 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9424305 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9427137 # Request fanout histogram -system.membus.reqLayer0.occupancy 17268043532 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9424305 # Request fanout histogram +system.membus.reqLayer0.occupancy 17323735553 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25679820043 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25676323677 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b441da851..b0d8b3c34 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085019 # Number of seconds simulated -sim_ticks 85018904000 # Number of ticks simulated -final_tick 85018904000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085022 # Number of seconds simulated +sim_ticks 85021523000 # Number of ticks simulated +final_tick 85021523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135768 # Simulator instruction rate (inst/s) -host_op_rate 143122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66991355 # Simulator tick rate (ticks/s) -host_mem_usage 315704 # Number of bytes of host memory used -host_seconds 1269.10 # Real time elapsed on the host +host_inst_rate 136979 # Simulator instruction rate (inst/s) +host_op_rate 144399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67591393 # Simulator tick rate (ticks/s) +host_mem_usage 315696 # Number of bytes of host memory used +host_seconds 1257.88 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 126976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71296 # Number of bytes read from this memory -system.physmem.bytes_read::total 246144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71104 # Number of bytes read from this memory +system.physmem.bytes_read::total 245888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 126976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 126976 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 1984 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1114 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3846 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 563075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 838590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2895168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 563075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 838590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2895168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3846 # Number of read requests accepted +system.physmem.num_reads::cpu.data 747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1111 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3842 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1493457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 562305 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 836306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2892068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1493457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1493457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1493457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 562305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 836306 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2892068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3842 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3846 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3842 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246144 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245888 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246144 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts system.physmem.perBankRdBursts::1 220 # Per bank write bursts -system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 309 # Per bank write bursts -system.physmem.perBankRdBursts::4 300 # Per bank write bursts +system.physmem.perBankRdBursts::2 134 # Per bank write bursts +system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 237 # Per bank write bursts +system.physmem.perBankRdBursts::7 232 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 291 # Per bank write bursts +system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts system.physmem.perBankRdBursts::12 193 # Per bank write bursts system.physmem.perBankRdBursts::13 211 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85018760500 # Total gap between requests +system.physmem.totGap 85021379500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3846 # Read request sizes (log2) +system.physmem.readPktSize::6 3842 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.211068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.877402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.919917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 237 30.50% 30.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 193 24.84% 55.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 10.81% 66.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 88 11.33% 77.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.50% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 40 5.15% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 20 2.57% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13 1.67% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 67 8.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 777 # Bytes accessed per row activation -system.physmem.totQLat 39111678 # Total ticks spent queuing -system.physmem.totMemAccLat 111224178 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10169.44 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 770 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.174026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 198.484323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.262764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 239 31.04% 31.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 194 25.19% 56.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 10.65% 66.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 86 11.17% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 28 3.64% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 38 4.94% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 1.95% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 2.08% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 72 9.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 770 # Bytes accessed per row activation +system.physmem.totQLat 41378240 # Total ticks spent queuing +system.physmem.totMemAccLat 113415740 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19210000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10769.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28919.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29519.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.71 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.89 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3067 # Number of row buffer hits during reads +system.physmem.readRowHits 3065 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22105761.96 # Average gap between requests -system.physmem.pageHitRate 79.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2744280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1497375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16231800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22129458.49 # Average gap between requests +system.physmem.pageHitRate 79.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2766960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1509750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2336092560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48961790250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56871322905 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.930183 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81450773508 # Time in different power states +system.physmem_0.actBackEnergy 2338310430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48959844750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56871567930 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.933066 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81449206260 # Time in different power states system.physmem_0.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 728623992 # Time in different power states +system.physmem_0.memoryStateTime::ACT 731844740 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13712400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3039120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1658250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13579800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 5552966640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2289194100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49002929250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56863639980 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.839816 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81519548908 # Time in different power states +system.physmem_1.actBackEnergy 2293221150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48999396750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56863861710 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.842424 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81513735655 # Time in different power states system.physmem_1.memoryStateTime::REF 2838940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 659848592 # Time in different power states +system.physmem_1.memoryStateTime::ACT 665661845 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85912123 # Number of BP lookups -system.cpu.branchPred.condPredicted 68393040 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6015536 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40101118 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39014565 # Number of BTB hits +system.cpu.branchPred.lookups 85912132 # Number of BP lookups +system.cpu.branchPred.condPredicted 68393043 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6015535 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40101121 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.290467 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 97.290465 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3703090 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 81902 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,95 +381,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170037809 # number of cpu cycles simulated +system.cpu.numCycles 170043047 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5613511 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349250633 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85912123 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42717654 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158261511 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12044973 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5613517 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349250630 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85912132 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42717657 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158263984 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12044969 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2368 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78950648 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169901476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150563 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78950646 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 18010 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169904018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150531 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047148 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17358895 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30204196 17.78% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31835534 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90502851 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17361437 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30204201 17.78% 28.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31835536 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90502844 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169901476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505253 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053959 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17563828 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17110473 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122657456 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6722156 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5847563 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11134699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190129 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306600036 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27639970 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5847563 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37745979 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8468798 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579877 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108923634 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8335625 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278650711 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13412582 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051453 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842711 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2185712 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 35165 # Number of times rename has blocked due to SQ full +system.cpu.fetch.rateDist::total 169904018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053895 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17563904 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17112948 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122657441 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722163 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5847562 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11134700 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190128 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306600022 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27639979 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5847562 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37746058 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8470500 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579781 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108923622 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8336495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278650706 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13412569 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051463 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842712 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2185705 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 36039 # Number of times rename has blocked due to SQ full system.cpu.rename.FullRegisterEvents 26489 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483080894 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196921588 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297573906 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 483080897 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196921555 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297573893 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3006747 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190103965 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 190103968 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 23523 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 23430 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13336347 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34142095 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476543 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2549376 # Number of conflicting loads. +system.cpu.rename.skidInsts 13336341 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34142087 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476532 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549378 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1793123 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 264810332 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 45855 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214902718 # Number of instructions issued +system.cpu.iq.iqInstsIssued 214902707 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 5190620 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 83220233 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219925398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 219925371 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 639 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169901476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264867 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 169904018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264848 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017464 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52832101 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36093158 21.24% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65784259 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13574357 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1570220 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47195 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52834646 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36093194 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65784220 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13574325 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570253 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47194 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 186 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169901476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169904018 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605011 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35605027 66.11% 66.11% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 152712 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available @@ -494,16 +494,16 @@ system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdFloatCmp 35741 0.07% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 239 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1037 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1038 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 34404 0.06% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078469 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945889 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078476 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3945873 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167344164 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167344168 77.87% 77.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 918970 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued @@ -532,84 +532,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 460547 0.21% 78.75% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32006921 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373534 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32006913 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13373527 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214902718 # Type of FU issued -system.cpu.iq.rate 1.263853 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53854775 # FU busy when requested +system.cpu.iq.FU_type_0::total 214902707 # Type of FU issued +system.cpu.iq.rate 1.263814 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53854783 # FU busy when requested system.cpu.iq.fu_busy_rate 0.250601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654798543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 654801069 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 346070765 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204597394 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953764 # Number of floating instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 204597399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953766 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2012584 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 1806443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266623027 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134466 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1601141 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 266623022 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134468 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1601145 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6245951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7537 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 6245943 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7536 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1831909 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1831898 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 25713 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 804 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 795 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5847563 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681873 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37049 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 5847562 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681846 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37059 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 264872174 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34142095 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476543 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 34142087 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476532 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 23447 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3919 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29963 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29973 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7067 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 3232804 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3246682 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 6479486 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207521850 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30720954 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7380868 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 207521845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720947 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380862 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 15987 # number of nop insts executed -system.cpu.iew.exec_refs 43860782 # number of memory reference insts executed -system.cpu.iew.exec_branches 44934590 # Number of branches executed -system.cpu.iew.exec_stores 13139828 # Number of stores executed -system.cpu.iew.exec_rate 1.220445 # Inst execution rate -system.cpu.iew.wb_sent 206738830 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206403837 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129472700 # num instructions producing a value -system.cpu.iew.wb_consumers 221699640 # num instructions consuming a value +system.cpu.iew.exec_refs 43860767 # number of memory reference insts executed +system.cpu.iew.exec_branches 44934593 # Number of branches executed +system.cpu.iew.exec_stores 13139820 # Number of stores executed +system.cpu.iew.exec_rate 1.220408 # Inst execution rate +system.cpu.iew.wb_sent 206738836 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206403842 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129472696 # num instructions producing a value +system.cpu.iew.wb_consumers 221699614 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213870 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584000 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213833 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584001 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69532932 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69532937 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 5840613 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158460459 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646701 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 158463001 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146327 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646694 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73681032 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276330 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22553900 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626912 6.08% 92.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73683575 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41276323 26.05% 72.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22553918 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9626893 6.08% 92.85% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 3550160 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2147757 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1281176 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147765 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1281178 0.81% 97.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 986541 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3356651 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3356648 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158460459 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158463001 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,34 +655,34 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3356651 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406281881 # The number of ROB reads -system.cpu.rob.rob_writes 513821502 # The number of ROB writes -system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 136333 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3356648 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406284431 # The number of ROB reads +system.cpu.rob.rob_writes 513821512 # The number of ROB writes +system.cpu.timesIdled 3435 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 139029 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986853 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986853 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013322 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013322 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218956398 # number of integer regfile reads -system.cpu.int_regfile_writes 114512064 # number of integer regfile writes +system.cpu.cpi 0.986884 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986884 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013291 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013291 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218956389 # number of integer regfile reads +system.cpu.int_regfile_writes 114512069 # number of integer regfile writes system.cpu.fp_regfile_reads 2904391 # number of floating regfile reads system.cpu.fp_regfile_writes 2441624 # number of floating regfile writes -system.cpu.cc_regfile_reads 709567727 # number of cc regfile reads -system.cpu.cc_regfile_writes 229536120 # number of cc regfile writes -system.cpu.misc_regfile_reads 59314176 # number of misc regfile reads +system.cpu.cc_regfile_reads 709567724 # number of cc regfile reads +system.cpu.cc_regfile_writes 229536137 # number of cc regfile writes +system.cpu.misc_regfile_reads 59314172 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72863 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.419653 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73375 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.346698 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504093500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.419653 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998867 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998867 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72862 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.418427 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115433 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73374 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.354254 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.418427 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id @@ -690,46 +690,46 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 229 system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82529747 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82529747 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729201 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729201 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341321 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341321 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529738 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529738 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729196 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729196 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341320 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341320 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41070522 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41070522 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41070883 # number of overall hits -system.cpu.dcache.overall_hits::total 41070883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89405 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22966 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22966 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 41070516 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070516 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41070877 # number of overall hits +system.cpu.dcache.overall_hits::total 41070877 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89406 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89406 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22967 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22967 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112371 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112371 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112488 # number of overall misses -system.cpu.dcache.overall_misses::total 112488 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 853901000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 853901000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 240852499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 240852499 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 112373 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112373 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112490 # number of overall misses +system.cpu.dcache.overall_misses::total 112490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 857195000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 857195000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 240069999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 240069999 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1094753499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1094753499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1094753499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1094753499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28818606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28818606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1097264999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1097264999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1097264999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1097264999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818602 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818602 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 478 # number of SoftPFReq accesses(hits+misses) @@ -738,14 +738,14 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41182893 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41182893 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183371 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183371 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41182889 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182889 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183367 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183367 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003102 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003102 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001858 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001858 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244770 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.244770 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses @@ -754,56 +754,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002729 system.cpu.dcache.demand_miss_rate::total 0.002729 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002731 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002731 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9550.931156 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9550.931156 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10487.350823 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10487.350823 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9587.667494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9587.667494 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10452.823573 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10452.823573 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9742.313399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9742.313399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9732.180313 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9732.180313 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9764.489682 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9764.489682 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9754.333710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9754.333710 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10552 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10364 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.198844 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 11.967667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 64850 # number of writebacks system.cpu.dcache.writebacks::total 64850 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24706 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24706 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14404 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14404 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24708 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24708 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14405 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39110 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39110 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39110 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39110 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64699 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64699 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 39113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64698 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64698 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8562 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 8562 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73261 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73261 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73375 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73375 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558347000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 558347000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85131499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85131499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 73260 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73260 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73374 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73374 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 560329500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85295999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85295999 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 970000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 970000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 643478499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 643478499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 644448499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 644448499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 645625499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 645625499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 646595499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 646595499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses @@ -814,221 +814,222 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8629.917000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8629.917000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9942.945457 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9942.945457 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8660.692757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8660.692757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9962.158257 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9962.158257 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8508.771930 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8508.771930 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8783.370402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8783.370402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8782.943768 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8782.943768 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8812.796874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8812.796874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8812.324515 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8812.324515 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 54433 # number of replacements -system.cpu.icache.tags.tagsinuse 510.604366 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78892637 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.603635 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78892635 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 54945 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.847429 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84263927500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.604366 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997274 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997274 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 1435.847393 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84266921500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.603635 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157956201 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157956201 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78892637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78892637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78892637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78892637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78892637 # number of overall hits -system.cpu.icache.overall_hits::total 78892637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57991 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57991 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57991 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57991 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57991 # number of overall misses -system.cpu.icache.overall_misses::total 57991 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 602655456 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 602655456 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 602655456 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 602655456 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 602655456 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 602655456 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78950628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78950628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78950628 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78950628 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78950628 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78950628 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 157956195 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157956195 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78892635 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78892635 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78892635 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78892635 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78892635 # number of overall hits +system.cpu.icache.overall_hits::total 78892635 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57990 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57990 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57990 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57990 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57990 # number of overall misses +system.cpu.icache.overall_misses::total 57990 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 602731956 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 602731956 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 602731956 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 602731956 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 602731956 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 602731956 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78950625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78950625 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78950625 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78950625 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78950625 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78950625 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000735 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000735 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000735 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000735 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000735 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000735 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10392.223897 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10392.223897 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10392.223897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10392.223897 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10392.223897 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 58612 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10393.722297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10393.722297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10393.722297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10393.722297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10393.722297 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 59431 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2849 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2848 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.572833 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.867626 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3046 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3046 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3046 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3046 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3046 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3046 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3045 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3045 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3045 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3045 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3045 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3045 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54945 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 54945 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 54945 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 54945 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 54945 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 54945 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 535420965 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 535420965 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 535420965 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 535420965 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 535420965 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 535420965 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 536017965 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 536017965 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 536017965 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 536017965 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 536017965 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 536017965 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9744.671308 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9744.671308 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9744.671308 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9744.671308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9744.671308 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9744.671308 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9755.536719 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9755.536719 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9755.536719 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9755.536719 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9755.536719 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9755.536719 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9365 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9365 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9423 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9423 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1339 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1377 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2660.276616 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 230314 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3583 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 64.279654 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2658.566262 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 230317 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3579 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 64.352333 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 701.934591 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.049531 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 421.061183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 161.231311 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042843 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 701.921035 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.043878 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 421.064959 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 159.536389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.042842 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.025700 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009841 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162370 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 261 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 155 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.162266 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 256 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 148 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 754 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015930 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202759 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3933865 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3933865 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015625 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202820 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3933845 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3933845 # Number of data accesses system.cpu.l2cache.Writeback_hits::writebacks 64850 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 64850 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8397 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8397 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52956 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 52956 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 64220 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 64220 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 52956 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72617 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8400 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8400 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 52955 # 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number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 234 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1990 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1990 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 522 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 522 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1990 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 756 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2746 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1990 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 756 # number of overall misses +system.cpu.l2cache.overall_misses::total 2746 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18159000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18159000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 136514500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 136514500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 39124000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 39124000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 136514500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 57283000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 193797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 136514500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 57283000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 193797500 # number of overall miss cycles system.cpu.l2cache.Writeback_accesses::writebacks 64850 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 64850 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 8634 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 8634 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 54945 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 54945 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64741 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 64741 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64740 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 64740 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 54945 # 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miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.008047 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.008047 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.010330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.021407 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.010330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.021407 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76008.438819 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76008.438819 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68331.573655 # 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number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 233 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 233 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1984 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1984 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 513 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 513 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 514 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 514 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1984 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2732 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 747 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2731 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1984 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1818 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4550 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70301588 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16173000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 123686500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 123686500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33594500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33594500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 123686500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49767500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 173454000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 123686500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49767500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70301588 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 243755588 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 747 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1827 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4558 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 69341141 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 69341141 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16554000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 124261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 124261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35586000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 124261000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52140000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 176401000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 124261000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52140000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 69341141 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245742141 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027218 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027218 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026986 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036109 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007924 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007924 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007939 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007939 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021291 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021283 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010194 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010181 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035458 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38669.740374 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68821.276596 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68821.276596 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62341.985887 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62341.985887 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65486.354776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65486.354776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63489.751098 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62341.985887 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66534.090909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38669.740374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53572.656703 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035521 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37953.552819 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71047.210300 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71047.210300 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62631.552419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62631.552419 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69233.463035 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69233.463035 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.090809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62631.552419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69799.196787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37953.552819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53914.467091 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 119686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119685 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 64850 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 51933 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2169 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 54945 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64741 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155973 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217447 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373421 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12362880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2160 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257776 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.008379 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.091155 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8846336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2169 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 257783 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.008414 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.091342 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 255616 99.16% 99.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2160 0.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 255614 99.16% 99.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2169 0.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257776 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192658000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 257783 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 192657000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82430973 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82431971 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110066991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110065491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3611 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3611 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7692 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7692 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246144 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3609 # Transaction distribution +system.membus.trans_dist::ReadExReq 233 # Transaction distribution +system.membus.trans_dist::ReadExResp 233 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3609 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7684 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7684 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3846 # Request fanout histogram +system.membus.snoop_fanout::samples 3842 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3846 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3842 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3846 # Request fanout histogram -system.membus.reqLayer0.occupancy 5081597 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3842 # Request fanout histogram +system.membus.reqLayer0.occupancy 4994667 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20277583 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20261553 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |