diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/long/se | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/long/se')
39 files changed, 17584 insertions, 17319 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 2f7887688..508ed63ed 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu sim_ticks 61241011500 # Number of ticks simulated final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252391 # Simulator instruction rate (inst/s) -host_op_rate 253648 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170598134 # Simulator tick rate (ticks/s) -host_mem_usage 450980 # Number of bytes of host memory used -host_seconds 358.98 # Real time elapsed on the host +host_inst_rate 266495 # Simulator instruction rate (inst/s) +host_op_rate 267822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180131185 # Simulator tick rate (ticks/s) +host_mem_usage 451088 # Number of bytes of host memory used +host_seconds 339.98 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 40 2.59% 51.26% # By system.physmem.bytesPerActivate::896-1023 47 3.05% 54.31% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 705 45.69% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1543 # Bytes accessed per row activation -system.physmem.totQLat 73241750 # Total ticks spent queuing -system.physmem.totMemAccLat 365254250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 73240250 # Total ticks spent queuing +system.physmem.totMemAccLat 365252750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.82 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4702.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.82 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23452.73 # Average memory access latency per DRAM burst system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 3440250 # En system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491477695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34557963000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41122783185 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.511702 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57480391250 # Time in different power states +system.physmem_0.actBackEnergy 2491483680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34557957750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41122783920 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.511714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57480384250 # Time in different power states system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713925750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1713932750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 5360040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2924625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2555146980 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34502112750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41122878195 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.513254 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57387655250 # Time in different power states +system.physmem_1.actBackEnergy 2555148690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34502111250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122878405 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.513257 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387653250 # Time in different power states system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1806574750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1806576750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 20752188 # Number of BP lookups system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted @@ -386,8 +386,8 @@ system.cpu.discardedOps 2176623 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.351856 # CPI: cycles per instruction system.cpu.ipc 0.739724 # IPC: instructions per cycle -system.cpu.tickCycles 109255164 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13226859 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 109255161 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226862 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946097 # number of replacements system.cpu.dcache.tags.tagsinuse 3616.872758 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. @@ -428,14 +428,14 @@ system.cpu.dcache.demand_misses::cpu.data 989217 # n system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses system.cpu.dcache.overall_misses::total 989221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11919048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2542627500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14461675500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14461675500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14461675500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11919046000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542633500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461679500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461679500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461679500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -460,14 +460,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.335544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.335544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.242627 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.242627 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.315580 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14619.315580 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.256465 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14619.256465 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.319624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.260509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,16 +496,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950190 system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865351000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481616500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481616500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865349000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481625500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481625500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12346967500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347124000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12347124000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12347131000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12347131000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -516,16 +516,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.843401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.166150 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.166150 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.209053 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.209053 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.332730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.332730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements system.cpu.icache.tags.tagsinuse 689.439811 # Cycle average of tags in use @@ -587,6 +587,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 5 # number of writebacks +system.cpu.icache.writebacks::total 5 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses @@ -613,12 +615,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536 system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10245.556298 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 10245.556296 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655412 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.655409 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444539 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456347 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy @@ -634,8 +636,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 943278 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits @@ -660,20 +664,22 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067673500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1067673500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067670500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067670500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 57597000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 21897000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 57597000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1089570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1147167500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089567500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1147164500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 57597000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1089570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1147167500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 943278 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943278 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.data 1089567500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1147164500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 943278 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46765 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) @@ -698,18 +704,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.894114 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.894114 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.794678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73621.325889 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,18 +746,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922233500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922233500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922230500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922230500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49710000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18946000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49710000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941179500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 990889500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941176500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 990886500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49710000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941179500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 990889500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941176500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 990886500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses @@ -764,18 +770,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.894114 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.894114 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.209459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.598690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1897097 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 946118 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -784,8 +790,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution @@ -793,22 +800,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012905 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1896781 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 316 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950829 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 950995 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891831500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -833,9 +840,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21741000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21739000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82130750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82131250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 6db072c1c..a88ddf684 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,116 +1,116 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058181 # Number of seconds simulated -sim_ticks 58181475500 # Number of ticks simulated -final_tick 58181475500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058178 # Number of seconds simulated +sim_ticks 58178156500 # Number of ticks simulated +final_tick 58178156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122946 # Simulator instruction rate (inst/s) -host_op_rate 123559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78962453 # Simulator tick rate (ticks/s) -host_mem_usage 448784 # Number of bytes of host memory used -host_seconds 736.82 # Real time elapsed on the host +host_inst_rate 123327 # Simulator instruction rate (inst/s) +host_op_rate 123942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79202629 # Simulator tick rate (ticks/s) +host_mem_usage 528964 # Number of bytes of host memory used +host_seconds 734.55 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 50176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 933312 # Number of bytes read from this memory -system.physmem.bytes_read::total 1027904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 28672 # Number of bytes written to this memory -system.physmem.bytes_written::total 28672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 784 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14583 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16061 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 448 # Number of write requests responded to by this memory -system.physmem.num_writes::total 448 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 763404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 862405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16041394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17667204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 763404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 763404 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 492803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 492803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 492803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 763404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 862405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16041394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18160007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16061 # Number of read requests accepted -system.physmem.writeReqs 448 # Number of write requests accepted -system.physmem.readBursts 16061 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 448 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1014144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 13760 # Total number of bytes read from write queue -system.physmem.bytesWritten 26688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1027904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 28672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 215 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 55744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 924288 # Number of bytes read from this memory +system.physmem.bytes_read::total 1024768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10048 # Number of bytes written to this memory +system.physmem.bytes_written::total 10048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 871 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14442 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 157 # Number of write requests responded to by this memory +system.physmem.num_writes::total 157 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 768948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 958160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15887200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17614309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 768948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 768948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 172711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 172711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 172711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 768948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 958160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15887200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17787019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16013 # Number of read requests accepted +system.physmem.writeReqs 157 # Number of write requests accepted +system.physmem.readBursts 16013 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1017152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 8064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1024832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1015 # Per bank write bursts -system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 960 # Per bank write bursts -system.physmem.perBankRdBursts::3 1024 # Per bank write bursts -system.physmem.perBankRdBursts::4 1064 # Per bank write bursts -system.physmem.perBankRdBursts::5 1138 # Per bank write bursts -system.physmem.perBankRdBursts::6 1126 # Per bank write bursts -system.physmem.perBankRdBursts::7 1116 # Per bank write bursts -system.physmem.perBankRdBursts::8 1048 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 56 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 1166 # Per bank write bursts +system.physmem.perBankRdBursts::1 919 # Per bank write bursts +system.physmem.perBankRdBursts::2 952 # Per bank write bursts +system.physmem.perBankRdBursts::3 1030 # Per bank write bursts +system.physmem.perBankRdBursts::4 1062 # Per bank write bursts +system.physmem.perBankRdBursts::5 1117 # Per bank write bursts +system.physmem.perBankRdBursts::6 1098 # Per bank write bursts +system.physmem.perBankRdBursts::7 1090 # Per bank write bursts +system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 947 # Per bank write bursts +system.physmem.perBankRdBursts::10 936 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 909 # Per bank write bursts -system.physmem.perBankRdBursts::13 891 # Per bank write bursts -system.physmem.perBankRdBursts::14 939 # Per bank write bursts -system.physmem.perBankRdBursts::15 932 # Per bank write bursts -system.physmem.perBankWrBursts::0 39 # Per bank write bursts +system.physmem.perBankRdBursts::12 905 # Per bank write bursts +system.physmem.perBankRdBursts::13 898 # Per bank write bursts +system.physmem.perBankRdBursts::14 901 # Per bank write bursts +system.physmem.perBankRdBursts::15 934 # Per bank write bursts +system.physmem.perBankWrBursts::0 7 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::2 6 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 10 # Per bank write bursts -system.physmem.perBankWrBursts::5 33 # Per bank write bursts -system.physmem.perBankWrBursts::6 78 # Per bank write bursts -system.physmem.perBankWrBursts::7 51 # Per bank write bursts -system.physmem.perBankWrBursts::8 44 # Per bank write bursts +system.physmem.perBankWrBursts::4 8 # Per bank write bursts +system.physmem.perBankWrBursts::5 12 # Per bank write bursts +system.physmem.perBankWrBursts::6 30 # Per bank write bursts +system.physmem.perBankWrBursts::7 2 # Per bank write bursts +system.physmem.perBankWrBursts::8 5 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 13 # Per bank write bursts -system.physmem.perBankWrBursts::11 2 # Per bank write bursts -system.physmem.perBankWrBursts::12 8 # Per bank write bursts -system.physmem.perBankWrBursts::13 25 # Per bank write bursts -system.physmem.perBankWrBursts::14 64 # Per bank write bursts -system.physmem.perBankWrBursts::15 39 # Per bank write bursts +system.physmem.perBankWrBursts::10 11 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 4 # Per bank write bursts +system.physmem.perBankWrBursts::13 16 # Per bank write bursts +system.physmem.perBankWrBursts::14 23 # Per bank write bursts +system.physmem.perBankWrBursts::15 2 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58181318500 # Total gap between requests +system.physmem.totGap 58178148000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16061 # Read request sizes (log2) +system.physmem.readPktSize::6 16013 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 448 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2513 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2533 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -148,26 +148,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -197,93 +197,90 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.533742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 297.285521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 435.040107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 621 31.75% 31.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 232 11.86% 43.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 86 4.40% 48.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 69 3.53% 51.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 2.51% 54.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 52 2.66% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 53 2.71% 59.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 2.35% 61.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 748 38.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 686.869565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 31.250235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3138.483903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 22 95.65% 95.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 4.35% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 23 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.130435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.125203 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.457697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21 91.30% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 4.35% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 4.35% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.physmem.totQLat 162337192 # Total ticks spent queuing -system.physmem.totMemAccLat 459449692 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10244.68 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 579.332201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 345.781267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 429.630743 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 460 26.03% 26.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 205 11.60% 37.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 93 5.26% 42.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 3.57% 46.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 2.60% 49.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 3.23% 52.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 50 2.83% 55.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 49 2.77% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 744 42.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2257.857143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 93.171857 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5824.405132 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 6 85.71% 85.71% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 14.29% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.physmem.totQLat 173222344 # Total ticks spent queuing +system.physmem.totMemAccLat 471216094 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79465000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10899.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28994.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.67 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.49 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29649.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.72 # Average write queue length when enqueuing -system.physmem.readRowHits 14167 # Number of row buffer hits during reads -system.physmem.writeRowHits 131 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.57 # Row buffer hit rate for writes -system.physmem.avgGap 3524218.21 # Average gap between requests -system.physmem.pageHitRate 87.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7983360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4356000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64662000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1438560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2503358775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32711543250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39093302265 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.947294 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54407827569 # Time in different power states -system.physmem_0.memoryStateTime::REF 1942720000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.20 # Average write queue length when enqueuing +system.physmem.readRowHits 14205 # Number of row buffer hits during reads +system.physmem.writeRowHits 38 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.00 # Row buffer hit rate for writes +system.physmem.avgGap 3597906.49 # Average gap between requests +system.physmem.pageHitRate 88.77 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7673400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4186875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65488800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2652037290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32576451750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39105711075 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.250549 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54182179525 # Time in different power states +system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1828586181 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2046707975 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6788880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3704250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58663800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1263600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2462347845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32747517750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39080246445 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.722887 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54468275483 # Time in different power states -system.physmem_1.memoryStateTime::REF 1942720000 # Time in different power states +system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58141200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 395280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2310125355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32876366250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39053220225 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.348359 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54689145986 # Time in different power states +system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1768727017 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1544922014 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257355 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279453 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837859 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842476 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784812 # Number of BTB hits +system.cpu.branchPred.lookups 28257532 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279536 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837837 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842353 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513075 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513163 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75800 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,83 +400,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116362952 # number of cpu cycles simulated +system.cpu.numCycles 116356314 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748921 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134986415 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257355 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860572 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114720736 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679131 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 953 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 835 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32301690 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 580 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116311010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.319039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748715 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134987552 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257532 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860500 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114713884 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679087 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32302381 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 573 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116303952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58740461 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13941673 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230825 7.94% 70.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398051 29.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58732386 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942591 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230864 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398111 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116311010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242838 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160046 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839998 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64050748 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034874 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558063 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101313 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12342 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114429656 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996969 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15281198 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49893829 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109582 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35425015 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14774059 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898152 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1415674 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11131476 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1144261 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1527056 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 488175 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129955893 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483270095 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119473614 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 428 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116303952 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242853 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160122 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839872 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64043721 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33034735 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558318 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827306 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101307 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114430502 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996250 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15281424 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49886472 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35424721 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774664 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110898746 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1414946 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132654 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143672 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1526966 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 487708 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483272295 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119473751 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22642974 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21507084 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812785 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5349554 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 517855 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 254082 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109689870 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101387714 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074676 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18657087 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41688114 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116311010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989305 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21508806 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812600 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5350060 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 518904 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253933 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109691142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101388881 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075842 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18658360 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41690770 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116303952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54670243 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31362294 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008143 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7072499 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197518 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54663353 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31360946 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22009705 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7071580 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1198055 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,44 +484,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116311010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116303952 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9794091 48.69% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9615955 47.81% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 703739 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9787032 48.68% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614737 47.82% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 704136 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984145 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71984931 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued @@ -546,90 +543,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 52 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343095 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049585 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343463 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049594 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101387714 # Type of FU issued -system.cpu.iq.rate 0.871306 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20113848 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198385 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340274513 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128355901 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99625297 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 449 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 614 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 111 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121501328 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 234 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 290500 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101388881 # Type of FU issued +system.cpu.iq.rate 0.871366 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20105968 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198305 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340263064 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128358435 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121494609 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 289420 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336874 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1516 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336689 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604710 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 605216 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7564 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130574 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130752 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8118136 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109710785 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8114677 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 684104 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109712059 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812785 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5349554 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 179049 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342646 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 26812600 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5350060 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178830 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342365 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436655 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412870 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849525 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100126849 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806470 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1260865 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 436596 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412868 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849464 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100127809 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806782 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261072 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12668 # number of nop insts executed -system.cpu.iew.exec_refs 28724380 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624234 # Number of branches executed -system.cpu.iew.exec_stores 4917910 # Number of stores executed -system.cpu.iew.exec_rate 0.860470 # Inst execution rate -system.cpu.iew.wb_sent 99710000 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99625408 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703416 # num instructions producing a value -system.cpu.iew.wb_consumers 95544446 # num instructions consuming a value +system.cpu.iew.exec_nop 12669 # number of nop insts executed +system.cpu.iew.exec_refs 28724706 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624810 # Number of branches executed +system.cpu.iew.exec_stores 4917924 # Number of stores executed +system.cpu.iew.exec_rate 0.860528 # Inst execution rate +system.cpu.iew.wb_sent 99710755 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626115 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59703966 # num instructions producing a value +system.cpu.iew.wb_consumers 95545842 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.856161 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624876 # average fanout of values written-back +system.cpu.iew.wb_rate 0.856216 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17385130 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384633 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825621 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113618734 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801396 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737990 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825600 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113611791 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801445 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737925 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77195687 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18614563 16.38% 84.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7151371 6.29% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3466253 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1641564 1.44% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 544784 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704352 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179993 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120167 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77186972 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18613328 16.38% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152554 6.30% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3469014 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644498 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541954 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704210 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178949 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120312 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113618734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113611791 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -675,78 +672,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120167 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217931602 # The number of ROB reads -system.cpu.rob.rob_writes 219570402 # The number of ROB writes -system.cpu.timesIdled 589 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 51942 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120312 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217924017 # The number of ROB reads +system.cpu.rob.rob_writes 219569293 # The number of ROB writes +system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52362 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284504 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284504 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778511 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778511 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111563 # number of integer regfile reads -system.cpu.int_regfile_writes 58701013 # number of integer regfile writes -system.cpu.fp_regfile_reads 59 # number of floating regfile reads +system.cpu.cpi 1.284431 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284431 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778555 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778555 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108111974 # number of integer regfile reads +system.cpu.int_regfile_writes 58701043 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369063684 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693489 # number of cc regfile writes -system.cpu.misc_regfile_reads 28414952 # number of misc regfile reads +system.cpu.cc_regfile_reads 369066936 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693781 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415091 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470194 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.787648 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18251935 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470706 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336303 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 35373500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.787648 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999585 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999585 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5470182 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784909 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18253071 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470694 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336518 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61908668 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61908668 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13889868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13889868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353786 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353786 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61911082 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61911082 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13891036 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13891036 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353748 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353748 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18243654 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18243654 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18244176 # number of overall hits -system.cpu.dcache.overall_hits::total 18244176 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585829 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585829 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381195 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381195 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18244784 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18244784 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18245306 # number of overall hits +system.cpu.dcache.overall_hits::total 18245306 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381233 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381233 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967024 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967024 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967031 # number of overall misses -system.cpu.dcache.overall_misses::total 9967031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88721011000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88721011000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4006916840 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4006916840 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967114 # number of overall misses +system.cpu.dcache.overall_misses::total 9967114 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88735069500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88735069500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002231848 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4002231848 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92727927840 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92727927840 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92727927840 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92727927840 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23475697 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23475697 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92737301348 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92737301348 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92737301348 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92737301348 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23476910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23476910 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -755,298 +752,310 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28210678 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28210678 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28211207 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28211207 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408330 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080506 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080506 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28211891 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28211891 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28212420 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28212420 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408311 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408311 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353307 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353307 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353300 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353300 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9255.434350 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9255.434350 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10511.462218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10511.462218 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353295 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353295 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353288 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353288 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.857486 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.857486 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10498.125419 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10498.125419 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9303.471913 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9303.471913 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9303.465379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9303.465379 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329844 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 111014 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121439 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12836 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.716129 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.648644 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.334884 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9304.334884 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.328349 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9304.328349 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 329976 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 109342 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121408 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12843 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717910 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.513743 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5433212 # number of writebacks -system.cpu.dcache.writebacks::total 5433212 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337614 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337614 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158708 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158708 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5470182 # number of writebacks +system.cpu.dcache.writebacks::total 5470182 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4337666 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158748 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158748 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496322 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496322 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496322 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496322 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248215 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248215 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222487 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222487 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496414 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470706 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43247632500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43247632500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285123725 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285123725 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470693 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470693 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470697 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470697 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43256008000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43256008000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285824228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285824228 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45532756225 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45532756225 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45532970725 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45532970725 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223559 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223559 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45541832228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45541832228 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45542046728 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45542046728 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223548 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193923 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193923 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193920 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8240.446037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8240.446037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10270.819082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10270.819082 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.052906 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.052906 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.059950 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.059950 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8323.018915 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8323.018915 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8323.052038 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8323.052038 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.691630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.691630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.724752 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.724752 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 451 # number of replacements -system.cpu.icache.tags.tagsinuse 428.507470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32300517 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35495.073626 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 452 # number of replacements +system.cpu.icache.tags.tagsinuse 428.759370 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32301211 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35456.872667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.507470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836929 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836929 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.759370 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64604262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64604262 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32300517 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32300517 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32300517 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32300517 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32300517 # number of overall hits -system.cpu.icache.overall_hits::total 32300517 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses -system.cpu.icache.overall_misses::total 1159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62258984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62258984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62258984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62258984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62258984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62258984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32301676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32301676 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32301676 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32301676 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32301676 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32301676 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64605645 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64605645 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32301211 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32301211 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32301211 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32301211 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32301211 # number of overall hits +system.cpu.icache.overall_hits::total 32301211 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1156 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1156 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1156 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1156 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1156 # number of overall misses +system.cpu.icache.overall_misses::total 1156 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53717.846419 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53717.846419 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18998 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 136 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 221 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53048.858997 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53048.858997 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53048.858997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53048.858997 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18977 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85.963801 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.342222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50293988 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50293988 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50293988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50293988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50293988 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50293988 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 452 # number of writebacks +system.cpu.icache.writebacks::total 452 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50084985 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50084985 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50084985 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50084985 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50084985 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50084985 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55268.118681 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55268.118681 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55268.118681 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55268.118681 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54917.746711 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54917.746711 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4980719 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5295706 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 273829 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4981768 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296904 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 273976 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074518 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 620 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12071.188165 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10691146 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 16060 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 665.700249 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14074864 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 212 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11227.859430 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5316692 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14883 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 357.232547 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11063.420038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 575.029353 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 219.514162 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 213.224612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035097 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.013398 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.736767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 266 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 22 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1064 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13065 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016235 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926147 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175272147 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175272147 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 5433212 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5433212 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226010 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226010 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 215 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 215 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243682 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243682 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 215 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469692 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469907 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 215 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469692 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469907 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 42306000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47939000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 47939000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30597000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30597000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47939000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 72903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 120842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47939000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 72903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 120842000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 5433212 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5433212 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.occ_blocks::writebacks 11063.435293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 164.424136 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675259 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685294 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 174 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3710 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 891 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010620 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884827 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180497662 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180497662 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 5453533 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 5453533 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14185 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14185 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 226016 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 226016 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 211 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243612 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5243612 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469628 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469839 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5469628 # number of overall hits +system.cpu.l2cache.overall_hits::total 5469839 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 503 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 503 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 563 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 563 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1066 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1767 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1066 # number of overall misses +system.cpu.l2cache.overall_misses::total 1767 # number of overall misses +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 68000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41269500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47748000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47748000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38694000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38694000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47748000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 79963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 127711500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47748000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 79963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 127711500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 5453533 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 5453533 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14185 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14185 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 910 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 910 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 5244187 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5470706 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5471616 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5470706 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5471616 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002247 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002247 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.763736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.763736 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000096 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000096 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.763736 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000185 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000312 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.763736 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000185 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000312 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83115.913556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83115.913556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68976.978417 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68976.978417 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60588.118812 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60588.118812 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70709.186659 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68976.978417 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71896.449704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70709.186659 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 912 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244175 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 5244175 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 912 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5470694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5471606 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 912 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5470694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5471606 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002221 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002221 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.768640 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.768640 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000107 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000107 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.768640 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000195 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000323 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.768640 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000195 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000323 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22666.666667 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82046.719682 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82046.719682 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68114.122682 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68114.122682 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68728.241563 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68728.241563 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68114.122682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75012.664165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72275.891341 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68114.122682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75012.664165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72275.891341 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1055,147 +1064,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 448 # number of writebacks -system.cpu.l2cache.writebacks::total 448 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 166 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 157 # number of writebacks +system.cpu.l2cache.writebacks::total 157 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 161 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 161 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 64 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 64 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 32 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 32 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 230 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 231 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 193 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 230 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 231 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 11 # number of CleanEvict MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20740 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 20740 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 343 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 343 # 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number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 848794725 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32842000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32842000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43715500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43715500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24991500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24991500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43715500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 57833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 101549000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43715500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 57833500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 848794725 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 950343725 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 193 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 194 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316256 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 316256 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 531 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 531 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1573 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316256 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 317829 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852114791 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852114791 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32658500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32658500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43494500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43494500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34061500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34061500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43494500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 66720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 110214500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43494500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 66720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852114791 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 962329291 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.762637 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000270 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.762637 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000143 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.767544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000101 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.004061 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 40925.493009 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95749.271137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95749.271137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62990.634006 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62990.634006 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 56670.068027 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 56670.068027 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68707.036536 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62990.634006 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73767.219388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 40925.493009 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42773.594608 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058087 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.383003 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95492.690058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95492.690058 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62135 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64145.951036 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64145.951036 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70066.433566 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3027.820907 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 10942261 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 6201 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 6201 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5245097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5433660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22620 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 10942243 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470651 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303048 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 5245086 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5453690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318131 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244187 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2259 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 697850752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 697908992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 23240 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10965501 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001098 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.033119 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244175 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16410940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700030528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700116992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319578 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791182 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052888 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224048 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10953460 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12041 0.11% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485204 94.72% 94.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305670 5.28% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10965501 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10904342500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1367495 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5791182 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10941755515 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 7525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1367997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206062992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206046991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15718 # Transaction distribution -system.membus.trans_dist::Writeback 448 # Transaction distribution -system.membus.trans_dist::CleanEvict 139 # Transaction distribution -system.membus.trans_dist::ReadExReq 343 # Transaction distribution -system.membus.trans_dist::ReadExResp 343 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15718 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32709 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32709 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1056576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1056576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 15672 # Transaction distribution +system.membus.trans_dist::WritebackDirty 157 # Transaction distribution +system.membus.trans_dist::CleanEvict 51 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 15673 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32243 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1034816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1034816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16648 # Request fanout histogram +system.membus.snoop_fanout::samples 16226 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16648 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16226 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16648 # Request fanout histogram -system.membus.reqLayer0.occupancy 28374711 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16226 # Request fanout histogram +system.membus.reqLayer0.occupancy 26763807 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 84025804 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83802056 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 8cbe9f760..5dc111e3a 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488536500 # Number of ticks simulated -final_tick 361488536500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.361598 # Number of seconds simulated +sim_ticks 361597758500 # Number of ticks simulated +final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117046 # Simulator instruction rate (inst/s) -host_op_rate 1117092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1656101101 # Simulator tick rate (ticks/s) -host_mem_usage 428664 # Number of bytes of host memory used -host_seconds 218.28 # Real time elapsed on the host +host_inst_rate 1135132 # Simulator instruction rate (inst/s) +host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1683423955 # Simulator tick rate (ticks/s) +host_mem_usage 429008 # Number of bytes of host memory used +host_seconds 214.80 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,17 +21,17 @@ system.physmem.bytes_inst_read::total 56256 # Nu system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 155623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2762444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 155623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 155576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2761610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 155576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2606034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2761610 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977073 # number of cpu cycles simulated +system.cpu.numCycles 723195517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -50,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977072.998000 # Number of busy cycles +system.cpu.num_busy_cycles 723195516.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -90,18 +90,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469029 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3562.412338 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366269500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469029 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 134409733500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.412338 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869730 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869730 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses @@ -126,16 +126,16 @@ system.cpu.dcache.demand_misses::cpu.data 939567 # n system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832738000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832738000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832738000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11614835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1320964000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 101000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 101000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12935799000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12935799000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12935799000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) @@ -156,16 +156,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.386401 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.386401 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.140399 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.140399 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13008.617281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13008.617281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28280.111325 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28280.111325 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 25250 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 25250 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13767.830288 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13767.830288 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -186,16 +186,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 939567 system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10720879000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1172292000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 90000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11893171000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11893171000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11893171000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10721978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1274254000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 97000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11996232000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11996232000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11996232000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12007.386401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12658.140399 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12658.140399 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12008.617281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27280.111325 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 24250 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 24250 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12767.830288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12767.830288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412972 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.404879 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412972 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 725.404879 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354202 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id @@ -246,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48389500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48389500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48389500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48389500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48389500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 54543500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 54543500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 54543500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 54543500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 54543500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -264,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54863.378685 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54863.378685 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54863.378685 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54863.378685 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61840.702948 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61840.702948 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61840.702948 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61840.702948 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,44 +278,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 25 # number of writebacks +system.cpu.icache.writebacks::total 25 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47507500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47507500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47507500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47507500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53661500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53661500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53661500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53661500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53863.378685 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53863.378685 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53863.378685 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60840.702948 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60840.702948 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60840.702948 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625106 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9729.320449 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813523 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.355896 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635584 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319455 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 8846.376929 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.627938 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 144.315582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.269970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.296915 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id @@ -325,8 +327,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15069916 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15069916 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 935266 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 935266 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 935266 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 25 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 25 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32147 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32147 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -351,20 +355,22 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 46150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8242500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 819160500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46150500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 819160500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 935266 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 935266 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 866736500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 52304000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9341500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 52304000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 876078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 928382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 52304000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 876078000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 928382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 935266 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 25 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 25 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46714 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 882 # number of ReadCleanReq accesses(hits+misses) @@ -389,18 +395,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52503.412969 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.192271 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.412969 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.192271 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.981797 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.224316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.981797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.224316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -421,18 +427,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 619097500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 37360500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6672500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 37360500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 625770000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 663130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 37360500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 625770000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 663130500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 721066500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43514000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7771500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 728838000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 772352000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43514000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 728838000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 772352000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311834 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadCleanReq accesses @@ -445,18 +451,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42503.412969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42503.412969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.192271 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.981797 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.981797 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.224316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1875953 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 935500 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -465,8 +471,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 233 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution @@ -474,22 +481,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1875953 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 940453 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000001 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.001033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.001031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1875951 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 940452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1875953 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1873242500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 940453 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1873267500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -514,9 +521,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15606000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15606500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 78018000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 78015000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 9774ca6b0..92e3ee5b5 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.061602 # Number of seconds simulated -sim_ticks 61602395500 # Number of ticks simulated -final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 61602281500 # Number of ticks simulated +final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109389 # Simulator instruction rate (inst/s) -host_op_rate 192617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42652748 # Simulator tick rate (ticks/s) -host_mem_usage 458300 # Number of bytes of host memory used -host_seconds 1444.28 # Real time elapsed on the host +host_inst_rate 108860 # Simulator instruction rate (inst/s) +host_op_rate 191684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42446103 # Simulator tick rate (ticks/s) +host_mem_usage 458164 # Number of bytes of host memory used +host_seconds 1451.31 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -18,41 +18,41 @@ system.physmem.bytes_read::cpu.data 1883136 # Nu system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory -system.physmem.bytes_written::total 11776 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory +system.physmem.bytes_written::total 12160 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory -system.physmem.num_writes::total 184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1036843 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30569201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31606044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1036843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1036843 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 191161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 191161 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 191161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1036843 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30569201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31797205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory +system.physmem.num_writes::total 190 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30422 # Number of read requests accepted -system.physmem.writeReqs 184 # Number of write requests accepted +system.physmem.writeReqs 190 # Number of write requests accepted system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1941952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 10304 # Total number of bytes written to DRAM +system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue +system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 24 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1928 # Per bank write bursts -system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::1 2059 # Per bank write bursts system.physmem.perBankRdBursts::2 2023 # Per bank write bursts system.physmem.perBankRdBursts::3 1928 # Per bank write bursts -system.physmem.perBankRdBursts::4 2026 # Per bank write bursts +system.physmem.perBankRdBursts::4 2025 # Per bank write bursts system.physmem.perBankRdBursts::5 1901 # Per bank write bursts system.physmem.perBankRdBursts::6 1952 # Per bank write bursts system.physmem.perBankRdBursts::7 1864 # Per bank write bursts @@ -65,12 +65,12 @@ system.physmem.perBankRdBursts::13 1800 # Pe system.physmem.perBankRdBursts::14 1818 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts system.physmem.perBankWrBursts::0 10 # Per bank write bursts -system.physmem.perBankWrBursts::1 82 # Per bank write bursts +system.physmem.perBankWrBursts::1 78 # Per bank write bursts system.physmem.perBankWrBursts::2 7 # Per bank write bursts system.physmem.perBankWrBursts::3 28 # Per bank write bursts system.physmem.perBankWrBursts::4 6 # Per bank write bursts system.physmem.perBankWrBursts::5 7 # Per bank write bursts -system.physmem.perBankWrBursts::6 13 # Per bank write bursts +system.physmem.perBankWrBursts::6 16 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61602210500 # Total gap between requests +system.physmem.totGap 61602096500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.writePktSize::6 190 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -151,13 +151,13 @@ system.physmem.wrQLenPdf::18 10 # Wh system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see @@ -193,186 +193,184 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.414401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 516.531797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.717070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 355 13.04% 13.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 240 8.82% 21.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 4.63% 26.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 120 4.41% 30.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 92 3.38% 34.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 131 4.81% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 110 4.04% 43.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 67 2.46% 45.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1481 54.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 132 4.85% 39.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 112 4.12% 43.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3364.888889 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 25.331779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10055.293027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.777778 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.765969 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.666667 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 132940250 # Total ticks spent queuing -system.physmem.totMemAccLat 701871500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4381.25 # Average queueing delay per DRAM burst +system.physmem.totQLat 133021500 # Total ticks spent queuing +system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23131.25 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.66 # Average write queue length when enqueuing -system.physmem.readRowHits 27667 # Number of row buffer hits during reads -system.physmem.writeRowHits 105 # Number of row buffer hits during writes +system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing +system.physmem.readRowHits 27659 # Number of row buffer hits during reads +system.physmem.writeRowHits 106 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes -system.physmem.avgGap 2012749.48 # Average gap between requests -system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined +system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes +system.physmem.avgGap 2012351.25 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_0.readEnergy 121984200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 984960 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2832436305 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34473777000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41469338730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.233237 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57335755750 # Time in different power states +system.physmem_0.actBackEnergy 2835924705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34470717000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469713850 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.239327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57330547250 # Time in different power states system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2206091250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2211196750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3020027580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34309215000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481571815 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.431985 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57061184750 # Time in different power states +system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.432024 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2480864750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480893250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 36908902 # Number of BP lookups -system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted +system.cpu.branchPred.lookups 36908905 # Number of BP lookups +system.cpu.branchPred.condPredicted 36908905 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits +system.cpu.branchPred.BTBLookups 21094596 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21013333 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5443329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 5443330 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123204792 # number of cpu cycles simulated +system.cpu.numCycles 123204564 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27815548 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 199030226 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36908902 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26456661 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94542157 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1553197 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5286 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27815555 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 199030250 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36908905 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26456663 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94541896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1553195 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 366 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5275 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27443892 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 182896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123139971 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.847273 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.366420 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 27443897 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182895 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123139703 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.847279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366421 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62945586 51.12% 51.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3649644 2.96% 54.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3480667 2.83% 56.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5913875 4.80% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7544210 6.13% 67.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5413973 4.40% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3251113 2.64% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2020097 1.64% 76.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 28920806 23.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62945303 51.12% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3649645 2.96% 54.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3480674 2.83% 56.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5913881 4.80% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7544216 6.13% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5413971 4.40% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3251108 2.64% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2020095 1.64% 76.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28920810 23.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 123139703 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.615442 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8529193 # Number of cycles rename is blocking +system.cpu.fetch.rate 1.615445 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12941515 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63708297 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 35887575 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9825719 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 776597 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 331225446 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 776597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18253426 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8529207 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55361210 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 325142958 # Number of instructions processed by rename +system.cpu.rename.RunCycles 40202725 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55360957 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142954 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48626800 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4947589 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 327068190 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 863737834 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 532004035 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 778303 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48626694 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947433 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068188 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737810 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004029 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47855443 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 47855441 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 492 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66412234 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49402348 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322302018 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued +system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63884608 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30260078 24.57% 24.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19566758 15.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16687037 13.55% 54.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17331221 14.07% 68.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14759373 11.99% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12567435 10.21% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6273256 5.09% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30259811 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566759 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687041 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331203 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759381 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567446 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273248 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3904177 3.17% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1790637 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123139703 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 338800 8.53% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available @@ -401,12 +399,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3433516 86.49% 95.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197610 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174121950 56.88% 56.89% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued @@ -439,80 +437,80 @@ system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Ty system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued -system.cpu.iq.rate 2.484506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3969922 # FU busy when requested +system.cpu.iq.FU_type_0::total 306103027 # Type of FU issued +system.cpu.iq.rate 2.484510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3969927 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 739361486 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 310039423 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 310039433 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 58196288 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 4729640 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 141544 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3100559 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 776597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5329160 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3100599 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322303732 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3102582 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 414776 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 786455 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305156727 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97750586 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 946300 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed -system.cpu.iew.exec_branches 31401847 # Number of branches executed +system.cpu.iew.exec_refs 131430384 # number of memory reference insts executed +system.cpu.iew.exec_branches 31401849 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed -system.cpu.iew.exec_rate 2.476825 # Inst execution rate -system.cpu.iew.wb_sent 304565840 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 230213925 # num instructions producing a value -system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value +system.cpu.iew.exec_rate 2.476830 # Inst execution rate +system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back +system.cpu.iew.wb_producers 230213909 # num instructions producing a value +system.cpu.iew.wb_consumers 333860979 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle +system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117118936 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.375299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.092759 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52926112 45.19% 45.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15815584 13.50% 58.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8749335 7.47% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1860124 1.59% 77.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1720771 1.47% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 865932 0.74% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 690108 0.59% 79.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52925822 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815600 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10978628 9.37% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749337 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860126 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720772 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865935 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690105 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23512611 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117118936 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -558,73 +556,73 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23512617 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 416008734 # The number of ROB reads -system.cpu.rob.rob_writes 650833809 # The number of ROB writes +system.cpu.commit.bw_lim_events 23512611 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 416008479 # The number of ROB reads +system.cpu.rob.rob_writes 650833820 # The number of ROB writes system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 64861 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads -system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 491477122 # number of integer regfile reads -system.cpu.int_regfile_writes 239432260 # number of integer regfile writes +system.cpu.cpi 0.779832 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.779832 # CPI: Total CPI of All Threads +system.cpu.ipc 1.282327 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.282327 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 491477132 # number of integer regfile reads +system.cpu.int_regfile_writes 239432261 # number of integer regfile writes system.cpu.fp_regfile_reads 110 # number of floating regfile reads system.cpu.fp_regfile_writes 84 # number of floating regfile writes -system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads +system.cpu.cc_regfile_reads 107533030 # number of cc regfile reads system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes -system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads +system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 2072313 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68071048 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.783063 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 630 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 143788667 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 143788667 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 36725223 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 36725223 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345824 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345824 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68071047 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68071047 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68071047 # number of overall hits -system.cpu.dcache.overall_hits::total 68071047 # number of overall hits +system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345825 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68071037 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits +system.cpu.dcache.overall_hits::total 68071037 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93928 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93928 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2785082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2785082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2785082 # number of overall misses -system.cpu.dcache.overall_misses::total 2785082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304507500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304507500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956593494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2956593494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35261100994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35261100994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35261100994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35261100994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses +system.cpu.dcache.overall_misses::total 2785081 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses @@ -633,19 +631,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.960940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.960940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.232497 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.232497 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.704781 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.704781 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.704781 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221514 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.630694 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.125029 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124387 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -653,12 +651,12 @@ system.cpu.dcache.writebacks::writebacks 2066601 # nu system.cpu.dcache.writebacks::total 2066601 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11884 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 708672 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 708672 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 708672 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 708672 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 708671 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses @@ -667,14 +665,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196144500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196144500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799371995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799371995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995516495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995516495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995516495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995516495 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195993500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195993500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995390495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995390495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995390495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995390495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -683,68 +681,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.248795 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.248795 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.374372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.374372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.053017 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.053017 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements -system.cpu.icache.tags.tagsinuse 825.039934 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27442574 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 27090.398815 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 825.039934 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.402852 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 825.039758 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.402851 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.402851 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54888798 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54888798 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27442569 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27442569 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27442569 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27442569 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27442569 # number of overall hits -system.cpu.icache.overall_hits::total 27442569 # number of overall hits +system.cpu.icache.tags.tag_accesses 54888808 # Number of tag accesses +system.cpu.icache.tags.data_accesses 54888808 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27442574 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27442574 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27442574 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27442574 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27442574 # number of overall hits +system.cpu.icache.overall_hits::total 27442574 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1323 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1323 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1323 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1323 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1323 # number of overall misses system.cpu.icache.overall_misses::total 1323 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 97144000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 97144000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 97144000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 97144000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 97144000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 97144000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27443892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27443892 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27443892 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27443892 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27443892 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27443892 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 97204000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 97204000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 97204000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 97204000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 97204000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 97204000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27443897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27443897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27443897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27443897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27443897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27443897 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73427.059713 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73427.059713 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73427.059713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73427.059713 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73427.059713 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73472.411187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73472.411187 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,6 +751,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 53 # number of writebacks +system.cpu.icache.writebacks::total 53 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits @@ -765,49 +765,51 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 1014 system.cpu.icache.demand_mshr_misses::total 1014 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1014 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 77391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 77391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 77391000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 77418000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 77418000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 77418000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 77418000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 77418000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 77418000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76322.485207 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76322.485207 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76322.485207 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76322.485207 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 487 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.335726 # Cycle average of tags in use +system.cpu.l2cache.tags.replacements 493 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20712.318868 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30405 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.711824 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30411 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.685640 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19791.576352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917522 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.603991 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 780 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27629 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27623 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33310467 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33310467 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2066601 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066601 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 33310473 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33310473 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 53 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 53071 # number of ReadExReq hits @@ -834,20 +836,22 @@ system.cpu.l2cache.demand_misses::total 30422 # nu system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses system.cpu.l2cache.overall_misses::total 30422 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118128500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2118128500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75694000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 75694000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32848500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32848500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 75694000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2150977000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226671000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 75694000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2150977000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226671000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2066601 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066601 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32704000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32704000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226559000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150842000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226559000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 53 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 # number of ReadExReq accesses(hits+misses) @@ -874,18 +878,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73043.951307 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73043.951307 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75845.691383 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75845.691383 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77109.154930 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77109.154930 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73192.788114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75845.691383 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73102.807232 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73192.788114 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73189.106568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73189.106568 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -894,10 +898,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks -system.cpu.l2cache.writebacks::total 184 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 190 # number of writebacks +system.cpu.l2cache.writebacks::total 190 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses @@ -910,20 +912,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30422 system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828148500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65714000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65714000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28588500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28588500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65714000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856737000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922451000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65714000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856737000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922451000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28444000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28444000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856602000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922339000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856602000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922339000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses @@ -936,18 +936,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63043.951307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63043.951307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65845.691383 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65845.691383 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67109.154930 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67109.154930 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65845.691383 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63102.807232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63192.788114 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -956,8 +956,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5974 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution @@ -967,39 +968,39 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 487 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.009390 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 493 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4149911 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 366 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) system.membus.trans_dist::ReadResp 1424 # Transaction distribution -system.membus.trans_dist::Writeback 184 # Transaction distribution -system.membus.trans_dist::CleanEvict 30 # Transaction distribution +system.membus.trans_dist::WritebackDirty 190 # Transaction distribution +system.membus.trans_dist::CleanEvict 24 # Transaction distribution system.membus.trans_dist::ReadExReq 28998 # Transaction distribution system.membus.trans_dist::ReadExResp 28998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 30636 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram @@ -1011,9 +1012,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42746000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index d05ee6d96..ff948a783 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365988859500 # Number of ticks simulated -final_tick 365988859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366199 # Number of seconds simulated +sim_ticks 366199170500 # Number of ticks simulated +final_tick 366199170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563395 # Simulator instruction rate (inst/s) -host_op_rate 992048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1305133674 # Simulator tick rate (ticks/s) -host_mem_usage 455224 # Number of bytes of host memory used -host_seconds 280.42 # Real time elapsed on the host +host_inst_rate 639917 # Simulator instruction rate (inst/s) +host_op_rate 1126791 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1483253517 # Simulator tick rate (ticks/s) +host_mem_usage 455604 # Number of bytes of host memory used +host_seconds 246.89 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,21 +25,21 @@ system.physmem.num_reads::cpu.data 29241 # Nu system.physmem.num_reads::total 30044 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 102 # Number of write requests responded to by this memory system.physmem.num_writes::total 102 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 140420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5113336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 5253756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 140420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 140420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5113336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5271592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 140339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5110399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 5250738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 140339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17826 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 140339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5110399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5268565 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731977719 # number of cpu cycles simulated +system.cpu.numCycles 732398341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731977718.998000 # Number of busy cycles +system.cpu.num_busy_cycles 732398340.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -100,18 +100,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488591 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.299825 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079705500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488591 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 126122344500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.299825 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995190 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1779 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2195 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses @@ -132,14 +132,14 @@ system.cpu.dcache.demand_misses::cpu.data 2066829 # n system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498474000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498474000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598457000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598457000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28096931000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28096931000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28096931000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28096931000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25499993500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2801625000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28301618500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28301618500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28301618500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) @@ -156,14 +156,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.648292 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.648292 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.563647 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.563647 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.221389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.221389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.221389 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13005.423263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13005.423263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26403.273992 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26403.273992 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13693.255949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13693.255949 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23537754000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23537754000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492348000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492348000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26030102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26030102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26030102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26030102000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23539273500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2695516000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26234789500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26234789500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26234789500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses @@ -198,24 +198,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12004.648292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12004.648292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23488.563647 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23488.563647 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12594.221389 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12594.221389 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12005.423263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25403.273992 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12693.255949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12693.255949 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632473 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.627299 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632473 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 665.627299 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.325013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.325013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44233500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44233500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44233500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44233500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44233500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44233500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49857000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49857000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49857000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49857000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49857000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54744.430693 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54744.430693 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54744.430693 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54744.430693 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54744.430693 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61704.207921 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61704.207921 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61704.207921 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61704.207921 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -267,44 +267,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 24 # number of writebacks +system.cpu.icache.writebacks::total 24 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43425500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43425500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43425500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43425500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43425500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43425500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 49049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 49049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 49049000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53744.430693 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53744.430693 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53744.430693 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53744.430693 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60704.207921 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60704.207921 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60704.207921 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 313 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.891909 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20037.622351 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992697 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30021 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.996802 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19329.043320 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.394677 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 156.453912 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.589876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016980 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 19324.712224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 556.457266 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 156.452862 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.589743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.016982 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.611500 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id @@ -314,8 +316,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27876 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 33179282 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 33179282 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2062482 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2062482 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2062482 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 24 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 24 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 77085 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 77085 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5 # number of ReadCleanReq hits @@ -340,20 +344,22 @@ system.cpu.l2cache.demand_misses::total 30044 # nu system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29241 # number of overall misses system.cpu.l2cache.overall_misses::total 30044 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42159500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 42159500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11392500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11392500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42159500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1535183500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1577343000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42159500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1535183500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1577343000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2062482 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2062482 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1726959000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47782000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 12911500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47782000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1739870500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1787652500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47782000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1739870500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1787652500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2062482 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 24 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 24 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 106109 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 808 # number of ReadCleanReq accesses(hits+misses) @@ -378,18 +384,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.014531 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014148 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014531 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52502.490660 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52502.490660 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.098389 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.490660 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.060155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.098389 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59504.358655 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.148316 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59504.358655 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.060155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.148316 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,18 +418,18 @@ system.cpu.l2cache.demand_mshr_misses::total 30044 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29241 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30044 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1233551000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1233551000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34129500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34129500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9222500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9222500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34129500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1242773500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1276903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34129500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1242773500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1276903000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1436719000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39752000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10741500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39752000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1447460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1487212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39752000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1447460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1487212500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.273530 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadCleanReq accesses @@ -436,18 +442,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014531 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014148 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014531 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42501.068082 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42502.490660 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42502.490660 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42502.490660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.060155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.098389 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.068082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49504.358655 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49504.358655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.060155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.148316 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4130394 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2062757 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 197 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 197 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2062584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 486 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2062584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 462 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 808 # Transaction distribution @@ -465,29 +472,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1960720 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6196391 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 6198031 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53248 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 264275904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 264327616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 264329152 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 313 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4130707 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000048 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.006906 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2067950 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000095 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009760 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4130510 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 197 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2067753 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4130707 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4127679000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2067950 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4127703000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadResp 1020 # Transaction distribution -system.membus.trans_dist::Writeback 102 # Transaction distribution +system.membus.trans_dist::WritebackDirty 102 # Transaction distribution system.membus.trans_dist::CleanEvict 14 # Transaction distribution system.membus.trans_dist::ReadExReq 29024 # Transaction distribution system.membus.trans_dist::ReadExResp 29024 # Transaction distribution @@ -509,9 +516,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 30160 # Request fanout histogram -system.membus.reqLayer0.occupancy 30601000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 30602500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 150253000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 150220000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 91596dbee..168253993 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.412080 # Number of seconds simulated -sim_ticks 412080064500 # Number of ticks simulated -final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412076 # Number of seconds simulated +sim_ticks 412076211500 # Number of ticks simulated +final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310711 # Simulator instruction rate (inst/s) -host_op_rate 310711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209245414 # Simulator tick rate (ticks/s) -host_mem_usage 301844 # Number of bytes of host memory used -host_seconds 1969.36 # Real time elapsed on the host +host_inst_rate 332870 # Simulator instruction rate (inst/s) +host_op_rate 332870 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 224166223 # Simulator tick rate (ticks/s) +host_mem_usage 300688 # Number of bytes of host memory used +host_seconds 1838.26 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24123968 # Number of bytes read from this memory -system.physmem.bytes_read::total 24294848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory -system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 376937 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379607 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 414677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58541944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58956621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 414677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 414677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45577007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45577007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45577007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 414677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58541944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104533628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379607 # Number of read requests accepted -system.physmem.writeReqs 293459 # Number of write requests accepted -system.physmem.readBursts 379607 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24271744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23104 # Total number of bytes read from write queue -system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24294848 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 361 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 156480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24143168 # Number of bytes read from this memory +system.physmem.bytes_read::total 24299648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790784 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377237 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379682 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293606 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293606 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 379736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58589085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58968820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 379736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 379736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45600264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45600264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45600264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 379736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58589085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104569084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379682 # Number of read requests accepted +system.physmem.writeReqs 293606 # Number of write requests accepted +system.physmem.readBursts 379682 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293606 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24277120 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22528 # Total number of bytes read from write queue +system.physmem.bytesWritten 18788736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24299648 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23711 # Per bank write bursts -system.physmem.perBankRdBursts::1 23184 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 23686 # Per bank write bursts +system.physmem.perBankRdBursts::1 23158 # Per bank write bursts system.physmem.perBankRdBursts::2 23442 # Per bank write bursts -system.physmem.perBankRdBursts::3 24496 # Per bank write bursts -system.physmem.perBankRdBursts::4 25435 # Per bank write bursts -system.physmem.perBankRdBursts::5 23571 # Per bank write bursts -system.physmem.perBankRdBursts::6 23637 # Per bank write bursts -system.physmem.perBankRdBursts::7 23952 # Per bank write bursts -system.physmem.perBankRdBursts::8 23149 # Per bank write bursts -system.physmem.perBankRdBursts::9 23951 # Per bank write bursts -system.physmem.perBankRdBursts::10 24706 # Per bank write bursts -system.physmem.perBankRdBursts::11 22760 # Per bank write bursts -system.physmem.perBankRdBursts::12 23713 # Per bank write bursts -system.physmem.perBankRdBursts::13 24379 # Per bank write bursts -system.physmem.perBankRdBursts::14 22720 # Per bank write bursts -system.physmem.perBankRdBursts::15 22440 # Per bank write bursts -system.physmem.perBankWrBursts::0 17781 # Per bank write bursts +system.physmem.perBankRdBursts::3 24500 # Per bank write bursts +system.physmem.perBankRdBursts::4 25445 # Per bank write bursts +system.physmem.perBankRdBursts::5 23568 # Per bank write bursts +system.physmem.perBankRdBursts::6 23655 # Per bank write bursts +system.physmem.perBankRdBursts::7 23906 # Per bank write bursts +system.physmem.perBankRdBursts::8 23193 # Per bank write bursts +system.physmem.perBankRdBursts::9 23982 # Per bank write bursts +system.physmem.perBankRdBursts::10 24711 # Per bank write bursts +system.physmem.perBankRdBursts::11 22783 # Per bank write bursts +system.physmem.perBankRdBursts::12 23721 # Per bank write bursts +system.physmem.perBankRdBursts::13 24390 # Per bank write bursts +system.physmem.perBankRdBursts::14 22740 # Per bank write bursts +system.physmem.perBankRdBursts::15 22450 # Per bank write bursts +system.physmem.perBankWrBursts::0 17782 # Per bank write bursts system.physmem.perBankWrBursts::1 17456 # Per bank write bursts -system.physmem.perBankWrBursts::2 17945 # Per bank write bursts -system.physmem.perBankWrBursts::3 18847 # Per bank write bursts +system.physmem.perBankWrBursts::2 17944 # Per bank write bursts +system.physmem.perBankWrBursts::3 18851 # Per bank write bursts system.physmem.perBankWrBursts::4 19513 # Per bank write bursts -system.physmem.perBankWrBursts::5 18587 # Per bank write bursts -system.physmem.perBankWrBursts::6 18727 # Per bank write bursts -system.physmem.perBankWrBursts::7 18653 # Per bank write bursts -system.physmem.perBankWrBursts::8 18413 # Per bank write bursts -system.physmem.perBankWrBursts::9 18933 # Per bank write bursts +system.physmem.perBankWrBursts::5 18590 # Per bank write bursts +system.physmem.perBankWrBursts::6 18777 # Per bank write bursts +system.physmem.perBankWrBursts::7 18659 # Per bank write bursts +system.physmem.perBankWrBursts::8 18440 # Per bank write bursts +system.physmem.perBankWrBursts::9 18941 # Per bank write bursts system.physmem.perBankWrBursts::10 19255 # Per bank write bursts -system.physmem.perBankWrBursts::11 18037 # Per bank write bursts -system.physmem.perBankWrBursts::12 18264 # Per bank write bursts -system.physmem.perBankWrBursts::13 18729 # Per bank write bursts -system.physmem.perBankWrBursts::14 17175 # Per bank write bursts -system.physmem.perBankWrBursts::15 17122 # Per bank write bursts +system.physmem.perBankWrBursts::11 18046 # Per bank write bursts +system.physmem.perBankWrBursts::12 18263 # Per bank write bursts +system.physmem.perBankWrBursts::13 18731 # Per bank write bursts +system.physmem.perBankWrBursts::14 17195 # Per bank write bursts +system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412079976500 # Total gap between requests +system.physmem.totGap 412076182000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379607 # Read request sizes (log2) +system.physmem.readPktSize::6 379682 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 377839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1392 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293606 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 377941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1374 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,31 +144,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 40 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see @@ -193,39 +193,39 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.629870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.695929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.359961 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50814 35.72% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38804 27.28% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13098 9.21% 72.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8314 5.84% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5760 4.05% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3818 2.68% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2956 2.08% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2613 1.84% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16081 11.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142258 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17331 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.881888 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 237.076982 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17323 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142335 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.556532 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.740913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.275213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50726 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38947 27.36% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13162 9.25% 72.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8307 5.84% 78.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5691 4.00% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3798 2.67% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3047 2.14% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2540 1.78% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16117 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142335 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17335 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.880819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 236.752171 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17326 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17331 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17331 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.931337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.860812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.636907 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17131 98.85% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 149 0.86% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.17% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17335 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17335 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.935333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.864235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.642113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17130 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 152 0.88% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 27 0.16% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 6 0.03% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads @@ -235,87 +235,87 @@ system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17331 # Writes before turning the bus around for reads -system.physmem.totQLat 4068932250 # Total ticks spent queuing -system.physmem.totMemAccLat 11179794750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10729.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17335 # Writes before turning the bus around for reads +system.physmem.totQLat 4058081750 # Total ticks spent queuing +system.physmem.totMemAccLat 11170519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896650000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10698.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29479.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.96 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29448.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.97 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing -system.physmem.readRowHits 314133 # Number of row buffer hits during reads -system.physmem.writeRowHits 216290 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes -system.physmem.avgGap 612243.04 # Average gap between requests -system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 548364600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 299206875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1493138400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62103866355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192770777250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285086241240 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.822973 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320142846250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing +system.physmem.readRowHits 314253 # Number of row buffer hits during reads +system.physmem.writeRowHits 216307 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes +system.physmem.avgGap 612035.54 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1492491000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 956130480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61976871495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192877504500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285065043090 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.784602 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320322978500 # Time in different power states +system.physmem_0.memoryStateTime::REF 13759980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78176682500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77989027750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527105880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287607375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1464957000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 945613440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59197387905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195320319750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 284658020790 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.783804 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324404039000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states +system.physmem_1.actEnergy 527491440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287817750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465854000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 945995760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26914520880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59032825200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195460001250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 284634506280 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.739793 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324635867250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13759980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73915489750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73676135250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 123917174 # Number of BP lookups -system.cpu.branchPred.condPredicted 87658941 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6214604 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71577859 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67272092 # Number of BTB hits +system.cpu.branchPred.lookups 123917200 # Number of BP lookups +system.cpu.branchPred.condPredicted 87658954 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6214605 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71577882 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67272105 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.984499 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15041850 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126019 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.984487 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15041853 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126020 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149344667 # DTB read hits -system.cpu.dtb.read_misses 549014 # DTB read misses +system.cpu.dtb.read_hits 149344669 # DTB read hits +system.cpu.dtb.read_misses 549013 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149893681 # DTB read accesses +system.cpu.dtb.read_accesses 149893682 # DTB read accesses system.cpu.dtb.write_hits 57319597 # DTB write hits system.cpu.dtb.write_misses 63704 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 57383301 # DTB write accesses -system.cpu.dtb.data_hits 206664264 # DTB hits -system.cpu.dtb.data_misses 612718 # DTB misses +system.cpu.dtb.data_hits 206664266 # DTB hits +system.cpu.dtb.data_misses 612717 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207276982 # DTB accesses -system.cpu.itb.fetch_hits 226051197 # ITB hits +system.cpu.dtb.data_accesses 207276983 # DTB accesses +system.cpu.itb.fetch_hits 226051267 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226051245 # ITB accesses +system.cpu.itb.fetch_accesses 226051315 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,24 +329,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 824160129 # number of cpu cycles simulated +system.cpu.numCycles 824152423 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12834592 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12834608 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346883 # CPI: cycles per instruction -system.cpu.ipc 0.742455 # IPC: instructions per cycle -system.cpu.tickCycles 739333640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 84826489 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.346871 # CPI: cycles per instruction +system.cpu.ipc 0.742462 # IPC: instructions per cycle +system.cpu.tickCycles 739334528 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84817895 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 2535265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.660702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202570424 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4087.660624 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202570425 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2539361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.772204 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.772205 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1635033500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660624 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -355,16 +355,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414584973 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414584973 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146904267 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146904267 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 414584975 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414584975 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146904268 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146904268 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 55666157 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 55666157 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202570424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202570424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202570424 # number of overall hits -system.cpu.dcache.overall_hits::total 202570424 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 202570425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202570425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202570425 # number of overall hits +system.cpu.dcache.overall_hits::total 202570425 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1908505 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1908505 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1543877 # number of WriteReq misses @@ -373,22 +373,22 @@ system.cpu.dcache.demand_misses::cpu.data 3452382 # n system.cpu.dcache.demand_misses::total 3452382 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3452382 # number of overall misses system.cpu.dcache.overall_misses::total 3452382 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37715152000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37715152000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47725761500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47725761500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85440913500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85440913500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85440913500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85440913500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148812772 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148812772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37724666000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37724666000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47726490500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47726490500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85451156500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85451156500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85451156500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85451156500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148812773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148812773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206022806 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206022806 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206022806 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206022806 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206022807 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206022807 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206022807 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206022807 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses @@ -397,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19761.620745 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19761.620745 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30912.929916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30912.929916 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24748.395021 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24748.395021 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24751.361958 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24751.361958 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,8 +413,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2339622 # number of writebacks -system.cpu.dcache.writebacks::total 2339622 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2339407 # number of writebacks +system.cpu.dcache.writebacks::total 2339407 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143967 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 143967 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits @@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2539361 system.cpu.dcache.demand_mshr_misses::total 2539361 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2539361 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2539361 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33198964500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33198964500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344010000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56542974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56542974500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56542974500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56542974500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33207035500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33207035500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344377500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344377500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56551413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56551413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56551413000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56551413000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -447,69 +447,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18814.536440 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18814.536440 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.184114 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.184114 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3153 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.819230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226046216 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4981 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45381.693636 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3156 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.812774 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226046283 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4984 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45354.390650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.819230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545322 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545322 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.812774 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545319 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545319 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1828 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 452107375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 452107375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226046216 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226046216 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226046216 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226046216 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226046216 # number of overall hits -system.cpu.icache.overall_hits::total 226046216 # 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number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226046283 # number of overall hits +system.cpu.icache.overall_hits::total 226046283 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4984 # number of overall misses +system.cpu.icache.overall_misses::total 4984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 231170500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 231170500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 231170500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 231170500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 231170500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 231170500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226051267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226051267 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226051267 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226051267 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226051267 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226051267 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49281.670347 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49281.670347 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49281.670347 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49281.670347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49281.670347 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49281.670347 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46382.524077 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46382.524077 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,129 +518,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4981 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4981 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4981 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4981 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 240491000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 240491000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 240491000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 240491000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 240491000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 240491000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 3156 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48281.670347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48281.670347 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45382.524077 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45382.524077 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45382.524077 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 45382.524077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45382.524077 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 45382.524077 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 346897 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29502.927026 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3908665 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379320 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.304400 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189124044500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21307.222747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 177.805871 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8017.898409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.650245 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005426 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.244687 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8022.460164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.650692 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.244826 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900430 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32430 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13170 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18832 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,122 +655,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293459 # number of writebacks -system.cpu.l2cache.writebacks::total 293459 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 738 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 738 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206261 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206261 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2670 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2670 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68635.701853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68179.213483 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68179.213483 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70686.077714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70686.077714 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.490570 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097051 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149226 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.490570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149226 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68621.281082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68621.281082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68539.263804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68539.263804 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70630.219333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70630.219333 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68539.263804 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.535878 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5082760 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538418 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5082766 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538421 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2391 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2391 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249951 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4984 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761201 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13124 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312254912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 346897 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.020980 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 7627111 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 520960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312241152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312762112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 347699 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2892044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000827 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.028741 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5427266 99.96% 99.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2391 0.04% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2889653 99.92% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2391 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2892044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4883946000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7471500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7476000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3809041500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 173346 # Transaction distribution -system.membus.trans_dist::Writeback 293459 # Transaction distribution -system.membus.trans_dist::CleanEvict 51785 # Transaction distribution -system.membus.trans_dist::ReadExReq 206261 # Transaction distribution -system.membus.trans_dist::ReadExResp 206261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173346 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104458 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43076224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43076224 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 173372 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293606 # Transaction distribution +system.membus.trans_dist::CleanEvict 51706 # Transaction distribution +system.membus.trans_dist::ReadExReq 206310 # Transaction distribution +system.membus.trans_dist::ReadExResp 206310 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173372 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104676 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104676 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43090432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43090432 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 724851 # Request fanout histogram +system.membus.snoop_fanout::samples 724994 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 724851 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 724994 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 724851 # Request fanout histogram -system.membus.reqLayer0.occupancy 2020156500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 724994 # Request fanout histogram +system.membus.reqLayer0.occupancy 2020992000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2008875000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2009252250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 7a68c081f..232b217c8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363600 # Number of seconds simulated -sim_ticks 363599502500 # Number of ticks simulated -final_tick 363599502500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363578 # Number of seconds simulated +sim_ticks 363578056500 # Number of ticks simulated +final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226144 # Simulator instruction rate (inst/s) -host_op_rate 244944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 162315109 # Simulator tick rate (ticks/s) -host_mem_usage 321124 # Number of bytes of host memory used -host_seconds 2240.08 # Real time elapsed on the host +host_inst_rate 237399 # Simulator instruction rate (inst/s) +host_op_rate 257134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170382928 # Simulator tick rate (ticks/s) +host_mem_usage 321244 # Number of bytes of host memory used +host_seconds 2133.89 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9223936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6189376 # Number of bytes written to this memory -system.physmem.bytes_written::total 6189376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144124 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96709 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96709 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 603565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24764830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25368396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 603565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 603565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17022510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17022510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17022510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 603565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24764830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42390905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144124 # Number of read requests accepted -system.physmem.writeReqs 96709 # Number of write requests accepted -system.physmem.readBursts 144124 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96709 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9217920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue -system.physmem.bytesWritten 6188224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9223936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6189376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory +system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory +system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143938 # Number of read requests accepted +system.physmem.writeReqs 97172 # Number of write requests accepted +system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9331 # Per bank write bursts -system.physmem.perBankRdBursts::1 8969 # Per bank write bursts -system.physmem.perBankRdBursts::2 9003 # Per bank write bursts -system.physmem.perBankRdBursts::3 8675 # Per bank write bursts -system.physmem.perBankRdBursts::4 9453 # Per bank write bursts -system.physmem.perBankRdBursts::5 9352 # Per bank write bursts -system.physmem.perBankRdBursts::6 8945 # Per bank write bursts -system.physmem.perBankRdBursts::7 8102 # Per bank write bursts -system.physmem.perBankRdBursts::8 8582 # Per bank write bursts -system.physmem.perBankRdBursts::9 8674 # Per bank write bursts -system.physmem.perBankRdBursts::10 8765 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 9348 # Per bank write bursts -system.physmem.perBankRdBursts::13 9513 # Per bank write bursts -system.physmem.perBankRdBursts::14 8719 # Per bank write bursts -system.physmem.perBankRdBursts::15 9123 # Per bank write bursts -system.physmem.perBankWrBursts::0 6195 # Per bank write bursts -system.physmem.perBankWrBursts::1 6094 # Per bank write bursts -system.physmem.perBankWrBursts::2 6011 # Per bank write bursts -system.physmem.perBankWrBursts::3 5821 # Per bank write bursts -system.physmem.perBankWrBursts::4 6181 # Per bank write bursts -system.physmem.perBankWrBursts::5 6188 # Per bank write bursts -system.physmem.perBankWrBursts::6 6015 # Per bank write bursts -system.physmem.perBankWrBursts::7 5499 # Per bank write bursts -system.physmem.perBankWrBursts::8 5743 # Per bank write bursts -system.physmem.perBankWrBursts::9 5830 # Per bank write bursts -system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6463 # Per bank write bursts -system.physmem.perBankWrBursts::12 6312 # Per bank write bursts -system.physmem.perBankWrBursts::13 6285 # Per bank write bursts -system.physmem.perBankWrBursts::14 6003 # Per bank write bursts -system.physmem.perBankWrBursts::15 6086 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9337 # Per bank write bursts +system.physmem.perBankRdBursts::1 8920 # Per bank write bursts +system.physmem.perBankRdBursts::2 8993 # Per bank write bursts +system.physmem.perBankRdBursts::3 8670 # Per bank write bursts +system.physmem.perBankRdBursts::4 9385 # Per bank write bursts +system.physmem.perBankRdBursts::5 9354 # Per bank write bursts +system.physmem.perBankRdBursts::6 8954 # Per bank write bursts +system.physmem.perBankRdBursts::7 8104 # Per bank write bursts +system.physmem.perBankRdBursts::8 8602 # Per bank write bursts +system.physmem.perBankRdBursts::9 8629 # Per bank write bursts +system.physmem.perBankRdBursts::10 8738 # Per bank write bursts +system.physmem.perBankRdBursts::11 9458 # Per bank write bursts +system.physmem.perBankRdBursts::12 9338 # Per bank write bursts +system.physmem.perBankRdBursts::13 9514 # Per bank write bursts +system.physmem.perBankRdBursts::14 8722 # Per bank write bursts +system.physmem.perBankRdBursts::15 9109 # Per bank write bursts +system.physmem.perBankWrBursts::0 6210 # Per bank write bursts +system.physmem.perBankWrBursts::1 6096 # Per bank write bursts +system.physmem.perBankWrBursts::2 6031 # Per bank write bursts +system.physmem.perBankWrBursts::3 5885 # Per bank write bursts +system.physmem.perBankWrBursts::4 6239 # Per bank write bursts +system.physmem.perBankWrBursts::5 6240 # Per bank write bursts +system.physmem.perBankWrBursts::6 6045 # Per bank write bursts +system.physmem.perBankWrBursts::7 5507 # Per bank write bursts +system.physmem.perBankWrBursts::8 5786 # Per bank write bursts +system.physmem.perBankWrBursts::9 5860 # Per bank write bursts +system.physmem.perBankWrBursts::10 5977 # Per bank write bursts +system.physmem.perBankWrBursts::11 6497 # Per bank write bursts +system.physmem.perBankWrBursts::12 6353 # Per bank write bursts +system.physmem.perBankWrBursts::13 6323 # Per bank write bursts +system.physmem.perBankWrBursts::14 6005 # Per bank write bursts +system.physmem.perBankWrBursts::15 6089 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363599476500 # Total gap between requests +system.physmem.totGap 363578030500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144124 # Read request sizes (log2) +system.physmem.readPktSize::6 143938 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96709 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97172 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,124 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.912652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.372535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.914583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24788 37.96% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18406 28.19% 66.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6849 10.49% 76.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7905 12.11% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2084 3.19% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1111 1.70% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 761 1.17% 94.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 643 0.98% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2755 4.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65302 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.797421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.883100 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5579 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5583 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.318825 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.224966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.238810 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2516 45.07% 45.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 99 1.77% 46.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2663 47.70% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.92% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 38 0.68% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.32% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.25% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 8 0.14% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.11% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 9 0.16% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.09% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.07% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 4 0.07% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 6 0.11% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 4 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.04% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.04% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5583 # Writes before turning the bus around for reads -system.physmem.totQLat 1538433000 # Total ticks spent queuing -system.physmem.totMemAccLat 4238995500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10681.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads +system.physmem.totQLat 1537591000 # Total ticks spent queuing +system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29431.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.80 # Average write queue length when enqueuing -system.physmem.readRowHits 110870 # Number of row buffer hits during reads -system.physmem.writeRowHits 64542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.74 # Row buffer hit rate for writes -system.physmem.avgGap 1509757.70 # Average gap between requests -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248293080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135477375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560086800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310832640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47486002320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176502477750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248991396285 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.804658 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293320694250 # Time in different power states -system.physmem_0.memoryStateTime::REF 12141220000 # Time in different power states +system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing +system.physmem.readRowHits 110822 # Number of row buffer hits during reads +system.physmem.writeRowHits 64690 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes +system.physmem.avgGap 1507934.26 # Average gap between requests +system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.723644 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58133810750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245148120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133761375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562957200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315401040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23748226320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46957937220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176965692750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248929124025 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.633389 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294092512000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12141220000 # Time in different power states +system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.636777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states +system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57361058000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131895360 # Number of BP lookups -system.cpu.branchPred.condPredicted 98029927 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6139026 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68388068 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64396789 # Number of BTB hits +system.cpu.branchPred.lookups 131892190 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.163779 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9981632 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18119 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -429,98 +417,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727199005 # number of cpu cycles simulated +system.cpu.numCycles 727156113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13199573 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435501 # CPI: cycles per instruction -system.cpu.ipc 0.696621 # IPC: instructions per cycle -system.cpu.tickCycles 690715590 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36483415 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139984 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.789434 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168644 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144080 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.612478 # Average number of references to valid blocks. +system.cpu.cpi 1.435416 # CPI: cycles per instruction +system.cpu.ipc 0.696662 # IPC: instructions per cycle +system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139983 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789434 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3499 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346592332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346592332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114650184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114650184 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538625 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538625 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168188809 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168188809 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191562 # number of overall hits -system.cpu.dcache.overall_hits::total 168191562 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854786 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854786 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700681 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700681 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555482 # number of overall misses -system.cpu.dcache.overall_misses::total 1555482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024022500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14024022500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21893600500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21893600500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35917623000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35917623000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35917623000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35917623000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115504970 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115504970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits +system.cpu.dcache.overall_hits::total 168191146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses +system.cpu.dcache.overall_misses::total 1555406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2768 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2768 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169744276 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169744276 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169747044 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169747044 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005419 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005419 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.471912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.471912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31246.174079 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31246.174079 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23091.215050 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23091.215050 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.992374 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23090.992374 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,111 +517,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068583 # number of writebacks -system.cpu.dcache.writebacks::total 1068583 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344513 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344513 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411399 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411399 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411399 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411399 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787900 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787900 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356168 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356168 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144068 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144068 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144080 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144080 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337991000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337991000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11121217500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11121217500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 946000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 946000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23459208500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23459208500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23460154500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23460154500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks +system.cpu.dcache.writebacks::total 1068257 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004335 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004335 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.336210 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.336210 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31224.639777 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31224.639777 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78833.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20505.082303 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20505.082303 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20505.694095 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20505.694095 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17702 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.317648 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199314883 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19574 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10182.634260 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17711 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.317648 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580233 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580233 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 306 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398688488 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398688488 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199314883 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199314883 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199314883 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199314883 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199314883 # number of overall hits -system.cpu.icache.overall_hits::total 199314883 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19574 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19574 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19574 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19574 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19574 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199334457 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199334457 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits +system.cpu.icache.overall_hits::total 199302654 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19583 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19583 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19583 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19583 # number of overall misses +system.cpu.icache.overall_misses::total 19583 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 449788500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 449788500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 449788500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 449788500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 449788500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 449788500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199322237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199322237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199322237 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25101.333401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25101.333401 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25101.333401 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22968.314354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22968.314354 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -642,128 +630,134 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19574 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19574 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19574 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19574 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19574 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19574 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 471759500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 471759500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 471759500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 471759500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 471759500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 471759500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 17711 # number of writebacks +system.cpu.icache.writebacks::total 17711 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19583 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19583 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19583 # 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mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24101.333401 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24101.333401 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24101.333401 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24101.333401 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21968.314354 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111370 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27634.033642 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1767249 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.396702 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163253473000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23457.713364 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.652620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3786.667658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.715873 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011891 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.115560 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25857 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19030322 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19030322 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1068583 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068583 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255591 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255591 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16143 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16143 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747780 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2907247000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195877500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9809805000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10005682500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2321340 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157756 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4922 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2616 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 807234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1165292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98842 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19574 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787660 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56613 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141610432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142863168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432710 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.071609 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112366 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2420180 99.48% 99.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12527 0.51% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432710 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2229253000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29379463 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716126986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43295 # Transaction distribution -system.membus.trans_dist::Writeback 96709 # Transaction distribution -system.membus.trans_dist::CleanEvict 13242 # Transaction distribution -system.membus.trans_dist::ReadExReq 100829 # Transaction distribution -system.membus.trans_dist::ReadExResp 100829 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398199 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398199 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15413312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15413312 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43015 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution +system.membus.trans_dist::CleanEvict 12571 # Transaction distribution +system.membus.trans_dist::ReadExReq 100923 # Transaction distribution +system.membus.trans_dist::ReadExResp 100923 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254075 # Request fanout histogram +system.membus.snoop_fanout::samples 253681 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254075 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254075 # Request fanout histogram -system.membus.reqLayer0.occupancy 683661500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253681 # Request fanout histogram +system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765035500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 153b00611..29a3d1e47 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.233306 # Number of seconds simulated -sim_ticks 233306027000 # Number of ticks simulated -final_tick 233306027000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.234001 # Number of seconds simulated +sim_ticks 234001297000 # Number of ticks simulated +final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128535 # Simulator instruction rate (inst/s) -host_op_rate 139249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59354207 # Simulator tick rate (ticks/s) -host_mem_usage 322028 # Number of bytes of host memory used -host_seconds 3930.74 # Real time elapsed on the host +host_inst_rate 134504 # Simulator instruction rate (inst/s) +host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62295833 # Simulator tick rate (ticks/s) +host_mem_usage 343376 # Number of bytes of host memory used +host_seconds 3756.29 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 683648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9174464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16490944 # Number of bytes read from this memory -system.physmem.bytes_read::total 26349056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 683648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 683648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18702784 # Number of bytes written to this memory -system.physmem.bytes_written::total 18702784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257671 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411704 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292231 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292231 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2930263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39323733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70683746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 112937742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2930263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2930263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80164170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80164170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80164170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2930263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39323733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70683746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193101912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411704 # Number of read requests accepted -system.physmem.writeReqs 292231 # Number of write requests accepted -system.physmem.readBursts 411704 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26211648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 137408 # Total number of bytes read from write queue -system.physmem.bytesWritten 18700672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26349056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18702784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26604 # Per bank write bursts -system.physmem.perBankRdBursts::1 25479 # Per bank write bursts -system.physmem.perBankRdBursts::2 25122 # Per bank write bursts -system.physmem.perBankRdBursts::3 24753 # Per bank write bursts -system.physmem.perBankRdBursts::4 27168 # Per bank write bursts -system.physmem.perBankRdBursts::5 26312 # Per bank write bursts -system.physmem.perBankRdBursts::6 25243 # Per bank write bursts -system.physmem.perBankRdBursts::7 24096 # Per bank write bursts -system.physmem.perBankRdBursts::8 25848 # Per bank write bursts -system.physmem.perBankRdBursts::9 24676 # Per bank write bursts -system.physmem.perBankRdBursts::10 25150 # Per bank write bursts -system.physmem.perBankRdBursts::11 26103 # Per bank write bursts -system.physmem.perBankRdBursts::12 26513 # Per bank write bursts -system.physmem.perBankRdBursts::13 25940 # Per bank write bursts -system.physmem.perBankRdBursts::14 25062 # Per bank write bursts -system.physmem.perBankRdBursts::15 25488 # Per bank write bursts -system.physmem.perBankWrBursts::0 18828 # Per bank write bursts -system.physmem.perBankWrBursts::1 18294 # Per bank write bursts -system.physmem.perBankWrBursts::2 17806 # Per bank write bursts -system.physmem.perBankWrBursts::3 17978 # Per bank write bursts -system.physmem.perBankWrBursts::4 18719 # Per bank write bursts -system.physmem.perBankWrBursts::5 18281 # Per bank write bursts -system.physmem.perBankWrBursts::6 17995 # Per bank write bursts -system.physmem.perBankWrBursts::7 17635 # Per bank write bursts -system.physmem.perBankWrBursts::8 18144 # Per bank write bursts -system.physmem.perBankWrBursts::9 17824 # Per bank write bursts -system.physmem.perBankWrBursts::10 18107 # Per bank write bursts -system.physmem.perBankWrBursts::11 18749 # Per bank write bursts -system.physmem.perBankWrBursts::12 18847 # Per bank write bursts -system.physmem.perBankWrBursts::13 18260 # Per bank write bursts -system.physmem.perBankWrBursts::14 18418 # Per bank write bursts -system.physmem.perBankWrBursts::15 18313 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory +system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory +system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423884 # Number of read requests accepted +system.physmem.writeReqs 292667 # Number of write requests accepted +system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue +system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26584 # Per bank write bursts +system.physmem.perBankRdBursts::1 25337 # Per bank write bursts +system.physmem.perBankRdBursts::2 25274 # Per bank write bursts +system.physmem.perBankRdBursts::3 32197 # Per bank write bursts +system.physmem.perBankRdBursts::4 27335 # Per bank write bursts +system.physmem.perBankRdBursts::5 28299 # Per bank write bursts +system.physmem.perBankRdBursts::6 25126 # Per bank write bursts +system.physmem.perBankRdBursts::7 24198 # Per bank write bursts +system.physmem.perBankRdBursts::8 25368 # Per bank write bursts +system.physmem.perBankRdBursts::9 25926 # Per bank write bursts +system.physmem.perBankRdBursts::10 25318 # Per bank write bursts +system.physmem.perBankRdBursts::11 26278 # Per bank write bursts +system.physmem.perBankRdBursts::12 27572 # Per bank write bursts +system.physmem.perBankRdBursts::13 25872 # Per bank write bursts +system.physmem.perBankRdBursts::14 25056 # Per bank write bursts +system.physmem.perBankRdBursts::15 25713 # Per bank write bursts +system.physmem.perBankWrBursts::0 18662 # Per bank write bursts +system.physmem.perBankWrBursts::1 18231 # Per bank write bursts +system.physmem.perBankWrBursts::2 18003 # Per bank write bursts +system.physmem.perBankWrBursts::3 17875 # Per bank write bursts +system.physmem.perBankWrBursts::4 18721 # Per bank write bursts +system.physmem.perBankWrBursts::5 18310 # Per bank write bursts +system.physmem.perBankWrBursts::6 17836 # Per bank write bursts +system.physmem.perBankWrBursts::7 17744 # Per bank write bursts +system.physmem.perBankWrBursts::8 17983 # Per bank write bursts +system.physmem.perBankWrBursts::9 17940 # Per bank write bursts +system.physmem.perBankWrBursts::10 18239 # Per bank write bursts +system.physmem.perBankWrBursts::11 18938 # Per bank write bursts +system.physmem.perBankWrBursts::12 18976 # Per bank write bursts +system.physmem.perBankWrBursts::13 18211 # Per bank write bursts +system.physmem.perBankWrBursts::14 18390 # Per bank write bursts +system.physmem.perBankWrBursts::15 18579 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233306009000 # Total gap between requests +system.physmem.totGap 234001244500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411704 # Read request sizes (log2) +system.physmem.readPktSize::6 423884 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292231 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292667 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 20067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -197,103 +197,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 306850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.361336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.891492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 182.277612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 184544 60.14% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81708 26.63% 86.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16503 5.38% 92.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7231 2.36% 94.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4881 1.59% 96.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2237 0.73% 96.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1756 0.57% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1532 0.50% 97.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6458 2.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 306850 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17319 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.647035 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.821350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17318 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17319 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17319 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.871528 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.829762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.229266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10538 60.85% 60.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 299 1.73% 62.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5524 31.90% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 601 3.47% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 136 0.79% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 86 0.50% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 52 0.30% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 38 0.22% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.14% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.08% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17319 # Writes before turning the bus around for reads -system.physmem.totQLat 9105020732 # Total ticks spent queuing -system.physmem.totMemAccLat 16784214482 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2047785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22231.39 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads +system.physmem.totQLat 8693371575 # Total ticks spent queuing +system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40981.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 112.35 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 112.94 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.50 # Data bus utilization in percentage -system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.84 # Average write queue length when enqueuing -system.physmem.readRowHits 299267 # Number of row buffer hits during reads -system.physmem.writeRowHits 95628 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.72 # Row buffer hit rate for writes -system.physmem.avgGap 331431.18 # Average gap between requests -system.physmem.pageHitRate 56.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1155833280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 630663000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1596964200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942956640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74824379370 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 74344372500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 168733152270 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.246471 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 123152752220 # Time in different power states -system.physmem_0.memoryStateTime::REF 7790380000 # Time in different power states +system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing +system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing +system.physmem.readRowHits 306420 # Number of row buffer hits during reads +system.physmem.writeRowHits 85606 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes +system.physmem.avgGap 326566.07 # Average gap between requests +system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.632069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states +system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 102358687280 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1163673000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 634940625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597073400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950279040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15237983280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74177760825 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74911581750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 168673291920 # Total energy per rank (pJ) -system.physmem_1.averagePower 722.989890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 124105976502 # Time in different power states -system.physmem_1.memoryStateTime::REF 7790380000 # Time in different power states +system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.230337 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states +system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101406021498 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175092094 # Number of BP lookups -system.cpu.branchPred.condPredicted 131341607 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444018 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90535143 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83876326 # Number of BTB hits +system.cpu.branchPred.lookups 175128597 # Number of BP lookups +system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.645047 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12109430 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104164 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,129 +421,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 466612055 # number of cpu cycles simulated +system.cpu.numCycles 468002595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7841296 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731804732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175092094 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95985756 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 450426990 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14940841 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 183 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13996 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236719309 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 465758844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.701594 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.179451 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 93829138 20.15% 20.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132701430 28.49% 48.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57853582 12.42% 61.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181374694 38.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 465758844 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.375241 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.568337 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32366390 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 117283842 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287098365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22028374 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6981873 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24050011 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715808617 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30003155 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6981873 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63420619 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 54156177 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40346363 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276695654 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24158158 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686602803 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340804 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9402338 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2387140 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1669358 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1928954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831026912 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019223277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723937000 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176903161 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544702 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535188 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42285800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143529225 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67986348 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12855797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11202653 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668172379 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610256171 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5859842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123799764 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319235639 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 465758844 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.310241 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101448 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 148618613 31.91% 31.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101179975 21.72% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145721974 31.29% 84.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63321350 13.60% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6916462 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 465758844 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71923603 52.95% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44560845 32.81% 85.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19351011 14.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413149972 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351777 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -562,84 +571,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134213690 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62540729 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610256171 # Type of FU issued -system.cpu.iq.rate 1.307845 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135835489 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222588 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1827966224 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 794978756 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594986581 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued +system.cpu.iq.rate 1.303953 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746091483 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7271635 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644469 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25562 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29008 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11125871 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225728 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22400 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6981873 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22924718 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 919849 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672638124 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143529225 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67986348 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258699 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 524927 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29008 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821848 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731355 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7553203 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599403304 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129574600 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10852867 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487415 # number of nop insts executed -system.cpu.iew.exec_refs 190539133 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373270 # Number of branches executed -system.cpu.iew.exec_stores 60964533 # Number of stores executed -system.cpu.iew.exec_rate 1.284586 # Inst execution rate -system.cpu.iew.wb_sent 596281070 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594986597 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349903865 # num instructions producing a value -system.cpu.iew.wb_consumers 570650112 # num instructions consuming a value +system.cpu.iew.exec_nop 1487469 # number of nop insts executed +system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373386 # Number of branches executed +system.cpu.iew.exec_stores 60956801 # Number of stores executed +system.cpu.iew.exec_rate 1.280758 # Inst execution rate +system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349895185 # num instructions producing a value +system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.275121 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613167 # average fanout of values written-back +system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110031903 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6955471 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 448643201 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.223009 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.887847 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 219610457 48.95% 48.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116308832 25.92% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43746420 9.75% 84.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23291517 5.19% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11578245 2.58% 92.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7791027 1.74% 94.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8269909 1.84% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4243315 0.95% 96.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13803479 3.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 448643201 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -685,385 +694,391 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13803479 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1093559316 # The number of ROB reads -system.cpu.rob.rob_writes 1334598854 # The number of ROB writes -system.cpu.timesIdled 13995 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 853211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095134181 # The number of ROB reads +system.cpu.rob.rob_writes 1334612111 # The number of ROB writes +system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.923550 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.923550 # CPI: Total CPI of All Threads -system.cpu.ipc 1.082779 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.082779 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611100755 # number of integer regfile reads -system.cpu.int_regfile_writes 328116502 # number of integer regfile writes +system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611088799 # number of integer regfile reads +system.cpu.int_regfile_writes 328120173 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170188783 # number of cc regfile reads -system.cpu.cc_regfile_writes 376538117 # number of cc regfile writes -system.cpu.misc_regfile_reads 217976814 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads +system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes +system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820876 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.631746 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169355780 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821388 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.025697 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 498153000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.631746 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999281 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999281 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2820726 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356248226 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356248226 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114651895 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114651895 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51723951 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51723951 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488560 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488560 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166375846 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166375846 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166378633 # number of overall hits -system.cpu.dcache.overall_hits::total 166378633 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4842252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4842252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2515355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2515355 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits +system.cpu.dcache.overall_hits::total 166375784 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7357607 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7357607 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7357619 # number of overall misses -system.cpu.dcache.overall_misses::total 7357619 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 56173880000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 56173880000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19052445440 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19052445440 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1310000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1310000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75226325440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75226325440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75226325440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75226325440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119494147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119494147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses +system.cpu.dcache.overall_misses::total 7359142 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2799 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2799 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488626 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488626 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173733453 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173733453 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173736252 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173736252 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040523 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040523 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046375 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004287 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.004287 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042350 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042350 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042349 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042349 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11600.775837 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11600.775837 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7574.455868 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7574.455868 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19848.484848 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19848.484848 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10224.292415 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10224.292415 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10224.275739 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10224.275739 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 932011 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221163 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.214136 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2352880 # number of writebacks -system.cpu.dcache.writebacks::total 2352880 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2540436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995769 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1995769 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4536205 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4536205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4536205 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4536205 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301816 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301816 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519586 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519586 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks +system.cpu.dcache.writebacks::total 2820726 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2821402 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2821402 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2821412 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2821412 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 28692574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 28692574000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4617588494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4617588494 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 686000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 686000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33310162494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 33310162494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33310848494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 33310848494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019263 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003573 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003573 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016240 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016240 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016240 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12465.190093 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12465.190093 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8887.053335 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8887.053335 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68600 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68600 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11806.244730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11806.244730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11806.446026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11806.446026 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73459 # number of replacements -system.cpu.icache.tags.tagsinuse 466.213956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236636536 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73971 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3199.044707 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114942017500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.213956 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910574 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910574 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73505 # number of replacements +system.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473512362 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473512362 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236636536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236636536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236636536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236636536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236636536 # number of overall hits -system.cpu.icache.overall_hits::total 236636536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 82647 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 82647 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 82647 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 82647 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 82647 # number of overall misses -system.cpu.icache.overall_misses::total 82647 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1564864673 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1564864673 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1564864673 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1564864673 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1564864673 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1564864673 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236719183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236719183 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236719183 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236719183 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236719183 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236719183 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000349 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000349 # 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number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 335947000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 335947000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 538896500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 538896500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10864639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10864639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538896500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11200586500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11739483000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538896500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11200586500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.041667 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.144425 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.060750 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.060750 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053201 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144425 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050809 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148304 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69356.062148 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92304.151871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92304.151871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67648.272957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67648.272957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71343.207508 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71343.207508 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71585.133249 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67648.272957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71878.519309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69356.062148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70155.690850 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789744 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894372 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23770 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 30234 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 30144 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373438 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2645111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 626124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 317103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521946 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 73997 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299442 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220575 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661383 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331153152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 335887104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 717772 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6507488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.011967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108866 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 950663 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6429701 98.80% 98.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 77697 1.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 90 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6507488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5247752000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111080826 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4232108471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 408044 # Transaction distribution -system.membus.trans_dist::Writeback 292231 # Transaction distribution -system.membus.trans_dist::CleanEvict 102781 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 3660 # Transaction distribution -system.membus.trans_dist::ReadExResp 3660 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 408044 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1218424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1218424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45051840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45051840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 420198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution +system.membus.trans_dist::CleanEvict 98618 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33 # Transaction distribution +system.membus.trans_dist::UpgradeResp 33 # Transaction distribution +system.membus.trans_dist::ReadExReq 3685 # Transaction distribution +system.membus.trans_dist::ReadExResp 3685 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 806718 # Request fanout histogram +system.membus.snoop_fanout::samples 815202 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 806718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 806718 # Request fanout histogram -system.membus.reqLayer0.occupancy 2171550377 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 815202 # Request fanout histogram +system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2176359308 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index ad7524f92..d23424e24 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707537 # Number of seconds simulated -sim_ticks 707536959500 # Number of ticks simulated -final_tick 707536959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708526 # Number of seconds simulated +sim_ticks 708526400500 # Number of ticks simulated +final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064510 # Simulator instruction rate (inst/s) -host_op_rate 1152817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1491485099 # Simulator tick rate (ticks/s) -host_mem_usage 319084 # Number of bytes of host memory used -host_seconds 474.38 # Real time elapsed on the host +host_inst_rate 974268 # Simulator instruction rate (inst/s) +host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1366955379 # Simulator tick rate (ticks/s) +host_mem_usage 319428 # Number of bytes of host memory used +host_seconds 518.32 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8946752 # Number of bytes read from this memory -system.physmem.bytes_read::total 9122112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6146048 # Number of bytes written to this memory -system.physmem.bytes_written::total 6146048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139793 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96032 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96032 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 247846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12644925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12892771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 247846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8686540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8686540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8686540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 247846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12644925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21579311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8963904 # Number of bytes read from this memory +system.physmem.bytes_read::total 9111296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6165120 # Number of bytes written to this memory +system.physmem.bytes_written::total 6165120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140061 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415073919 # number of cpu cycles simulated +system.cpu.numCycles 1417052801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986854 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415073918.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548302 # Number of branches fetched @@ -215,14 +215,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695379 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318106 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716435500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318106 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11820971000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11820971000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8866220000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20687191000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20687191000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20687191000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20687191000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15103.641825 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15103.641825 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24886.936507 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24886.936507 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18163.914491 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18163.914491 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18163.898542 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18163.898542 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064880 # number of writebacks -system.cpu.dcache.writebacks::total 1064880 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks +system.cpu.dcache.writebacks::total 1064678 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11038314000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11038314000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509960000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509960000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19548274000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19548274000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19548328000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19548328000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14103.641825 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14103.641825 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23886.936507 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23886.936507 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17163.914491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17163.914491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17163.946834 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17163.946834 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.371232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.371232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 265444000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 265444000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 265444000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 265444000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 265444000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 265444000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23040.013888 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23040.013888 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23040.013888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23040.013888 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23040.013888 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,92 +409,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 9788 # number of writebacks +system.cpu.icache.writebacks::total 9788 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11521 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 11521 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 11521 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 253923000 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22040.013888 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22040.013888 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22040.013888 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22040.013888 # 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number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.077163 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1743796 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 140956 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.371208 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494154000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23345.006122 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.705462 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3616.365578 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.712433 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110363 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 110394 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # 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Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18829920 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 1064880 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1064880 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255527 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255527 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8781 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743598 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 743598 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8781 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 999125 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1007906 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8781 # 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number of overall misses -system.cpu.l2cache.overall_misses::total 142533 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5292536500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5292536500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 144147000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2053419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2053419500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144147000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7345956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7490103000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144147000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7345956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7490103000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 1064880 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1064880 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9751 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # 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number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282751 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282751 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.237827 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.237827 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.049907 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.049907 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.237827 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122742 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123894 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.237827 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122742 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123894 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.245004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.245004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52608.394161 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52570.903738 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52570.903738 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52549.956852 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52608.394161 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52548.811457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52549.956852 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,70 +545,71 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96032 # number of writebacks -system.cpu.l2cache.writebacks::total 96032 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 792 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 792 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100733 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39060 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39060 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 139793 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 142533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 139793 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 142533 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285206500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285206500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 116747000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1662819500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1662819500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116747000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5948026000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6064773000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116747000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5948026000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6064773000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 96330 # number of writebacks +system.cpu.l2cache.writebacks::total 96330 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100788 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2303 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 39273 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140061 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 142364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282751 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237827 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.049907 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.049907 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123894 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122742 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123894 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42540.245004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42540.245004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42608.394161 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42570.903738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42570.903738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42608.394161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42548.811457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42549.956852 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2140 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2139 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1160912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 90016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution @@ -610,51 +617,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141043072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 141780416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 109779 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2404828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003790 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.061455 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 110394 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2395714 99.62% 99.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9113 0.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2404828 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2212404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 41800 # Transaction distribution -system.membus.trans_dist::Writeback 96032 # Transaction distribution -system.membus.trans_dist::CleanEvict 12399 # Transaction distribution -system.membus.trans_dist::ReadExReq 100733 # Transaction distribution -system.membus.trans_dist::ReadExResp 100733 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 41800 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393497 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 393497 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15268160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15268160 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 41576 # Transaction distribution +system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution +system.membus.trans_dist::CleanEvict 11920 # Transaction distribution +system.membus.trans_dist::ReadExReq 100788 # Transaction distribution +system.membus.trans_dist::ReadExResp 100788 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 41576 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 392978 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15276416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15276416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 251058 # Request fanout histogram +system.membus.snoop_fanout::samples 250615 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 251058 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 250615 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 251058 # Request fanout histogram -system.membus.reqLayer0.occupancy 643796492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 250615 # Request fanout histogram +system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 719009164 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 987362254..e3c4d5903 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403931 # Number of seconds simulated -sim_ticks 403931323500 # Number of ticks simulated -final_tick 403931323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403830 # Number of seconds simulated +sim_ticks 403830091000 # Number of ticks simulated +final_tick 403830091000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95186 # Simulator instruction rate (inst/s) -host_op_rate 176009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46498470 # Simulator tick rate (ticks/s) -host_mem_usage 433064 # Number of bytes of host memory used -host_seconds 8686.98 # Real time elapsed on the host +host_inst_rate 95719 # Simulator instruction rate (inst/s) +host_op_rate 176996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46747318 # Simulator tick rate (ticks/s) +host_mem_usage 431916 # Number of bytes of host memory used +host_seconds 8638.57 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24500544 # Number of bytes read from this memory -system.physmem.bytes_read::total 24718528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18869632 # Number of bytes written to this memory -system.physmem.bytes_written::total 18869632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382821 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386227 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294838 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 539656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60655222 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61194878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539656 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46714951 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46714951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60655222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107909829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386228 # Number of read requests accepted -system.physmem.writeReqs 294838 # Number of write requests accepted -system.physmem.readBursts 386228 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294838 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24699456 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19136 # Total number of bytes read from write queue -system.physmem.bytesWritten 18868032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24718592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18869632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24545280 # Number of bytes read from this memory +system.physmem.bytes_read::total 24709056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory +system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383520 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386079 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 405557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60781206 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61186763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 405557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46778168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46778168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 405557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60781206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107964931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386079 # Number of read requests accepted +system.physmem.writeReqs 295163 # Number of write requests accepted +system.physmem.readBursts 386079 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24689408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18889088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24709056 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 196128 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24062 # Per bank write bursts -system.physmem.perBankRdBursts::1 26430 # Per bank write bursts -system.physmem.perBankRdBursts::2 24903 # Per bank write bursts -system.physmem.perBankRdBursts::3 24577 # Per bank write bursts -system.physmem.perBankRdBursts::4 23181 # Per bank write bursts -system.physmem.perBankRdBursts::5 23704 # Per bank write bursts -system.physmem.perBankRdBursts::6 24550 # Per bank write bursts -system.physmem.perBankRdBursts::7 24303 # Per bank write bursts -system.physmem.perBankRdBursts::8 23663 # Per bank write bursts -system.physmem.perBankRdBursts::9 23568 # Per bank write bursts -system.physmem.perBankRdBursts::10 24789 # Per bank write bursts -system.physmem.perBankRdBursts::11 23975 # Per bank write bursts -system.physmem.perBankRdBursts::12 23330 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24089 # Per bank write bursts -system.physmem.perBankRdBursts::15 23873 # Per bank write bursts -system.physmem.perBankWrBursts::0 18604 # Per bank write bursts -system.physmem.perBankWrBursts::1 19922 # Per bank write bursts -system.physmem.perBankWrBursts::2 19191 # Per bank write bursts -system.physmem.perBankWrBursts::3 18985 # Per bank write bursts -system.physmem.perBankWrBursts::4 18090 # Per bank write bursts -system.physmem.perBankWrBursts::5 18485 # Per bank write bursts -system.physmem.perBankWrBursts::6 19138 # Per bank write bursts -system.physmem.perBankWrBursts::7 19082 # Per bank write bursts -system.physmem.perBankWrBursts::8 18642 # Per bank write bursts -system.physmem.perBankWrBursts::9 17946 # Per bank write bursts -system.physmem.perBankWrBursts::10 18887 # Per bank write bursts -system.physmem.perBankWrBursts::11 17737 # Per bank write bursts -system.physmem.perBankWrBursts::12 17398 # Per bank write bursts -system.physmem.perBankWrBursts::13 16988 # Per bank write bursts -system.physmem.perBankWrBursts::14 17875 # Per bank write bursts -system.physmem.perBankWrBursts::15 17843 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 251728 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24087 # Per bank write bursts +system.physmem.perBankRdBursts::1 26440 # Per bank write bursts +system.physmem.perBankRdBursts::2 24835 # Per bank write bursts +system.physmem.perBankRdBursts::3 24498 # Per bank write bursts +system.physmem.perBankRdBursts::4 23219 # Per bank write bursts +system.physmem.perBankRdBursts::5 23721 # Per bank write bursts +system.physmem.perBankRdBursts::6 24501 # Per bank write bursts +system.physmem.perBankRdBursts::7 24288 # Per bank write bursts +system.physmem.perBankRdBursts::8 23633 # Per bank write bursts +system.physmem.perBankRdBursts::9 23532 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 23996 # Per bank write bursts +system.physmem.perBankRdBursts::12 23302 # Per bank write bursts +system.physmem.perBankRdBursts::13 22925 # Per bank write bursts +system.physmem.perBankRdBursts::14 24085 # Per bank write bursts +system.physmem.perBankRdBursts::15 23896 # Per bank write bursts +system.physmem.perBankWrBursts::0 18615 # Per bank write bursts +system.physmem.perBankWrBursts::1 19935 # Per bank write bursts +system.physmem.perBankWrBursts::2 19196 # Per bank write bursts +system.physmem.perBankWrBursts::3 19026 # Per bank write bursts +system.physmem.perBankWrBursts::4 18118 # Per bank write bursts +system.physmem.perBankWrBursts::5 18514 # Per bank write bursts +system.physmem.perBankWrBursts::6 19142 # Per bank write bursts +system.physmem.perBankWrBursts::7 19086 # Per bank write bursts +system.physmem.perBankWrBursts::8 18651 # Per bank write bursts +system.physmem.perBankWrBursts::9 17953 # Per bank write bursts +system.physmem.perBankWrBursts::10 18925 # Per bank write bursts +system.physmem.perBankWrBursts::11 17775 # Per bank write bursts +system.physmem.perBankWrBursts::12 17401 # Per bank write bursts +system.physmem.perBankWrBursts::13 17016 # Per bank write bursts +system.physmem.perBankWrBursts::14 17907 # Per bank write bursts +system.physmem.perBankWrBursts::15 17882 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403931308500 # Total gap between requests +system.physmem.totGap 403830049500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386228 # Read request sizes (log2) +system.physmem.readPktSize::6 386079 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294838 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295163 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,248 +193,248 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.637860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.325639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.046473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54140 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39981 27.22% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13765 9.37% 73.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7667 5.22% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5371 3.66% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3914 2.67% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3025 2.06% 87.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2731 1.86% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16272 11.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17494 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.060078 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.173610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17485 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.793805 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.429172 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.898216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54192 36.91% 36.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39812 27.11% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13750 9.36% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7660 5.22% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5440 3.71% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4000 2.72% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3009 2.05% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2793 1.90% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16171 11.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146827 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17508 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.033813 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.830406 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17494 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.852235 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.776145 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.682764 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17296 98.87% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 0.82% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 28 0.16% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17508 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.857551 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.779124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.831180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17335 99.01% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 121 0.69% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17494 # Writes before turning the bus around for reads -system.physmem.totQLat 4291077750 # Total ticks spent queuing -system.physmem.totMemAccLat 11527246500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1929645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11118.83 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17508 # Writes before turning the bus around for reads +system.physmem.totQLat 4276128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11509353000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928860000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11084.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29868.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.71 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29834.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.35 # Average write queue length when enqueuing -system.physmem.readRowHits 317989 # Number of row buffer hits during reads -system.physmem.writeRowHits 215873 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.22 # Row buffer hit rate for writes -system.physmem.avgGap 593086.88 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 567438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 309614250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526405400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 981499680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62258546970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187743770250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279769842150 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.623817 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311776883750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem.avgWrQLen 21.79 # Average write queue length when enqueuing +system.physmem.readRowHits 318168 # Number of row buffer hits during reads +system.physmem.writeRowHits 215906 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes +system.physmem.avgGap 592785.02 # Average gap between requests +system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 567876960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 309853500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525477200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982432800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62051510430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187864648500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279677755230 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.569390 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311979208000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78662661250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78362495750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 542467800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295989375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483341600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928473840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26382567120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60448758210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189331310250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279412908195 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.740141 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314432491250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13488020000 # Time in different power states +system.physmem_1.actEnergy 541779840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295614000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1483021800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929672640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26375955840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60320910060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189382719000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279329673180 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.707431 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314516116250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13484640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76007072500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75825587500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219314839 # Number of BP lookups -system.cpu.branchPred.condPredicted 219314839 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123981217 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121825604 # Number of BTB hits +system.cpu.branchPred.lookups 219264229 # Number of BP lookups +system.cpu.branchPred.condPredicted 219264229 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8531047 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124002696 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121802201 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.261339 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27068206 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1407908 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.225446 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27063113 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406921 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807862648 # number of cpu cycles simulated +system.cpu.numCycles 807660183 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175941692 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208657835 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219314839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148893810 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 622000001 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17769177 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 227 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92380 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 735169 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1433 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170789403 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2323822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.784658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175911242 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208663462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219264229 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148865314 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621862787 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17775835 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 233 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 94904 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 745978 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1264 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170762091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2319100 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.785127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417598750 51.71% 51.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32531773 4.03% 55.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31857083 3.94% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32716073 4.05% 63.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26594170 3.29% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26933309 3.33% 70.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35181908 4.36% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31423846 3.89% 78.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172818607 21.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417532473 51.71% 51.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32497368 4.02% 55.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31891068 3.95% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32657877 4.04% 63.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26554759 3.29% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26902865 3.33% 70.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35168137 4.36% 74.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31391832 3.89% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172907963 21.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807655519 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271475 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496118 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120412218 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 371076736 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225209960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82072017 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8884588 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132095724 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8884588 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152556291 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150817488 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 41958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271423783 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223931411 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088526658 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 137354 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138380994 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24891978 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50561951 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190720490 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5278322969 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3357144423 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 60320 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807504342 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271481 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496500 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120449956 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370877919 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225251519 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82037031 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8887917 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132109647 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8887917 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152555499 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150771591 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 44475 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271462113 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223782747 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088438662 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 138448 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138151621 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24868058 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50731794 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190645258 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278038161 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357041251 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59967 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576679636 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3187 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2956 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 423114583 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507122992 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200812983 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229080264 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68423458 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023133283 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22942 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1788928106 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 421261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494167524 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 833180412 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22390 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807655519 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.214964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070282 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576604404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3331 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3057 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422478077 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507119798 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200816388 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229077730 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68200212 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023068034 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1788999576 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 413303 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494102244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832764755 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22359 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807504342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.215467 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.071001 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238829466 29.57% 29.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123732265 15.32% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119115162 14.75% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107661207 13.33% 72.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89581047 11.09% 84.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60232277 7.46% 91.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42307619 5.24% 96.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18921199 2.34% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7275277 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238908265 29.59% 29.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123628552 15.31% 44.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118817632 14.71% 59.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107769877 13.35% 72.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89573603 11.09% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60241832 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42310466 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18973159 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7280956 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807655519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807504342 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11512552 42.68% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12355843 45.81% 88.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3105832 11.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11498712 42.77% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12295029 45.73% 88.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3093590 11.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2718297 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183078959 66.13% 66.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 370517 0.02% 66.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881151 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718967 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183065523 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369413 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881231 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 133 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 67 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 365 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 60 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -456,84 +456,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428492741 23.95% 90.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170385875 9.52% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428545273 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170418596 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1788928106 # Type of FU issued -system.cpu.iq.rate 2.214396 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26974227 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015078 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412876800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517572556 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762303286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 30419 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 69720 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5693 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813170766 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 13270 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186079397 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1788999576 # Type of FU issued +system.cpu.iq.rate 2.215040 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26887331 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015029 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412774566 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517442986 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762358918 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29562 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69250 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5611 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813154984 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12956 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186087729 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123023075 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 212257 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 371984 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51652797 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123020037 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213128 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 372787 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51656202 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 22860 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1101 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 22930 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1078 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8884588 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97906785 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6199562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023156225 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370486 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507125232 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200812983 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7241 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1822287 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3474512 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 371984 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845065 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4137242 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8982307 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1769932780 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423113153 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 18995326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8887917 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97798502 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6162253 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023090945 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375323 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507122194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200816388 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7129 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1832886 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3426694 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 372787 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845812 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4140641 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8986453 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1769991187 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423150453 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19008389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590301691 # number of memory reference insts executed -system.cpu.iew.exec_branches 168980249 # Number of branches executed -system.cpu.iew.exec_stores 167188538 # Number of stores executed -system.cpu.iew.exec_rate 2.190883 # Inst execution rate -system.cpu.iew.wb_sent 1766804374 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762308979 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339663552 # num instructions producing a value -system.cpu.iew.wb_consumers 2049989844 # num instructions consuming a value +system.cpu.iew.exec_refs 590375275 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976940 # Number of branches executed +system.cpu.iew.exec_stores 167224822 # Number of stores executed +system.cpu.iew.exec_rate 2.191505 # Inst execution rate +system.cpu.iew.wb_sent 1766866321 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762364529 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339720871 # num instructions producing a value +system.cpu.iew.wb_consumers 2049946578 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.181446 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653498 # average fanout of values written-back +system.cpu.iew.wb_rate 2.182062 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653539 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 494228972 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494164798 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8612841 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740434686 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.064988 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.575030 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8615583 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 740300612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.065362 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575682 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276267324 37.31% 37.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172135150 23.25% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 56000087 7.56% 68.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86333753 11.66% 79.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25859703 3.49% 83.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26527369 3.58% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9854605 1.33% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9004729 1.22% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78451966 10.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276280439 37.32% 37.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172026383 23.24% 60.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 56011691 7.57% 68.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86227626 11.65% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25892196 3.50% 83.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26512378 3.58% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9839162 1.33% 88.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8995484 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78515253 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740434686 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 740300612 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,344 +579,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78451966 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2685200393 # The number of ROB reads -system.cpu.rob.rob_writes 4113829657 # The number of ROB writes -system.cpu.timesIdled 2326 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207129 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78515253 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684938858 # The number of ROB reads +system.cpu.rob.rob_writes 4113685431 # The number of ROB writes +system.cpu.timesIdled 1962 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 155841 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.977004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.977004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023537 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023537 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722489562 # number of integer regfile reads -system.cpu.int_regfile_writes 1435790744 # number of integer regfile writes -system.cpu.fp_regfile_reads 5969 # number of floating regfile reads -system.cpu.fp_regfile_writes 521 # number of floating regfile writes -system.cpu.cc_regfile_reads 596647275 # number of cc regfile reads -system.cpu.cc_regfile_writes 405463698 # number of cc regfile writes -system.cpu.misc_regfile_reads 971582048 # number of misc regfile reads +system.cpu.cpi 0.976760 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976760 # CPI: Total CPI of All Threads +system.cpu.ipc 1.023793 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.023793 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722687854 # number of integer regfile reads +system.cpu.int_regfile_writes 1435809850 # number of integer regfile writes +system.cpu.fp_regfile_reads 5827 # number of floating regfile reads +system.cpu.fp_regfile_writes 561 # number of floating regfile writes +system.cpu.cc_regfile_reads 596681162 # number of cc regfile reads +system.cpu.cc_regfile_writes 405470892 # number of cc regfile writes +system.cpu.misc_regfile_reads 971641846 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2530897 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.817920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381840179 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534993 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.627705 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530997 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.815869 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381868965 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535093 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.633119 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.817920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.815869 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 865 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772772413 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772772413 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233184165 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233184165 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148172813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148172813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381356978 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381356978 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381356978 # number of overall hits -system.cpu.dcache.overall_hits::total 381356978 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2774343 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2774343 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 987389 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 987389 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3761732 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3761732 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3761732 # number of overall misses -system.cpu.dcache.overall_misses::total 3761732 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59119368500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31296279995 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90415648495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90415648495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90415648495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235958508 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235958508 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772828805 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772828805 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233213748 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233213748 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173817 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173817 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381387565 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381387565 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381387565 # number of overall hits +system.cpu.dcache.overall_hits::total 381387565 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2772906 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2772906 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986385 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3759291 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3759291 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3759291 # number of overall misses +system.cpu.dcache.overall_misses::total 3759291 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59174415500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31292251995 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90466667495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90466667495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90466667495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235986654 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235986654 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385118710 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385118710 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385118710 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385118710 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011758 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006620 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21309.322063 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21309.322063 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31695.998229 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31695.998229 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24035.643287 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24035.643287 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10106 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1086 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.305709 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385146856 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385146856 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385146856 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385146856 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009761 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009761 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21340.216906 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21340.216906 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31724.176660 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31724.176660 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24064.821663 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24064.821663 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9788 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.348615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330787 # number of writebacks -system.cpu.dcache.writebacks::total 2330787 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1009448 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19379 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19379 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1028827 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1028827 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1028827 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764895 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 968010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 968010 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2732905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2732905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2732905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33550858500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30073647496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63624505996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63624505996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006490 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007096 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19010.115899 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31067.496716 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23280.906580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23280.906580 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330532 # number of writebacks +system.cpu.dcache.writebacks::total 2330532 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1007920 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1027323 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1027323 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1027323 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 966982 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 966982 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2731968 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2731968 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2731968 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33558631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 30070164497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63628795497 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63628795497 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007479 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.007093 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.007093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19013.539484 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31096.922690 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23290.461490 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23290.461490 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6655 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.678215 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 170577740 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8265 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20638.565033 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6653 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.717066 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170551460 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8264 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20637.882381 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.678215 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506679 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 326 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786133 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341785100 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341785100 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170580521 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170580521 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170580521 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170580521 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170580521 # number of overall hits -system.cpu.icache.overall_hits::total 170580521 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 208882 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 208882 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 208882 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 208882 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 208882 # number of overall misses -system.cpu.icache.overall_misses::total 208882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312211500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1312211500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1312211500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1312211500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1312211500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170789403 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170789403 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170789403 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170789403 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170789403 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001223 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001223 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001223 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001223 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001223 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6282.070739 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6282.070739 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6282.070739 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6282.070739 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 889 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.717066 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506698 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 321 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1160 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341729418 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341729418 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170554639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170554639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170554639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170554639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170554639 # number of overall hits +system.cpu.icache.overall_hits::total 170554639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 207451 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 207451 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 207451 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 207451 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 207451 # number of overall misses +system.cpu.icache.overall_misses::total 207451 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1211820000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1211820000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1211820000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1211820000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1211820000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170762090 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170762090 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170762090 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170762090 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170762090 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001215 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001215 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001215 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001215 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001215 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5841.475818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 5841.475818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 5841.475818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 5841.475818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 674 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 74.083333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2585 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2585 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2585 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2585 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2585 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 206297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 206297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 206297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 206297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 206297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 989635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 989635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 989635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 989635000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001208 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001208 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001208 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4797.137137 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4797.137137 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4797.137137 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 6653 # number of writebacks +system.cpu.icache.writebacks::total 6653 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2211 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2211 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2211 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2211 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2211 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205240 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205240 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205240 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205240 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205240 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 926829000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 926829000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 926829000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 926829000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4515.830248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4515.830248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4515.830248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 353544 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29619.458392 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3891749 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385874 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.085543 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 189343942500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20941.541383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 242.518808 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8435.398201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007401 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.257428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32330 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13379 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18648 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986633 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43295860 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43295860 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2330787 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330787 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1834 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1834 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 563915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 563915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1588207 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1588207 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2152122 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2156965 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2152122 # number of overall hits -system.cpu.l2cache.overall_hits::total 2156965 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 196078 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 196078 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206573 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206573 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3410 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3410 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176298 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 176298 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3410 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382871 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386281 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3410 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382871 # number of overall misses -system.cpu.l2cache.overall_misses::total 386281 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 13890000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 13890000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16378927500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16378927500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 280136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 280136500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14178823000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 14178823000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26951247500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990733 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268107 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.412941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099914 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151884 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.412941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151884 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22050.960694 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69288.810735 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72156.543427 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70425.319629 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72156.543427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69812.131240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.815141 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990659 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268566 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310755 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310755 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22053.123649 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69319.986565 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72005.273438 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70327.210711 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72005.273438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69783.830289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69798.558254 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5476754 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2732107 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 213805 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3607 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5474858 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731062 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212394 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3599 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3599 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1970799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2625625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 253914 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 197912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 206297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764505 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7985563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8206352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 528000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311409920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311937920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 551588 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5830298 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072755 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259734 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1969834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 249937 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196875 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 205240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764596 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219739 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7984230 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8203969 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 927936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311400000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312327936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552340 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3292546 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.124310 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329935 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5406114 92.72% 92.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 424184 7.28% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883249 87.57% 87.57% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 409297 12.43% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5830298 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5097760193 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3292546 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5102581952 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 309447487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 307865483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3901446077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3901080066 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179703 # Transaction distribution -system.membus.trans_dist::Writeback 294838 # Transaction distribution -system.membus.trans_dist::CleanEvict 57117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 196128 # Transaction distribution -system.membus.trans_dist::UpgradeResp 196128 # Transaction distribution -system.membus.trans_dist::ReadExReq 206523 # Transaction distribution -system.membus.trans_dist::ReadExResp 206523 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179705 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1516665 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43588096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43588096 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution +system.membus.trans_dist::CleanEvict 56643 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195085 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195085 # Transaction distribution +system.membus.trans_dist::ReadExReq 206880 # Transaction distribution +system.membus.trans_dist::ReadExResp 206880 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179199 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1514133 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43599424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43599424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 934311 # Request fanout histogram +system.membus.snoop_fanout::samples 932970 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 934311 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 932970 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 934311 # Request fanout histogram -system.membus.reqLayer0.occupancy 2245481708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 932970 # Request fanout histogram +system.membus.reqLayer0.occupancy 2244779968 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2435298904 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2432276830 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 22535a108..1b9df2638 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.647861 # Number of seconds simulated -sim_ticks 1647861059500 # Number of ticks simulated -final_tick 1647861059500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650527 # Number of seconds simulated +sim_ticks 1650526667500 # Number of ticks simulated +final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 657040 # Simulator instruction rate (inst/s) -host_op_rate 1214941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1309397988 # Simulator tick rate (ticks/s) -host_mem_usage 327616 # Number of bytes of host memory used -host_seconds 1258.49 # Real time elapsed on the host +host_inst_rate 726731 # Simulator instruction rate (inst/s) +host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450624585 # Simulator tick rate (ticks/s) +host_mem_usage 327760 # Number of bytes of host memory used +host_seconds 1137.80 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 120384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24254848 # Number of bytes read from this memory -system.physmem.bytes_read::total 24375232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 120384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 120384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18763136 # Number of bytes written to this memory -system.physmem.bytes_written::total 18763136 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 378982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380863 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 73055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14718989 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14792043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 73055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 73055 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11386358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11386358 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11386358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 73055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14718989 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26178401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295722119 # number of cpu cycles simulated +system.cpu.numCycles 3301053335 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295722118.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -100,14 +100,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415711 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211725500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415711 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 2518458 # n system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29707934500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29707934500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18949311500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18949311500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48657246000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48657246000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48657246000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48657246000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17197.923891 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17197.923891 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23954.813512 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23954.813512 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19320.253107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19320.253107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19320.253107 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323227 # number of writebacks -system.cpu.dcache.writebacks::total 2323227 # number of writebacks +system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks +system.cpu.dcache.writebacks::total 2323200 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27980520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27980520500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18158267500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18158267500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46138788000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46138788000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46138788000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46138788000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16197.923891 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16197.923891 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22954.813512 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22954.813512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18320.253107 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18320.253107 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.348726 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.348726 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430346 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115655000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115655000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115655000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115655000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115655000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115655000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41099.857854 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41099.857854 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41099.857854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41099.857854 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41099.857854 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -270,92 +270,98 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1253 # number of writebacks +system.cpu.icache.writebacks::total 1253 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2814 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 2814 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 2814 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112841000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 112841000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112841000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 112841000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112841000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 112841000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40099.857854 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40099.857854 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40099.857854 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 40099.857854 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348182 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29285.938694 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3846845 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380537 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.108991 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755943397500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20928.501607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.116925 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8218.320163 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.638687 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004246 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893736 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 348438 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.473875 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3847001 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.102472 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.252047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.876987 # 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Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41466677 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2323227 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2323227 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584717 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584717 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 933 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 933 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554759 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1554759 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 933 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2139476 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2140409 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 933 # 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number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 378982 # number of overall misses -system.cpu.l2cache.overall_misses::total 380863 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10832173000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10832173000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 98817000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 98817000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9064428500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9064428500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19896601500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19995418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19896601500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19995418500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 2323227 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2323227 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41466938 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41466938 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2323200 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2323200 # 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n system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260829 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.668443 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.668443 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.668443 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150482 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214627500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89562500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762823000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852385500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89562500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762823000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852385500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260829 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.668443 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151060 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.668443 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150482 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151060 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.026657 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.026657 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42534.290271 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42534.290271 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.237468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.237468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42534.290271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.122697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.291443 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -462,8 +468,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2616401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 247396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution @@ -471,53 +478,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 180096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309867840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310047936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348182 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5385069 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000321 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.017916 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5383340 99.97% 99.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1729 0.03% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5385069 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4841670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174536 # Transaction distribution -system.membus.trans_dist::Writeback 293174 # Transaction distribution -system.membus.trans_dist::CleanEvict 53553 # Transaction distribution -system.membus.trans_dist::ReadExReq 206327 # Transaction distribution -system.membus.trans_dist::ReadExResp 206327 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174536 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108453 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43138368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43138368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43138368 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 174499 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution +system.membus.trans_dist::CleanEvict 53507 # Transaction distribution +system.membus.trans_dist::ReadExReq 206356 # Transaction distribution +system.membus.trans_dist::ReadExResp 206356 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727623 # Request fanout histogram +system.membus.snoop_fanout::samples 727569 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727623 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727623 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900350576 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727569 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904342076 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index e60710ec5..55abb5639 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.225711 # Nu sim_ticks 225710988500 # Number of ticks simulated final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311102 # Simulator instruction rate (inst/s) -host_op_rate 311102 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 176136084 # Simulator tick rate (ticks/s) -host_mem_usage 304484 # Number of bytes of host memory used -host_seconds 1281.46 # Real time elapsed on the host +host_inst_rate 329346 # Simulator instruction rate (inst/s) +host_op_rate 329346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 186465123 # Simulator tick rate (ticks/s) +host_mem_usage 304340 # Number of bytes of host memory used +host_seconds 1210.47 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -482,6 +482,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3187 # number of writebacks +system.cpu.icache.writebacks::total 3187 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5165 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 5165 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 5165 # number of demand (read+write) MSHR misses @@ -528,8 +530,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4439 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160828 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 114772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 114772 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3187 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3187 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1273 # number of ReadCleanReq hits @@ -566,8 +570,10 @@ system.cpu.l2cache.demand_miss_latency::total 593982000 system.cpu.l2cache.overall_miss_latency::cpu.inst 291102500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 302879500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 593982000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 3187 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 3187 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5165 # number of ReadCleanReq accesses(hits+misses) @@ -668,8 +674,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3187 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution @@ -677,22 +684,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 534528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 842944 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9330 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13288 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 9330 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9330 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10485000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 0e0bba79f..b6e4d84e4 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.067874 # Number of seconds simulated -sim_ticks 67874346000 # Number of ticks simulated -final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067897 # Number of seconds simulated +sim_ticks 67896839000 # Number of ticks simulated +final_tick 67896839000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238872 # Simulator instruction rate (inst/s) -host_op_rate 238872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43169272 # Simulator tick rate (ticks/s) -host_mem_usage 305488 # Number of bytes of host memory used -host_seconds 1572.28 # Real time elapsed on the host +host_inst_rate 250075 # Simulator instruction rate (inst/s) +host_op_rate 250075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45208847 # Simulator tick rate (ticks/s) +host_mem_usage 305364 # Number of bytes of host memory used +host_seconds 1501.85 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 220544 # Nu system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory system.physmem.num_reads::total 7435 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3249298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3761303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7010602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3249298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3249298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3249298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3761303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3248222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3760057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7008279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3248222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3248222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3248222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3760057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7008279 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7435 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7435 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 67874250500 # Total gap between requests +system.physmem.totGap 67896729500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 925 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.437870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.390396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.239962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 445 32.91% 32.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 293 21.67% 54.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 153 11.32% 65.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 95 7.03% 72.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 4.66% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.88% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 2.96% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 2.22% 85.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 194 14.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation -system.physmem.totQLat 65565000 # Total ticks spent queuing -system.physmem.totMemAccLat 204971250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.928942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 210.322228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 345.388131 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 435 32.20% 32.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 296 21.91% 54.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 157 11.62% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 94 6.96% 72.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.66% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 44 3.26% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.96% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 2.22% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 192 14.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1351 # Bytes accessed per row activation +system.physmem.totQLat 64430000 # Total ticks spent queuing +system.physmem.totMemAccLat 203836250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37175000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8818.43 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8665.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27568.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27415.77 # Average memory access latency per DRAM burst system.physmem.avgRdBW 7.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 7.01 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6075 # Number of row buffer hits during reads +system.physmem.readRowHits 6082 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9129018.22 # Average gap between requests -system.physmem.pageHitRate 81.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5866560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3201000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32260800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9132041.63 # Average gap between requests +system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5851440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3192750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32416800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2086073460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 38893911750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 45454431090 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.698264 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 64700624500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2266420000 # Time in different power states +system.physmem_0.refreshEnergy 4434643200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2090127870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38904370500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 45470602560 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.706043 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 64718030250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2267200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 905970500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 911143500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4354560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2376000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25482600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25529400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1937209410 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 39024494250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 45427034340 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.294616 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 64919021500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2266420000 # Time in different power states +system.physmem_1.refreshEnergy 4434643200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1924310025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 39049824750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 45441049620 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.270777 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 64961032000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2267200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 687756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 668141750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 50012521 # Number of BP lookups -system.cpu.branchPred.condPredicted 28997086 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 979524 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24735831 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22942844 # Number of BTB hits +system.cpu.branchPred.lookups 50014651 # Number of BP lookups +system.cpu.branchPred.condPredicted 28998018 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978942 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24722016 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22941909 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.751458 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9100143 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.799507 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9101024 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 303 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 102391599 # DTB read hits -system.cpu.dtb.read_misses 62990 # DTB read misses +system.cpu.dtb.read_hits 102396635 # DTB read hits +system.cpu.dtb.read_misses 63118 # DTB read misses system.cpu.dtb.read_acv 49453 # DTB read access violations -system.cpu.dtb.read_accesses 102454589 # DTB read accesses -system.cpu.dtb.write_hits 78819200 # DTB write hits +system.cpu.dtb.read_accesses 102459753 # DTB read accesses +system.cpu.dtb.write_hits 78818401 # DTB write hits system.cpu.dtb.write_misses 1456 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 78820656 # DTB write accesses -system.cpu.dtb.data_hits 181210799 # DTB hits -system.cpu.dtb.data_misses 64446 # DTB misses +system.cpu.dtb.write_accesses 78819857 # DTB write accesses +system.cpu.dtb.data_hits 181215036 # DTB hits +system.cpu.dtb.data_misses 64574 # DTB misses system.cpu.dtb.data_acv 49455 # DTB access violations -system.cpu.dtb.data_accesses 181275245 # DTB accesses -system.cpu.itb.fetch_hits 49841893 # ITB hits +system.cpu.dtb.data_accesses 181279610 # DTB accesses +system.cpu.itb.fetch_hits 49842949 # ITB hits system.cpu.itb.fetch_misses 342 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 49842235 # ITB accesses +system.cpu.itb.fetch_accesses 49843291 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,140 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 135748695 # number of cpu cycles simulated +system.cpu.numCycles 135793681 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 50498280 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448284151 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50012521 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32042987 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 83907127 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2061462 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 50500103 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448292718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50014651 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32042933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 83951008 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2060866 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 13448 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 49841893 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 439921 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 135449808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.309596 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.352335 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 49842949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 438776 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 135495214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.308550 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.352263 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 56539159 41.74% 41.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4401809 3.25% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7053804 5.21% 50.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5366390 3.96% 54.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11526105 8.51% 62.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7792927 5.75% 68.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5844960 4.32% 72.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1860483 1.37% 74.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35064171 25.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56579471 41.76% 41.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4403688 3.25% 45.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7055956 5.21% 50.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5366912 3.96% 54.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11526073 8.51% 62.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7794072 5.75% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5845240 4.31% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1860126 1.37% 74.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35063676 25.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 135449808 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.368420 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.302309 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 43878250 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15711242 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 70556820 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4276924 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1026572 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9420233 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 135495214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368314 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.301278 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 43850651 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15792236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70529676 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4296377 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1026274 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9420515 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 4199 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 443516613 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 443538757 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1026572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45656178 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5038667 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72948338 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10260451 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440529832 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 437774 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2529018 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2798103 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3728351 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 287391913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 579992044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 412277767 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 167714276 # Number of floating rename lookups +system.cpu.rename.SquashCycles 1026274 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45639997 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5068254 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72928908 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10312435 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440551913 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 438641 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2536044 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2850928 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3712864 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 287405500 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 580024697 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 412290195 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 167734501 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27859584 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37459 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 27873171 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37458 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15899092 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104653375 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80643825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12436283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9680421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 409213494 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 16037778 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104660927 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80646144 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12483488 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9717177 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 409234709 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 402403006 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 455901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 33638980 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16018200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 402404750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 453779 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33660195 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16045960 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 135449808 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.970864 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.211480 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 135495214 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.969882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.211663 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21699625 16.02% 16.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19301136 14.25% 30.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22441860 16.57% 46.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18632936 13.76% 60.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19381094 14.31% 74.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13936411 10.29% 85.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9566467 7.06% 92.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6208123 4.58% 96.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4282156 3.16% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21727779 16.04% 16.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19323046 14.26% 30.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22437590 16.56% 46.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18638995 13.76% 60.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19382000 14.30% 74.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13933331 10.28% 85.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9554257 7.05% 92.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6216386 4.59% 96.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4281830 3.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 135449808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 135495214 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 249921 1.26% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 142099 0.71% 1.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 92744 0.47% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 4235 0.02% 2.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3484759 17.51% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1673016 8.41% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9313907 46.79% 75.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4943226 24.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 249431 1.25% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 142108 0.71% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 93369 0.47% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 4363 0.02% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3491173 17.54% 19.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1672209 8.40% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9312767 46.78% 75.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4941825 24.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 151496219 37.65% 37.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128363 0.53% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 151497707 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128305 0.53% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37051349 9.21% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7361129 1.83% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2793884 0.69% 49.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16753499 4.16% 54.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1596248 0.40% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37050665 9.21% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7361267 1.83% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793686 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16753119 4.16% 54.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1596202 0.40% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.48% # Type of FU issued @@ -448,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103848617 25.81% 80.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79340117 19.72% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103852879 25.81% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79337339 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 402403006 # Type of FU issued -system.cpu.iq.rate 2.964323 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19903907 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049463 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 615743047 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 258422157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234653025 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 344872581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 184503638 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 162319054 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 242850926 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179422406 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19947233 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 402404750 # Type of FU issued +system.cpu.iq.rate 2.963354 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19907245 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 615781749 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 258431172 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234656399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 344883989 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 184537520 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162320770 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 242844978 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 179433436 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19957407 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9898888 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123887 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 73372 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7123096 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9906440 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 125316 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 73841 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7125415 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 383831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 383693 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3808 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1026572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3903842 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 90265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 434136051 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 99585 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104653375 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80643825 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1026274 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3908203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111577 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 434157595 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 99580 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104660927 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80646144 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 295 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7679 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82299 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 73372 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 826459 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 307772 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1134231 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 399253806 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 102504065 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3149200 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 8166 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 103056 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 73841 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 825839 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 307783 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1133622 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 399257785 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102509229 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3146965 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24922262 # number of nop insts executed -system.cpu.iew.exec_refs 181324750 # number of memory reference insts executed -system.cpu.iew.exec_branches 46546315 # Number of branches executed -system.cpu.iew.exec_stores 78820685 # Number of stores executed -system.cpu.iew.exec_rate 2.941124 # Inst execution rate -system.cpu.iew.wb_sent 397727618 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396972079 # cumulative count of insts written-back -system.cpu.iew.wb_producers 196558282 # num instructions producing a value -system.cpu.iew.wb_consumers 281889088 # num instructions consuming a value +system.cpu.iew.exec_nop 24922591 # number of nop insts executed +system.cpu.iew.exec_refs 181329115 # number of memory reference insts executed +system.cpu.iew.exec_branches 46548281 # Number of branches executed +system.cpu.iew.exec_stores 78819886 # Number of stores executed +system.cpu.iew.exec_rate 2.940179 # Inst execution rate +system.cpu.iew.wb_sent 397733168 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396977169 # cumulative count of insts written-back +system.cpu.iew.wb_producers 196565794 # num instructions producing a value +system.cpu.iew.wb_consumers 281908418 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.924316 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697289 # average fanout of values written-back +system.cpu.iew.wb_rate 2.923385 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697268 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35472304 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35494113 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 975365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130528765 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.054228 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.231390 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 974783 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130571429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.053230 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.231493 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 46472448 35.60% 35.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17656165 13.53% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9417491 7.21% 56.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8632138 6.61% 62.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6273043 4.81% 67.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4304526 3.30% 71.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4966466 3.80% 74.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2588480 1.98% 76.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30218008 23.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46510589 35.62% 35.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17663753 13.53% 49.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9427402 7.22% 56.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8631802 6.61% 62.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6252911 4.79% 67.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4309640 3.30% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4961322 3.80% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2589236 1.98% 76.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30224774 23.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130528765 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130571429 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,32 +571,32 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 30218008 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 534444667 # The number of ROB reads -system.cpu.rob.rob_writes 873208037 # The number of ROB writes -system.cpu.timesIdled 3160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 298887 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30224774 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 534502374 # The number of ROB reads +system.cpu.rob.rob_writes 873254462 # The number of ROB writes +system.cpu.timesIdled 3162 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298467 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.361442 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.361442 # CPI: Total CPI of All Threads -system.cpu.ipc 2.766692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.766692 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 399091287 # number of integer regfile reads -system.cpu.int_regfile_writes 169885620 # number of integer regfile writes -system.cpu.fp_regfile_reads 156870882 # number of floating regfile reads -system.cpu.fp_regfile_writes 104904950 # number of floating regfile writes +system.cpu.cpi 0.361562 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.361562 # CPI: Total CPI of All Threads +system.cpu.ipc 2.765775 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.765775 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 399095542 # number of integer regfile reads +system.cpu.int_regfile_writes 169885767 # number of integer regfile writes +system.cpu.fp_regfile_reads 156866113 # number of floating regfile reads +system.cpu.fp_regfile_writes 104908933 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 777 # number of replacements -system.cpu.dcache.tags.tagsinuse 3293.050932 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 155556653 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3293.060025 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 155551655 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4177 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37241.238449 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37240.041896 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3293.050932 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3293.060025 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803970 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803970 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -604,44 +604,44 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 311160441 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 311160441 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82055589 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82055589 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 311150441 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 311150441 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82050592 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82050592 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501057 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501057 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 155556647 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 155556647 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 155556647 # number of overall hits -system.cpu.dcache.overall_hits::total 155556647 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21479 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21479 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21479 # number of overall misses -system.cpu.dcache.overall_misses::total 21479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128709000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128709000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1198982453 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1198982453 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1327691453 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1327691453 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1327691453 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1327691453 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82057397 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82057397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 155551649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 155551649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 155551649 # number of overall hits +system.cpu.dcache.overall_hits::total 155551649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1805 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1805 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19672 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19672 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21477 # number of overall misses +system.cpu.dcache.overall_misses::total 21477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128536500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128536500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1197114453 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1197114453 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1325650953 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1325650953 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1325650953 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1325650953 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82052397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82052397 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 155578126 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 155578126 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 155578126 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 155578126 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 155573126 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 155573126 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 155573126 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 155573126 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses @@ -650,32 +650,32 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71188.606195 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71188.606195 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60951.779421 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60951.779421 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61813.466782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61813.466782 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49798 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71211.357341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71211.357341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60853.723719 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60853.723719 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61724.214415 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61724.214415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61724.214415 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61724.214415 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49394 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 748 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.574866 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.034759 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 86 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 656 # number of writebacks system.cpu.dcache.writebacks::total 656 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 820 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 820 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16482 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16482 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17302 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17302 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17302 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17302 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 817 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 817 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16483 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16483 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17300 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 988 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 988 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3189 # number of WriteReq MSHR misses @@ -684,14 +684,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4177 system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75199500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75199500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 250368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 250368000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 325567500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 325567500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 325567500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 325567500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 74845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 74845500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 249448500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 249448500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 324294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 324294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 324294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 324294000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -700,130 +700,134 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76112.854251 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76112.854251 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78509.877705 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78509.877705 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77942.901604 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77942.901604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77942.901604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77942.901604 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75754.554656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75754.554656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78221.542803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78221.542803 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77638.017716 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77638.017716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77638.017716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77638.017716 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2126 # number of replacements -system.cpu.icache.tags.tagsinuse 1833.088267 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 49836296 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1833.091155 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 49837345 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4054 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12293.116922 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 12293.375678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1833.088267 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.895063 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.895063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1833.091155 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.895064 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.895064 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1353 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 99687840 # Number of tag accesses -system.cpu.icache.tags.data_accesses 99687840 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 49836296 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 49836296 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 49836296 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 49836296 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 49836296 # number of overall hits -system.cpu.icache.overall_hits::total 49836296 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5597 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5597 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5597 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5597 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5597 # number of overall misses -system.cpu.icache.overall_misses::total 5597 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 364082499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 364082499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 364082499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 364082499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 364082499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 364082499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 49841893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 49841893 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 49841893 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 49841893 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 49841893 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 49841893 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 99689952 # Number of tag accesses +system.cpu.icache.tags.data_accesses 99689952 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 49837345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 49837345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 49837345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 49837345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 49837345 # number of overall hits +system.cpu.icache.overall_hits::total 49837345 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5604 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5604 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5604 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5604 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5604 # number of overall misses +system.cpu.icache.overall_misses::total 5604 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365347499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365347499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365347499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365347499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365347499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365347499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 49842949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 49842949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 49842949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 49842949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 49842949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 49842949 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65049.579954 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65049.579954 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65049.579954 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65049.579954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65049.579954 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65049.579954 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65194.057637 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65194.057637 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65194.057637 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65194.057637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65194.057637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65194.057637 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 644 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.857143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1543 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1543 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1543 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1543 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1543 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1543 # number of overall MSHR hits +system.cpu.icache.writebacks::writebacks 2126 # number of writebacks +system.cpu.icache.writebacks::total 2126 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1550 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1550 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1550 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1550 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1550 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1550 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4054 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4054 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4054 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 4054 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4054 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4054 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 273657000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 273657000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 273657000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 273657000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 273657000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 273657000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 273942500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 273942500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 273942500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 273942500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 273942500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 273942500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67502.960039 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67502.960039 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67502.960039 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67502.960039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67502.960039 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67502.960039 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67573.384312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67573.384312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67573.384312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67573.384312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67573.384312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67573.384312 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4002.026272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4002.038570 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3073 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4841 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.634786 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.009955 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2970.733849 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 660.282469 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.011804 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2970.742908 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 660.283858 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011322 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020150 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122132 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122133 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4841 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4030 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.147736 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 97102 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 97102 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 656 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 656 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 656 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 656 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2126 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2126 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 608 # number of ReadCleanReq hits @@ -848,20 +852,22 @@ system.cpu.l2cache.demand_misses::total 7435 # nu system.cpu.l2cache.overall_misses::cpu.inst 3446 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses system.cpu.l2cache.overall_misses::total 7435 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 244858000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 244858000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261180500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 261180500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72283000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 72283000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261180500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 317141000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 578321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261180500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 317141000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 578321500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 656 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 656 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 243935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 243935500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261376000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 261376000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 71927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 261376000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 315863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 577239000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 261376000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 315863000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 577239000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 656 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 656 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2126 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2126 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3189 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3189 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4054 # number of ReadCleanReq accesses(hits+misses) @@ -886,18 +892,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.903292 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.850025 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.954992 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.903292 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78254.394375 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78254.394375 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75792.367963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75792.367963 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84050 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84050 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75792.367963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79503.885686 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77783.658373 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75792.367963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79503.885686 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77783.658373 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77959.571748 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77959.571748 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75849.100406 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75849.100406 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83636.627907 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83636.627907 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75849.100406 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79183.504638 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77638.063215 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75849.100406 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79183.504638 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77638.063215 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,18 +924,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7435 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3446 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 213568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 213568000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226720500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226720500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63683000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63683000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226720500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 277251000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 503971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226720500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 277251000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 503971500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 212645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 212645500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226916000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226916000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63327500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63327500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226916000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 502889000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226916000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275973000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 502889000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981185 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981185 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for ReadCleanReq accesses @@ -942,18 +948,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.903292 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954992 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.903292 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68254.394375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68254.394375 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65792.367963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65792.367963 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74050 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67959.571748 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67959.571748 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65849.100406 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65849.100406 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73636.627907 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73636.627907 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65849.100406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69183.504638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67638.063215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65849.100406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69183.504638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67638.063215 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 11134 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2903 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -962,8 +968,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 121 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4054 # Transaction distribution @@ -971,22 +978,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9131 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 19365 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 395520 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 704832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8231 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11134 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8231 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8231 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 8349000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 6081000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1011,9 +1018,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7435 # Request fanout histogram -system.membus.reqLayer0.occupancy 9180000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9238500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39204250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39203500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index b9717df42..8253a646b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335097500 # Number of ticks simulated -final_tick 567335097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.567385 # Number of seconds simulated +sim_ticks 567385356500 # Number of ticks simulated +final_tick 567385356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1348015 # Simulator instruction rate (inst/s) -host_op_rate 1348015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1918345002 # Simulator tick rate (ticks/s) -host_mem_usage 301916 # Number of bytes of host memory used -host_seconds 295.74 # Real time elapsed on the host +host_inst_rate 1390819 # Simulator instruction rate (inst/s) +host_op_rate 1390819 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1979434182 # Simulator tick rate (ticks/s) +host_mem_usage 302276 # Number of bytes of host memory used +host_seconds 286.64 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 205120 # Nu system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361550 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 361518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 809214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 361518 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 361518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 809214 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670195 # number of cpu cycles simulated +system.cpu.numCycles 1134770713 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -82,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670195 # Number of busy cycles +system.cpu.num_busy_cycles 1134770713 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -122,14 +122,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930558 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3288.807028 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930558 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.807028 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id @@ -155,14 +155,14 @@ system.cpu.dcache.demand_misses::cpu.data 4152 # n system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 52888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 52888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195593000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195593000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 248481500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 248481500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 248481500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -179,14 +179,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55672.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55672.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61084.634603 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61084.634603 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59846.218690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59846.218690 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,14 +205,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 46134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 46134000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 170388000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 170388000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216522000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 216522000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216522000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 216522000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51938500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 192391000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 244329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 244329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 244329500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -221,28 +221,28 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52148.843931 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54672.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60084.634603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58846.218690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58846.218690 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138955 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.084430 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138955 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.084430 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.876506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.876506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id @@ -260,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182363500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182363500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182363500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182363500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182363500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182363500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 204815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 204815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 204815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 204815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 204815000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -278,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49649.741356 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49649.741356 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49649.741356 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49649.741356 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49649.741356 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55762.319630 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55762.319630 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55762.319630 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55762.319630 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,55 +292,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1769 # number of writebacks +system.cpu.icache.writebacks::total 1769 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178690500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178690500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178690500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178690500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178690500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178690500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 201142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 201142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 201142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 201142000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48649.741356 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48649.741356 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48649.741356 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48649.741356 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54762.319630 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54762.319630 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54762.319630 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485272 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3772.330397 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2561 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.560885 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475155 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 371.516873 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.363420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.450105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.115122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 90632 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 90632 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits @@ -365,20 +369,22 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 168265000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 168265000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43417500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 43417500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 168265000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 376637500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 168265000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 376637500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 186953000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 190709000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 49213500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 190709000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 236166500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 426875500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 190709000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 236166500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 426875500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +409,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52500.780031 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52500.780031 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.348481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.780031 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.348481 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59501.273074 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.588144 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59508.464329 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.136326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.588144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59502.771479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.136326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,18 +441,18 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133535000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 136215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 136215000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 136215000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168682500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 304897500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 136215000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168682500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 304897500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 155533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 158659000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 40943500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 158659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 196476500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 355135500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 158659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 196476500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 355135500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses @@ -459,18 +465,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42500.780031 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42500.780031 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42500.780031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.348481 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49501.273074 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.588144 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49508.464329 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.588144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49502.771479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.136326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -479,8 +485,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution @@ -488,22 +495,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10358 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10358 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10358 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5828000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -528,9 +535,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7176500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35872500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 5974a793e..54314baaf 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.215510 # Number of seconds simulated -sim_ticks 215510486500 # Number of ticks simulated -final_tick 215510486500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215512 # Number of seconds simulated +sim_ticks 215512229500 # Number of ticks simulated +final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166248 # Simulator instruction rate (inst/s) -host_op_rate 199599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131220473 # Simulator tick rate (ticks/s) -host_mem_usage 326292 # Number of bytes of host memory used -host_seconds 1642.35 # Real time elapsed on the host +host_inst_rate 175368 # Simulator instruction rate (inst/s) +host_op_rate 210548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 138419960 # Simulator tick rate (ticks/s) +host_mem_usage 326400 # Number of bytes of host memory used +host_seconds 1556.94 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 218880 # Nu system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1015635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1235986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2251621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1015635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1015635 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1015635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1235986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2251621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1015627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1235976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1235976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251603 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 215510247500 # Total gap between requests +system.physmem.totGap 215511990500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 894 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 319.408190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.009179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.260420 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.26% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.85% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 166 10.96% 70.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 79 5.22% 75.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.15% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.17% 83.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.44% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 1.78% 87.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 12.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1514 # Bytes accessed per row activation -system.physmem.totQLat 52026250 # Total ticks spent queuing -system.physmem.totMemAccLat 194188750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1510 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 320.169536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.396997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.756940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 36.42% 36.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 336 22.25% 58.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.85% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.83% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 74 4.90% 80.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.44% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.19% 85.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.92% 87.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 184 12.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1510 # Bytes accessed per row activation +system.physmem.totQLat 54741000 # Total ticks spent queuing +system.physmem.totMemAccLat 196903500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6861.81 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7219.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25611.81 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25969.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,47 +216,47 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6062 # Number of row buffer hits during reads +system.physmem.readRowHits 6065 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.95 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28423931.35 # Average gap between requests -system.physmem.pageHitRate 79.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28424161.24 # Average gap between requests +system.physmem.pageHitRate 79.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5019840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2739000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5660638650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124339380000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144113699910 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.715971 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206848311250 # Time in different power states +system.physmem_0.actBackEnergy 5641560180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124356115500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144111263400 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.704665 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206876360250 # Time in different power states system.physmem_0.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1464242250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1436474750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6388200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3485625 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 6373080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3477375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 14075923680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5785657605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124229714250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144130146360 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.792285 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 206662748250 # Time in different power states +system.physmem_1.actBackEnergy 5809762620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124208569500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144133083255 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.805913 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206629350750 # Time in different power states system.physmem_1.memoryStateTime::REF 7196280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1649073000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1684213750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 32816918 # Number of BP lookups -system.cpu.branchPred.condPredicted 16892730 # Number of conditional branches predicted +system.cpu.branchPred.lookups 32816919 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892731 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17497037 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15468342 # Number of BTB hits +system.cpu.branchPred.BTBLookups 17497038 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468343 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.405494 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 88.405495 # BTB Hit Percentage system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 431020973 # number of cpu cycles simulated +system.cpu.numCycles 431024459 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.discardedOps 3889164 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.578612 # CPI: cycles per instruction -system.cpu.ipc 0.633468 # IPC: instructions per cycle -system.cpu.tickCycles 427416493 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3604480 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578625 # CPI: cycles per instruction +system.cpu.ipc 0.633463 # IPC: instructions per cycle +system.cpu.tickCycles 427416966 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3607493 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.814208 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3085.807941 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168714884 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37400.772334 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814208 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.807941 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753371 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753371 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -430,14 +430,14 @@ system.cpu.dcache.demand_misses::cpu.data 7285 # n system.cpu.dcache.demand_misses::total 7285 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 136254500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 136254500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 393515500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 393515500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 529770000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 529770000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 529770000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 529770000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 138607500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 138607500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 393622500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 393622500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 532230000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 532230000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 532230000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 532230000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86584168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -462,14 +462,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66175.084993 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66175.084993 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75299.559893 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75299.559893 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72720.658888 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72720.658888 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72670.781893 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72670.781893 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73058.339053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73008.230453 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -498,16 +498,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4508 system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109975000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 109975000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219249000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 219249000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 111882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 111882000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219521500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219521500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329224000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329224000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329462000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329462000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 331403500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 331403500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 331641500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 331641500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -518,26 +518,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67139.804640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67139.804640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76393.379791 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76393.379791 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73031.055901 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73031.055901 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73035.247174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73035.247174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36873 # number of replacements -system.cpu.icache.tags.tagsinuse 1923.840697 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 72548791 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1869.380582 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36871 # number of replacements +system.cpu.icache.tags.tagsinuse 1923.837997 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548794 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38807 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.477002 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1923.840697 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939375 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939375 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.837997 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939374 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939374 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id @@ -547,42 +547,42 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 145214011 # Number of tag accesses system.cpu.icache.tags.data_accesses 145214011 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 72548791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 72548791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 72548791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 72548791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 72548791 # number of overall hits -system.cpu.icache.overall_hits::total 72548791 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses -system.cpu.icache.overall_misses::total 38810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 740838000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 740838000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 740838000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 740838000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 740838000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 740838000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 72587601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 72587601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 72587601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 72587601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 72587601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 72587601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548794 # number of overall hits +system.cpu.icache.overall_hits::total 72548794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38808 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38808 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38808 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38808 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38808 # number of overall misses +system.cpu.icache.overall_misses::total 38808 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 741346000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 741346000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 741346000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 741346000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 741346000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 741346000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587602 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587602 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587602 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587602 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587602 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587602 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19088.843082 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19102.916924 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19102.916924 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19102.916924 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19102.916924 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19102.916924 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19102.916924 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,40 +591,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # 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average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18088.868848 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18088.868848 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18088.868848 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18102.942692 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18102.942692 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18102.942692 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18102.942692 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18102.942692 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.200424 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.332133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 353.814210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.192128 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.329945 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010798 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020701 # Average percentage of cache occupancy @@ -636,22 +638,24 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1250 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # 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number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 215012500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 215012500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 257866500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 257866500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 106408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 257866500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321420500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 579287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 257866500 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088178 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.176035 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088173 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.176043 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088178 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.176035 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75242.291521 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75242.291521 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75199.883109 # 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miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75337.245971 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -744,79 +750,80 @@ system.cpu.l2cache.demand_mshr_misses::total 7582 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186201500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186201500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 222999500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 222999500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88418500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 222999500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 497619500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 222999500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274620000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 497619500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 186472500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 186472500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223532000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223532000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90324000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90324000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223532000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 276796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 500328500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223532000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 276796500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 500328500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088126 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.175027 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088126 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65242.291521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65242.291521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65204.532164 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65204.532164 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67598.241590 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67598.241590 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65204.532164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65982.700625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65631.693485 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.175027 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 81548 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 38331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 81544 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 38329 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15017 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 21970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99585 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 109845 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3889728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4243072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.369574 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.482692 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.476679 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 51410 63.04% 63.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 30138 36.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 28198 65.09% 65.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15121 34.91% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 43319 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 78653000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58211498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6787957 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 4728 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution @@ -837,9 +844,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7582 # Request fanout histogram -system.membus.reqLayer0.occupancy 8866500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40241250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40239750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index b3c953357..8af356e7f 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112728 # Number of seconds simulated -sim_ticks 112728298500 # Number of ticks simulated -final_tick 112728298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.116576 # Number of seconds simulated +sim_ticks 116576497500 # Number of ticks simulated +final_tick 116576497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116763 # Simulator instruction rate (inst/s) -host_op_rate 140187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48207604 # Simulator tick rate (ticks/s) -host_mem_usage 330392 # Number of bytes of host memory used -host_seconds 2338.39 # Real time elapsed on the host +host_inst_rate 122787 # Simulator instruction rate (inst/s) +host_op_rate 147419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52425325 # Simulator tick rate (ticks/s) +host_mem_usage 336136 # Number of bytes of host memory used +host_seconds 2223.67 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169408 # Number of bytes read from this memory -system.physmem.bytes_read::total 469184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1762 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2647 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7331 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1658927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1000352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1502799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4162078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1658927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1658927 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1658927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1000352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1502799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4162078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7331 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 620608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4625216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169088 # Number of bytes read from this memory +system.physmem.bytes_read::total 5414912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 620608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 620608 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 72269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2642 # Number of read requests responded to by this memory +system.physmem.num_reads::total 84608 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 5323612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39675373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1450447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46449431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5323612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5323612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5323612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39675373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1450447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 46449431 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 84608 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7331 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 84608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 469184 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 5414912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 469184 # Total read bytes from the system interface side +system.physmem.bytesReadSys 5414912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 589 # Per bank write bursts -system.physmem.perBankRdBursts::1 789 # Per bank write bursts -system.physmem.perBankRdBursts::2 601 # Per bank write bursts -system.physmem.perBankRdBursts::3 520 # Per bank write bursts -system.physmem.perBankRdBursts::4 444 # Per bank write bursts -system.physmem.perBankRdBursts::5 345 # Per bank write bursts -system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 255 # Per bank write bursts -system.physmem.perBankRdBursts::8 219 # Per bank write bursts -system.physmem.perBankRdBursts::9 290 # Per bank write bursts -system.physmem.perBankRdBursts::10 315 # Per bank write bursts -system.physmem.perBankRdBursts::11 411 # Per bank write bursts -system.physmem.perBankRdBursts::12 547 # Per bank write bursts -system.physmem.perBankRdBursts::13 678 # Per bank write bursts -system.physmem.perBankRdBursts::14 620 # Per bank write bursts -system.physmem.perBankRdBursts::15 555 # Per bank write bursts +system.physmem.perBankRdBursts::0 955 # Per bank write bursts +system.physmem.perBankRdBursts::1 811 # Per bank write bursts +system.physmem.perBankRdBursts::2 833 # Per bank write bursts +system.physmem.perBankRdBursts::3 2939 # Per bank write bursts +system.physmem.perBankRdBursts::4 10638 # Per bank write bursts +system.physmem.perBankRdBursts::5 59815 # Per bank write bursts +system.physmem.perBankRdBursts::6 159 # Per bank write bursts +system.physmem.perBankRdBursts::7 253 # Per bank write bursts +system.physmem.perBankRdBursts::8 227 # Per bank write bursts +system.physmem.perBankRdBursts::9 304 # Per bank write bursts +system.physmem.perBankRdBursts::10 3835 # Per bank write bursts +system.physmem.perBankRdBursts::11 811 # Per bank write bursts +system.physmem.perBankRdBursts::12 1140 # Per bank write bursts +system.physmem.perBankRdBursts::13 693 # Per bank write bursts +system.physmem.perBankRdBursts::14 643 # Per bank write bursts +system.physmem.perBankRdBursts::15 552 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112728140000 # Total gap between requests +system.physmem.totGap 116576339000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7331 # Read request sizes (log2) +system.physmem.readPktSize::6 84608 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,20 +94,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 64943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 339.670794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.560456 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.691004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 480 34.96% 34.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 312 22.72% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 141 10.27% 67.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 79 5.75% 73.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 4.01% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.50% 81.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 1.68% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 27 1.97% 84.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 208 15.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1373 # Bytes accessed per row activation -system.physmem.totQLat 90206647 # Total ticks spent queuing -system.physmem.totMemAccLat 227662897 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36655000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12304.82 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 22133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 244.635973 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.851890 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 150.002141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 2617 11.82% 11.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8410 38.00% 49.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7826 35.36% 85.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1287 5.81% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1278 5.77% 96.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 443 2.00% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 0.14% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 31 0.14% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 209 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22133 # Bytes accessed per row activation +system.physmem.totQLat 841966540 # Total ticks spent queuing +system.physmem.totMemAccLat 2428366540 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 423040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9951.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31054.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28701.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 46.45 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.16 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 46.45 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.36 # Data bus utilization in percentage +system.physmem.busUtilRead 0.36 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5948 # Number of row buffer hits during reads +system.physmem.readRowHits 62473 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.13 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15376911.74 # Average gap between requests -system.physmem.pageHitRate 81.13 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4815720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2627625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 28618200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 1377840.62 # Average gap between requests +system.physmem.pageHitRate 73.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 142967160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 78007875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 595896600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3214163025 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64813639500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75426287190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.136639 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107820696894 # Time in different power states -system.physmem_0.memoryStateTime::REF 3764020000 # Time in different power states +system.physmem_0.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63983016135 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 13820144250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 86234192340 # Total energy per rank (pJ) +system.physmem_0.averagePower 739.725124 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22625694019 # Time in different power states +system.physmem_0.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1137632606 # Time in different power states +system.physmem_0.memoryStateTime::ACT 90057594731 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5511240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3007125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28126800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 24358320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 13290750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 63999000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7362423120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3285750465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64750835250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75435654000 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.219817 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107714946135 # Time in different power states -system.physmem_1.memoryStateTime::REF 3764020000 # Time in different power states +system.physmem_1.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11183516280 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 60135495000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 79034819670 # Total energy per rank (pJ) +system.physmem_1.averagePower 677.968219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 99984327847 # Time in different power states +system.physmem_1.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1243230865 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12698960903 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37743002 # Number of BP lookups -system.cpu.branchPred.condPredicted 20164593 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746138 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18663724 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17299181 # Number of BTB hits +system.cpu.branchPred.lookups 37744347 # Number of BP lookups +system.cpu.branchPred.condPredicted 20165678 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746151 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18664383 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17300356 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.688796 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7223599 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.691818 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7223561 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3816 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,129 +381,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225456598 # number of cpu cycles simulated +system.cpu.numCycles 233152996 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12486047 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334063522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37743002 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24522780 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210891035 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3510673 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1258 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2507 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89094273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21774 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 225136183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.799914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229503 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12613908 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334078036 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37744347 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24523917 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 217730983 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3511013 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89097958 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 22048 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.745924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.249191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51412756 22.84% 22.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42958324 19.08% 41.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30027813 13.34% 55.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100737290 44.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58364727 25.15% 25.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42980177 18.52% 43.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30021674 12.93% 56.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100737568 43.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 225136183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167407 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.481720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27896248 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63927882 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108602791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23088664 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620598 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880038 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135173 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363542969 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6170181 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45231914 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 18002517 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341926 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113354912 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46584316 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355763735 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2890412 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6625666 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 177937 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7803151 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21129906 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 2817742 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403401676 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2534003745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350242817 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194894499 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.161887 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.432870 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28023980 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70770838 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108573375 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23115192 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620761 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880073 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135178 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363549116 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6170266 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620761 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45363672 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 24814789 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341990 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113350212 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46612722 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355770088 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2890615 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6644499 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 177384 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7802434 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21145232 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2810415 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403411912 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2534053104 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350245362 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194900491 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31171625 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17025 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55451024 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92416595 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88498352 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1661185 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1846398 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353252669 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28026 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346437634 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2301476 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 25469093 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73749076 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 225136183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.538791 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.099493 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31181861 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16825 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 16811 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55467243 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92417326 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88498414 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1663819 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1859064 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353254299 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27832 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346438253 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2301561 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 25470529 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73751649 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5712 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 232104146 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.492598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113201 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40701776 18.08% 18.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78366146 34.81% 52.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60939580 27.07% 79.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34977344 15.54% 95.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9507598 4.22% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 632530 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 11209 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47511470 20.47% 20.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78618745 33.87% 54.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 60884809 26.23% 80.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34936770 15.05% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9533364 4.11% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 607804 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 11184 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 225136183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 232104146 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9586225 7.69% 7.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7350 0.01% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 255762 0.21% 7.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 132929 0.11% 8.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 93071 0.07% 8.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 61949 0.05% 8.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 719141 0.58% 8.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 303244 0.24% 8.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 683031 0.55% 9.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53752847 43.14% 52.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 59000415 47.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9573854 7.69% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7345 0.01% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 255499 0.21% 7.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 127544 0.10% 8.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 93452 0.08% 8.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 56991 0.05% 8.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 707524 0.57% 8.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 297297 0.24% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 683417 0.55% 9.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53764278 43.17% 52.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58976477 47.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110655046 31.94% 31.94% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148359 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110655125 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148158 0.62% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued @@ -522,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6798342 1.96% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798099 1.96% 34.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667218 2.50% 37.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3332482 0.96% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592517 0.46% 38.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20930304 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8667622 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332487 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592703 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20931016 6.04% 44.49% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 7182327 2.07% 46.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148965 2.06% 48.63% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91923294 26.53% 75.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85883494 24.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91923310 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85883155 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346437634 # Type of FU issued -system.cpu.iq.rate 1.536605 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124595964 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.359649 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 757212589 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251740831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223259855 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287696302 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 127019209 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117423886 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 303336303 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167697295 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5085757 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346438253 # Type of FU issued +system.cpu.iq.rate 1.485884 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124543678 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.359497 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 764166784 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251741027 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223260031 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287659107 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 127022045 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117425060 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303322253 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167659678 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5063326 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6684320 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13571 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10256 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6122735 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6685051 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13552 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10416 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6122797 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 155306 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 607778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 155252 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 607596 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2118913 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 332541 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353281560 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620761 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2118966 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 346415 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353282999 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92416595 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88498352 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16993 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8047 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 339026 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10256 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 439070 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1659723 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342447875 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90703562 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3989759 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92417326 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88498414 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16799 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8049 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 352915 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10416 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220605 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439066 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659671 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342448265 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90703428 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3989988 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 865 # number of nop insts executed -system.cpu.iew.exec_refs 175290975 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752712 # Number of branches executed -system.cpu.iew.exec_stores 84587413 # Number of stores executed -system.cpu.iew.exec_rate 1.518908 # Inst execution rate -system.cpu.iew.wb_sent 340942422 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340683741 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153622639 # num instructions producing a value -system.cpu.iew.wb_consumers 266573014 # num instructions consuming a value +system.cpu.iew.exec_nop 868 # number of nop insts executed +system.cpu.iew.exec_refs 175290651 # number of memory reference insts executed +system.cpu.iew.exec_branches 31753222 # Number of branches executed +system.cpu.iew.exec_stores 84587223 # Number of stores executed +system.cpu.iew.exec_rate 1.468771 # Inst execution rate +system.cpu.iew.wb_sent 340943350 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340685091 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153596503 # num instructions producing a value +system.cpu.iew.wb_consumers 266530182 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.511083 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.576287 # average fanout of values written-back +system.cpu.iew.wb_rate 1.461208 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.576282 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23082594 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23083392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611400 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221410973 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.480560 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.051639 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611406 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 228378919 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.435387 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.036441 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87667745 39.60% 39.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 70465931 31.83% 71.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20808534 9.40% 80.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13377083 6.04% 86.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8762034 3.96% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4538069 2.05% 92.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3005918 1.36% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2461295 1.11% 95.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10324364 4.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 94653053 41.45% 41.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70419351 30.83% 72.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20855772 9.13% 81.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13391170 5.86% 87.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8734239 3.82% 91.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4529616 1.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3006865 1.32% 94.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2429241 1.06% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10359612 4.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221410973 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 228378919 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,182 +655,182 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction -system.cpu.commit.bw_lim_events 10324364 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 561978894 # The number of ROB reads -system.cpu.rob.rob_writes 705518745 # The number of ROB writes -system.cpu.timesIdled 51182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320415 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 10359612 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 568912390 # The number of ROB reads +system.cpu.rob.rob_writes 705520379 # The number of ROB writes +system.cpu.timesIdled 58444 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1048850 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.825736 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.825736 # CPI: Total CPI of All Threads -system.cpu.ipc 1.211041 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.211041 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331331297 # number of integer regfile reads -system.cpu.int_regfile_writes 136939218 # number of integer regfile writes -system.cpu.fp_regfile_reads 187106677 # number of floating regfile reads -system.cpu.fp_regfile_writes 132176732 # number of floating regfile writes -system.cpu.cc_regfile_reads 1297128117 # number of cc regfile reads -system.cpu.cc_regfile_writes 80240781 # number of cc regfile writes -system.cpu.misc_regfile_reads 1183123878 # number of misc regfile reads +system.cpu.cpi 0.853924 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.853924 # CPI: Total CPI of All Threads +system.cpu.ipc 1.171065 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.171065 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331328730 # number of integer regfile reads +system.cpu.int_regfile_writes 136938455 # number of integer regfile writes +system.cpu.fp_regfile_reads 187108865 # number of floating regfile reads +system.cpu.fp_regfile_writes 132177694 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297131127 # number of cc regfile reads +system.cpu.cc_regfile_writes 80243114 # number of cc regfile writes +system.cpu.misc_regfile_reads 1183136277 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533840 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.843429 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163621677 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534352 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.638944 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82703000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.843429 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533838 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844582 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163641356 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534350 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.651909 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 84508000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844582 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336594804 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336594804 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82588364 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82588364 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80941030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80941030 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70477 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70477 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 336640002 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336640002 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82608606 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82608606 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80940468 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80940468 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70474 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70474 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10911 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10911 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163529394 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163529394 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163599871 # number of overall hits -system.cpu.dcache.overall_hits::total 163599871 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2796859 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2796859 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1111669 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1111669 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 163549074 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163549074 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163619548 # number of overall hits +system.cpu.dcache.overall_hits::total 163619548 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2799218 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2799218 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1112231 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1112231 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3908528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3908528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3908546 # number of overall misses -system.cpu.dcache.overall_misses::total 3908546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22523988500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22523988500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8974716998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8974716998 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3911449 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3911449 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3911467 # number of overall misses +system.cpu.dcache.overall_misses::total 3911467 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31000710000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31000710000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973516996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8973516996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31498705498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31498705498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31498705498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31498705498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85385223 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85385223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 39974226996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39974226996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39974226996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39974226996 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85407824 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85407824 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70495 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70495 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70492 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70492 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10916 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10916 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167437922 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167437922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167508417 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167508417 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032756 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013548 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013548 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167460523 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167460523 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167531015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167531015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032775 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032775 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013555 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013555 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023343 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023343 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8053.315702 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 8053.315702 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8073.191749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8073.191749 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023348 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023348 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.033525 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.033525 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 8058.968875 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 8058.968875 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 8058.931761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 8058.931761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.800129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10219.800129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.753099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10219.753099 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1061983 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1061203 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 134750 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 134969 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 7.881135 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.862568 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966339 # number of writebacks -system.cpu.dcache.writebacks::total 966339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1483171 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1483171 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891014 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 891014 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1533838 # number of writebacks +system.cpu.dcache.writebacks::total 1533838 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1485532 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1485532 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891576 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 891576 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2374185 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2374185 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2374185 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2374185 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313688 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2377108 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2377108 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2377108 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2377108 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313686 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313686 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220655 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 220655 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534343 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534343 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534354 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534354 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10737741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10737741500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828416279 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828416279 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 682500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12566157779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12566157779 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12566840279 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12566840279 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015385 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534341 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534341 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534352 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534352 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15231288500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15231288500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828351773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828351773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059640273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17059640273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060321773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17060321773 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015381 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015381 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009164 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009164 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009160 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8173.737980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8173.737980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.312474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.312474 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62045.454545 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62045.454545 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8189.927402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8189.927402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8190.313499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8190.313499 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009162 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009162 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.020136 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.020136 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.545534 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.545534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.909985 # 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Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716490 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.345336 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 330590500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.829667 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999667 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -839,208 +840,210 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 246 system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178904656 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89094257 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008101 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008101 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008101 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8307.573670 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8307.573670 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8307.573670 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8307.573670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8307.573670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8307.573670 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 62233 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178912379 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178912379 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88375700 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88375700 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88375700 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88375700 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88375700 # number of overall hits +system.cpu.icache.overall_hits::total 88375700 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 722244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 722244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 722244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 722244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 722244 # number of overall misses +system.cpu.icache.overall_misses::total 722244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486041445 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 6486041445 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 6486041445 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 6486041445 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 6486041445 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 6486041445 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89097944 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89097944 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89097944 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89097944 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89097944 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89097944 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008106 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008106 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008106 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008106 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008106 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008106 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.401976 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8980.401976 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8980.401976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8980.401976 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 66919 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2180 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2190 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.547248 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.556621 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 31.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5641 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 5641 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 5641 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 5641 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 5641 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 5641 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716142 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 716142 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 716142 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 716142 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 716142 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 716142 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5575388455 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5575388455 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5575388455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5575388455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5575388455 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5575388455 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008038 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008038 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008038 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008038 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7785.311370 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7785.311370 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7785.311370 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7785.311370 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 715978 # number of writebacks +system.cpu.icache.writebacks::total 715978 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 5753 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 5753 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 5753 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 5753 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 5753 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 5753 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716491 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716491 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716491 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716491 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716491 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716491 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035132455 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6035132455 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035132455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6035132455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035132455 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6035132455 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008042 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008042 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008042 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.179712 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.179712 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404899 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404967 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 62 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404824 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404865 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 38 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28121 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28167 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5994.543426 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3840397 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7305 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 525.721697 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5610.545510 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3011470 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 6745 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 446.474426 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.183678 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.782296 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 613.575916 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 125.001536 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157177 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163622 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007629 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.365878 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 519 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6786 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 108.219059 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.335835 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006605 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.342441 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 498 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6247 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 771 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5745 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414185 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 68224984 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 68224984 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 966339 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966339 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 906 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5055 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.030396 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.381287 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 68984443 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 68984443 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 965413 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 965413 # 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number of cycles access was blocked @@ -1049,151 +1052,152 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 53 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 53 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 34 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 87 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 87 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 100 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30448 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 30448 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 44 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 44 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 33 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 33 # 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180856312 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50141500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50141500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638751500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638751500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4638052000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4638052000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4688193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5326945000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638751500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4688193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5507801312 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003349 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003349 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004085 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000779 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002082 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004085 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001148 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003299 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003299 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013544 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.054458 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.054458 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.036424 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015617 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5800.587395 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68702.300406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68702.300406 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62035.763176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62035.763176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67706.744868 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67706.744868 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64326.110162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62035.763176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68124.290579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5800.587395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13603.546197 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059358 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.491871 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.042590 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.042590 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.690847 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41234.391022 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4499965 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249489 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 27801 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 27801 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2029841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1033885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 31840 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 4500659 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249836 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 130203 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52857 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77346 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2030188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 965413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 81238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 52995 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 716142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313699 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2122562 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377748 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6500310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45775104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160044224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205819328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 32746 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4531805 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.116184 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320445 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 716491 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313697 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2123993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6501639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 90080128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 181970688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 272050816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134761 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2385076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.191571 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.468754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4005282 88.38% 88.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 526523 11.62% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2005511 84.09% 84.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 302219 12.67% 96.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 77346 3.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4531805 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3216321500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074578268 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2302086882 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2385076 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4500145500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1075017936 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2302043463 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 6592 # Transaction distribution +system.membus.trans_dist::ReadResp 83880 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 739 # Transaction distribution -system.membus.trans_dist::ReadExResp 739 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 6592 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 469184 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 728 # Transaction distribution +system.membus.trans_dist::ReadExResp 728 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 83880 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 169218 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5414912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 5414912 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7332 # Request fanout histogram +system.membus.snoop_fanout::samples 84609 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7332 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 84609 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7332 # Request fanout histogram -system.membus.reqLayer0.occupancy 9416916 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 38389399 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_fanout::total 84609 # Request fanout histogram +system.membus.reqLayer0.occupancy 103435410 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 446650667 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index e29d83073..863619ff4 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517243 # Number of seconds simulated -sim_ticks 517243165500 # Number of ticks simulated -final_tick 517243165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517291 # Number of seconds simulated +sim_ticks 517291025500 # Number of ticks simulated +final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 702843 # Simulator instruction rate (inst/s) -host_op_rate 843789 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1332923086 # Simulator tick rate (ticks/s) -host_mem_usage 322968 # Number of bytes of host memory used -host_seconds 388.05 # Real time elapsed on the host +host_inst_rate 635145 # Simulator instruction rate (inst/s) +host_op_rate 762516 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1204648551 # Simulator tick rate (ticks/s) +host_mem_usage 323584 # Number of bytes of host memory used +host_seconds 429.41 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 166912 # Nu system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034486331 # number of cpu cycles simulated +system.cpu.numCycles 1034582051 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739286 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034486330.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563503 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812214 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.444355 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.444355 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id @@ -249,14 +249,14 @@ system.cpu.dcache.demand_misses::cpu.data 4476 # n system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 78469000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 78469000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157423500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157423500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235892500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235892500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235892500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235892500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48920.822943 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48920.822943 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.196379 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.196379 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52701.630920 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52701.630920 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52666.331770 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52666.331770 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76826000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 154551500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 154551500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 162000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 162000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 231377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 231377500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 231539500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 231539500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,26 +335,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47926.388022 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47926.388022 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53813.196379 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53813.196379 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51704.469274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51704.469274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51706.007146 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51706.007146 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007280 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007280 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 320168000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 320168000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 320168000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 320168000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 320168000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 320168000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20519.643658 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20519.643658 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20519.643658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20519.643658 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20519.643658 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,44 +408,46 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13796 # number of writebacks +system.cpu.icache.writebacks::total 13796 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 304565000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 304565000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 304565000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 304565000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 304565000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 304565000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19519.643658 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19519.643658 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19519.643658 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19519.643658 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764139 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.622938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.426609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.714591 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073469 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.022544 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.106434 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id @@ -455,8 +457,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits @@ -481,20 +485,22 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150075000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 150075000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137027500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137027500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 72007000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 72007000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137027500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 222082000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359109500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137027500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 222082000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359109500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) @@ -519,18 +525,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.268908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.268908 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52541.219325 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52541.219325 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52636.695906 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52636.695906 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52562.865925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.219325 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.231061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52562.865925 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,18 +557,18 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 121515000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 121515000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 110947500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 110947500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 58327000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 58327000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110947500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 179842000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 290789500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110947500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 179842000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 290789500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses @@ -575,18 +581,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42547.268908 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42547.268908 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42541.219325 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42541.219325 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42636.695906 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42636.695906 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42541.219325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42576.231061 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42562.865925 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -595,8 +601,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6465 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution @@ -604,22 +611,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 35209 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.438041 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.496153 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 19786 56.20% 56.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15423 43.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35209 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 18602500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -644,9 +651,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7261500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34588500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index dc4595f22..1ecb81d4d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.560940 # Number of seconds simulated -sim_ticks 560939659000 # Number of ticks simulated -final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.560955 # Number of seconds simulated +sim_ticks 560955232000 # Number of ticks simulated +final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 314051 # Simulator instruction rate (inst/s) -host_op_rate 314051 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189670339 # Simulator tick rate (ticks/s) -host_mem_usage 308244 # Number of bytes of host memory used -host_seconds 2957.45 # Real time elapsed on the host +host_inst_rate 340981 # Simulator instruction rate (inst/s) +host_op_rate 340981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205940379 # Simulator tick rate (ticks/s) +host_mem_usage 308844 # Number of bytes of host memory used +host_seconds 2723.87 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18514112 # Number of bytes read from this memory -system.physmem.bytes_read::total 18700928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 184896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18519872 # Number of bytes read from this memory +system.physmem.bytes_read::total 18704768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 184896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 184896 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289283 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292202 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289373 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292262 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33005532 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33338573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7608148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7608148 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7608148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33005532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40946722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292202 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 329609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33014884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33344493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 329609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 329609 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7607937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7607937 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7607937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 329609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33014884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40952430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292262 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292262 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18682112 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18700928 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18684608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18704768 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18035 # Per bank write bursts -system.physmem.perBankRdBursts::1 18362 # Per bank write bursts -system.physmem.perBankRdBursts::2 18392 # Per bank write bursts -system.physmem.perBankRdBursts::3 18337 # Per bank write bursts -system.physmem.perBankRdBursts::4 18250 # Per bank write bursts -system.physmem.perBankRdBursts::5 18249 # Per bank write bursts -system.physmem.perBankRdBursts::6 18316 # Per bank write bursts -system.physmem.perBankRdBursts::7 18295 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18228 # Per bank write bursts -system.physmem.perBankRdBursts::10 18207 # Per bank write bursts -system.physmem.perBankRdBursts::11 18382 # Per bank write bursts -system.physmem.perBankRdBursts::12 18252 # Per bank write bursts -system.physmem.perBankRdBursts::13 18131 # Per bank write bursts -system.physmem.perBankRdBursts::14 18059 # Per bank write bursts -system.physmem.perBankRdBursts::15 18183 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18033 # Per bank write bursts +system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18332 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18255 # Per bank write bursts +system.physmem.perBankRdBursts::6 18314 # Per bank write bursts +system.physmem.perBankRdBursts::7 18296 # Per bank write bursts +system.physmem.perBankRdBursts::8 18227 # Per bank write bursts +system.physmem.perBankRdBursts::9 18236 # Per bank write bursts +system.physmem.perBankRdBursts::10 18229 # Per bank write bursts +system.physmem.perBankRdBursts::11 18376 # Per bank write bursts +system.physmem.perBankRdBursts::12 18263 # Per bank write bursts +system.physmem.perBankRdBursts::13 18132 # Per bank write bursts +system.physmem.perBankRdBursts::14 18061 # Per bank write bursts +system.physmem.perBankRdBursts::15 18191 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4186 # Per bank write bursts +system.physmem.perBankWrBursts::9 4192 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560939577000 # Total gap between requests +system.physmem.totGap 560955208000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292202 # Read request sizes (log2) +system.physmem.readPktSize::6 292262 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4051 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,43 +193,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 220.607081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.832345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.107277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 38319 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43999 42.30% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8903 8.56% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 723 0.70% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.533003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.789866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.043159 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38344 36.85% 36.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 44004 42.28% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8921 8.57% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 721 0.69% 88.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1141 1.10% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 666 0.64% 91.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 599 0.58% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8297 7.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104019 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.696468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.574169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 760.359503 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 3 0.07% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 1145 1.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 668 0.64% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 598 0.57% 92.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8294 7.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104067 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.768889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.564435 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 763.185509 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463818 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.443063 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.844207 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3110 76.81% 76.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 939 23.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2923147000 # Total ticks spent queuing -system.physmem.totMemAccLat 8396422000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10013.93 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4050 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.461235 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.440549 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.842853 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3116 76.94% 76.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 76.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 932 23.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4050 # Writes before turning the bus around for reads +system.physmem.totQLat 2934449500 # Total ticks spent queuing +system.physmem.totMemAccLat 8408455750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459735000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10051.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28763.93 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28801.31 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s @@ -239,71 +243,71 @@ system.physmem.busUtil 0.32 # Da system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.30 # Average write queue length when enqueuing -system.physmem.readRowHits 202517 # Number of row buffer hits during reads -system.physmem.writeRowHits 52027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.02 # Row buffer hit rate for writes -system.physmem.avgGap 1563006.47 # Average gap between requests +system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing +system.physmem.readRowHits 202530 # Number of row buffer hits during reads +system.physmem.writeRowHits 52011 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes +system.physmem.avgGap 1562788.75 # Average gap between requests system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 392311080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 214058625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140422400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140391200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109190821365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240780947250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388572678720 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.720364 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 399879041250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states +system.physmem_0.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109486358955 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240531047250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388619465820 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.784540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399461576500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18731440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142327335000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142759852250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 394019640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 214990875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215531280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109681250220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240350746500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388630405035 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.823275 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399158044000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states +system.physmem_1.actEnergy 394276680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 215131125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136522400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36638696640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109506441195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240513431250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388620069450 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.785616 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399429681750 # Time in different power states +system.physmem_1.memoryStateTime::REF 18731440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 143048821000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142792236250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125747730 # Number of BP lookups -system.cpu.branchPred.condPredicted 81143399 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12156451 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103980487 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83512673 # Number of BTB hits +system.cpu.branchPred.lookups 125747709 # Number of BP lookups +system.cpu.branchPred.condPredicted 81143389 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12156447 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103980471 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83512685 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.315716 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691015 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.315740 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691016 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537770 # DTB read hits +system.cpu.dtb.read_hits 237537764 # DTB read hits system.cpu.dtb.read_misses 198464 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736234 # DTB read accesses -system.cpu.dtb.write_hits 98304947 # DTB write hits +system.cpu.dtb.read_accesses 237736228 # DTB read accesses +system.cpu.dtb.write_hits 98304946 # DTB write hits system.cpu.dtb.write_misses 7177 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312124 # DTB write accesses -system.cpu.dtb.data_hits 335842717 # DTB hits +system.cpu.dtb.write_accesses 98312123 # DTB write accesses +system.cpu.dtb.data_hits 335842710 # DTB hits system.cpu.dtb.data_misses 205641 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048358 # DTB accesses -system.cpu.itb.fetch_hits 316984864 # ITB hits +system.cpu.dtb.data_accesses 336048351 # DTB accesses +system.cpu.itb.fetch_hits 316984906 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316984984 # ITB accesses +system.cpu.itb.fetch_accesses 316985026 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,24 +321,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1121879318 # number of cpu cycles simulated +system.cpu.numCycles 1121910464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30861365 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30861351 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.207895 # CPI: cycles per instruction -system.cpu.ipc 0.827887 # IPC: instructions per cycle -system.cpu.tickCycles 1059707231 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62172087 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.207928 # CPI: cycles per instruction +system.cpu.ipc 0.827864 # IPC: instructions per cycle +system.cpu.tickCycles 1059707465 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62202999 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776530 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.727909 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322866545 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.728000 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322866540 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599528 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.599521 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.727909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.728000 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -344,40 +348,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648211884 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648211884 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224702500 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224702500 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164045 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164045 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322866545 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322866545 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322866545 # number of overall hits -system.cpu.dcache.overall_hits::total 322866545 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648211872 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648211872 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224702494 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224702494 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164046 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164046 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322866540 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322866540 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322866540 # number of overall hits +system.cpu.dcache.overall_hits::total 322866540 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137155 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137155 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849084 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849084 # number of overall misses -system.cpu.dcache.overall_misses::total 849084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888766500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24888766500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9955853000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9955853000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34844619500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34844619500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34844619500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34844619500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225414429 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225414429 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849083 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849083 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849083 # number of overall misses +system.cpu.dcache.overall_misses::total 849083 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24904735500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24904735500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9954481000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9954481000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34859216500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34859216500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34859216500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34859216500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225414423 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225414423 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323715629 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323715629 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323715629 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323715629 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323715623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323715623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323715623 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323715623 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -386,14 +390,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.618866 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.618866 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72588.334366 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72588.334366 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41037.894366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41037.894366 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41055.134186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41055.134186 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,16 +406,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88852 # number of writebacks -system.cpu.dcache.writebacks::total 88852 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88497 # number of writebacks +system.cpu.dcache.writebacks::total 88497 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68144 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68144 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68458 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68458 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68458 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68458 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68143 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68143 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68457 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68457 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68457 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68457 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -420,14 +424,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780626 system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170053000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170053000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993475000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993475000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29163528000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29163528000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29163528000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29163528000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24185998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24185998000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4992658500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4992658500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29178656500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29178656500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29178656500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29178656500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -436,69 +440,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33965.069595 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33965.069595 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72357.667618 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72357.667618 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37359.155345 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37359.155345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37359.155345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37359.155345 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10565 # number of replacements -system.cpu.icache.tags.tagsinuse 1685.376392 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316972557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12306 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25757.561921 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10567 # number of replacements +system.cpu.icache.tags.tagsinuse 1685.376446 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316972597 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12308 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25753.379672 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376392 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376446 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1571 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633982034 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633982034 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316972557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316972557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316972557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316972557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316972557 # number of overall hits -system.cpu.icache.overall_hits::total 316972557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12307 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12307 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12307 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12307 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12307 # number of overall misses -system.cpu.icache.overall_misses::total 12307 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 350414000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 350414000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 350414000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 350414000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 350414000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 350414000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316984864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316984864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316984864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316984864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316984864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316984864 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 633982120 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633982120 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316972597 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316972597 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316972597 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316972597 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316972597 # number of overall hits +system.cpu.icache.overall_hits::total 316972597 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12309 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12309 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12309 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12309 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12309 # number of overall misses +system.cpu.icache.overall_misses::total 12309 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 349738000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 349738000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 349738000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 349738000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 349738000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 349738000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 316984906 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 316984906 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 316984906 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 316984906 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 316984906 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 316984906 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28472.739092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28472.739092 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28472.739092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28472.739092 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28413.193598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28413.193598 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,129 +511,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12307 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12307 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12307 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12307 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338108000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 338108000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338108000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 338108000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338108000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 338108000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 10567 # number of writebacks +system.cpu.icache.writebacks::total 10567 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12309 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12309 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12309 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12309 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12309 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12309 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 337430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 337430000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 337430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 337430000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 337430000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 337430000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27472.820346 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27472.820346 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259423 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.990901 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218275 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292159 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.169904 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259935 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32594.451091 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218218 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292671 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.162414 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002372 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912968 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994704 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 277 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2659 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29473 # 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mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312863 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368509 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368509 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63000.045015 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63000.045015 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65717.636986 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65717.636986 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70706.606689 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70706.606689 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.234788 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312989 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312989 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368584 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.234788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370694 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368584 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1580028 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1580032 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2077 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2079 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2079 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155180 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881285 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12309 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35184 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2372960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 787584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259423 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001129 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.033584 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 2372966 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57087872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259935 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1052870 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001975 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1837374 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2077 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1050791 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2079 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1052870 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 889080000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18462000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170939000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225557 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191114 # Transaction distribution +system.membus.trans_dist::ReadResp 225617 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191173 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225557 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842201 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842201 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22968640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225617 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842380 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22972480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549999 # Request fanout histogram +system.membus.snoop_fanout::samples 550118 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550118 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549999 # Request fanout histogram -system.membus.reqLayer0.occupancy 918564500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550118 # Request fanout histogram +system.membus.reqLayer0.occupancy 918693000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556125250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556459000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 4dbf3fd00..ba9bff2cb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.276406 # Number of seconds simulated -sim_ticks 276406029500 # Number of ticks simulated -final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.276414 # Number of seconds simulated +sim_ticks 276414065500 # Number of ticks simulated +final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172081 # Simulator instruction rate (inst/s) -host_op_rate 172081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56464121 # Simulator tick rate (ticks/s) -host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 4895.25 # Real time elapsed on the host +host_inst_rate 180346 # Simulator instruction rate (inst/s) +host_op_rate 180346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59177560 # Simulator tick rate (ticks/s) +host_mem_usage 308352 # Number of bytes of host memory used +host_seconds 4670.93 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18519360 # Number of bytes read from this memory -system.physmem.bytes_read::total 18693312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 172736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18523584 # Number of bytes read from this memory +system.physmem.bytes_read::total 18696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 172736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 172736 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289365 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289431 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292130 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 629335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 67000564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67629900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 629335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 629335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15440011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15440011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15440011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 629335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 67000564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 83069910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292083 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 624918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 67013898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67638816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 624918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 624918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15439562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15439562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15439562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 624918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 67013898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 83078377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292130 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292083 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292130 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18672064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18693312 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18675136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18696320 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18010 # Per bank write bursts -system.physmem.perBankRdBursts::1 18319 # Per bank write bursts -system.physmem.perBankRdBursts::2 18376 # Per bank write bursts -system.physmem.perBankRdBursts::3 18330 # Per bank write bursts -system.physmem.perBankRdBursts::4 18231 # Per bank write bursts -system.physmem.perBankRdBursts::5 18221 # Per bank write bursts -system.physmem.perBankRdBursts::6 18322 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18218 # Per bank write bursts -system.physmem.perBankRdBursts::10 18207 # Per bank write bursts -system.physmem.perBankRdBursts::11 18389 # Per bank write bursts -system.physmem.perBankRdBursts::12 18249 # Per bank write bursts -system.physmem.perBankRdBursts::13 18121 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191079 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18006 # Per bank write bursts +system.physmem.perBankRdBursts::1 18321 # Per bank write bursts +system.physmem.perBankRdBursts::2 18379 # Per bank write bursts +system.physmem.perBankRdBursts::3 18333 # Per bank write bursts +system.physmem.perBankRdBursts::4 18240 # Per bank write bursts +system.physmem.perBankRdBursts::5 18219 # Per bank write bursts +system.physmem.perBankRdBursts::6 18314 # Per bank write bursts +system.physmem.perBankRdBursts::7 18303 # Per bank write bursts +system.physmem.perBankRdBursts::8 18232 # Per bank write bursts +system.physmem.perBankRdBursts::9 18223 # Per bank write bursts +system.physmem.perBankRdBursts::10 18219 # Per bank write bursts +system.physmem.perBankRdBursts::11 18380 # Per bank write bursts +system.physmem.perBankRdBursts::12 18258 # Per bank write bursts +system.physmem.perBankRdBursts::13 18122 # Per bank write bursts system.physmem.perBankRdBursts::14 18052 # Per bank write bursts -system.physmem.perBankRdBursts::15 18183 # Per bank write bursts +system.physmem.perBankRdBursts::15 18198 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts +system.physmem.perBankWrBursts::9 4187 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276405940000 # Total gap between requests +system.physmem.totGap 276414034500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292083 # Read request sizes (log2) +system.physmem.readPktSize::6 292130 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 216501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215201 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,121 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.668262 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.414135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 279.665008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34391 34.59% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42842 43.08% 77.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10220 10.28% 87.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 417 0.42% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 400 0.40% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 621 0.62% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 466 0.47% 89.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1450 1.46% 91.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8630 8.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99437 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.663212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.607328 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 761.755251 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4044 99.78% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 99419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.737062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.797862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.058381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34339 34.54% 34.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42571 42.82% 77.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9880 9.94% 87.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 767 0.77% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1066 1.07% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 606 0.61% 89.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 182 0.18% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1419 1.43% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8589 8.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99419 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.841638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.476950 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 763.295063 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.449050 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.428679 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.836709 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3145 77.60% 77.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 905 22.33% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3647206250 # Total ticks spent queuing -system.physmem.totMemAccLat 9117537500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1458755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12501.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.443759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.423618 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.831866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3155 77.82% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 77.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 896 22.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads +system.physmem.totQLat 3656274250 # Total ticks spent queuing +system.physmem.totMemAccLat 9127505500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1458995000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12530.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31251.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.63 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31280.11 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 67.56 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.43 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 15.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.65 # Data bus utilization in percentage system.physmem.busUtilRead 0.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing -system.physmem.readRowHits 206989 # Number of row buffer hits during reads -system.physmem.writeRowHits 51984 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 207034 # Number of row buffer hits during reads +system.physmem.writeRowHits 52000 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes -system.physmem.avgGap 770435.16 # Average gap between requests -system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 373947840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204039000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139408400 # Energy for read commands per rank (pJ) +system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes +system.physmem.avgGap 770356.80 # Average gap between requests +system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139463000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80174383695 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95514202500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 195675791355 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.933114 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158383013500 # Time in different power states -system.physmem_0.memoryStateTime::REF 9229740000 # Time in different power states +system.physmem_0.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80208829935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95488658250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 195685642110 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.948810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158328598000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9230000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108791696000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108853550750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 377742960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 206109750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1135890600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80329865445 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 95377815000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 195696365355 # Total energy per rank (pJ) -system.physmem_1.averagePower 708.007549 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 158148138750 # Time in different power states -system.physmem_1.memoryStateTime::REF 9229740000 # Time in different power states +system.physmem_1.actEnergy 377342280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 205891125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80561309670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 95179465500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 195729613335 # Total energy per rank (pJ) +system.physmem_1.averagePower 708.107889 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 157816922000 # Time in different power states +system.physmem_1.memoryStateTime::REF 9230000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109026483750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109365226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192576076 # Number of BP lookups -system.cpu.branchPred.condPredicted 126054565 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11561227 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 137875170 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126274438 # Number of BTB hits +system.cpu.branchPred.lookups 192576024 # Number of BP lookups +system.cpu.branchPred.condPredicted 126054494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11561226 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 137875105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126274367 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.586062 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28678363 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 136 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.586053 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28678385 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 133 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 242441387 # DTB read hits -system.cpu.dtb.read_misses 312131 # DTB read misses +system.cpu.dtb.read_hits 242441427 # DTB read hits +system.cpu.dtb.read_misses 312020 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 242753518 # DTB read accesses -system.cpu.dtb.write_hits 135445935 # DTB write hits +system.cpu.dtb.read_accesses 242753447 # DTB read accesses +system.cpu.dtb.write_hits 135445847 # DTB write hits system.cpu.dtb.write_misses 31631 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135477566 # DTB write accesses -system.cpu.dtb.data_hits 377887322 # DTB hits -system.cpu.dtb.data_misses 343762 # DTB misses +system.cpu.dtb.write_accesses 135477478 # DTB write accesses +system.cpu.dtb.data_hits 377887274 # DTB hits +system.cpu.dtb.data_misses 343651 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 378231084 # DTB accesses -system.cpu.itb.fetch_hits 194828154 # ITB hits -system.cpu.itb.fetch_misses 242 # ITB misses +system.cpu.dtb.data_accesses 378230925 # DTB accesses +system.cpu.itb.fetch_hits 194827904 # ITB hits +system.cpu.itb.fetch_misses 239 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 194828396 # ITB accesses +system.cpu.itb.fetch_accesses 194828143 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,98 +320,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 552812060 # number of cpu cycles simulated +system.cpu.numCycles 552828132 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 198850471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1637321626 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192576076 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 154952801 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341917067 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 23591046 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 198849781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1637321417 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192576024 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 154952752 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341932468 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 23591048 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6993 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 6961 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 194828154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7885913 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 552570202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 194827904 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7885927 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 552584882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963022 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236054473 42.72% 42.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29638362 5.36% 48.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21702458 3.93% 52.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35773228 6.47% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67707960 12.25% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21595876 3.91% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19328628 3.50% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3978060 0.72% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 116791157 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236070631 42.72% 42.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29638226 5.36% 48.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21699661 3.93% 52.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 35773155 6.47% 58.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67709217 12.25% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21596173 3.91% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19328814 3.50% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3978253 0.72% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 116790752 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 552570202 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348357 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.961805 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166802287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90542864 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 271199395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12236841 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11788815 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15468328 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 552584882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348347 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.961719 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166809048 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 90546856 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 271205722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12234440 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11788816 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15468258 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 6932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1567838176 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24969 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11788815 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 173688859 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 60716441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13717 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276533617 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29828753 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1529250735 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8190 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2401406 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20516503 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7198838 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1021411513 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1760089033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1720202399 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39886633 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 1567837184 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 24953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11788816 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 173694356 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 60697364 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276538556 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29852032 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1529249378 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8057 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2407484 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20532473 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7206116 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1021410389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1760087391 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1720201095 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39886295 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 382444355 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1364 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9081858 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 369185264 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 173801333 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40211283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11128775 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1296786218 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 72 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1011356527 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8787388 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454404260 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 422537101 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 552570202 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.830277 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913640 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 382443231 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9068503 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 369184759 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 173801249 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40216404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11112363 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1296784829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1011355981 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8787623 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 454402873 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 422535596 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 552584882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.830227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.913668 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197270443 35.70% 35.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90785192 16.43% 52.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 90547416 16.39% 68.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58763251 10.63% 79.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 57064914 10.33% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29634790 5.36% 94.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 16885134 3.06% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7510156 1.36% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4108906 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197292642 35.70% 35.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90775823 16.43% 52.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 90545836 16.39% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 58767814 10.64% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57065281 10.33% 89.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29635375 5.36% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 16880319 3.05% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7509205 1.36% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4112587 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 552570202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 552584882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2519726 10.56% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2519786 10.56% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available @@ -441,16 +440,16 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15983640 67.00% 77.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5352814 22.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15987276 67.00% 77.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5353537 22.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 577739239 57.13% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 577738940 57.13% 57.13% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7929 0.00% 57.13% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13232477 1.31% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13232476 1.31% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 3339799 0.33% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued @@ -475,84 +474,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 274563645 27.15% 86.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138645616 13.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 274563490 27.15% 86.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138645524 13.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1011356527 # Type of FU issued -system.cpu.iq.rate 1.829476 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23856180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023588 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2536915249 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1709850818 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 936642710 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 71011575 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41384719 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34526976 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 998747828 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36463603 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 49725855 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1011355981 # Type of FU issued +system.cpu.iq.rate 1.829422 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23860599 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023593 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2536933524 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1709848613 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 936642568 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 71011542 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41384153 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34526963 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 998751721 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36463583 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 49725864 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 131674667 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1209013 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 75500133 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 131674162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1208593 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45366 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 75500049 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2715 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4018 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 4217 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11788815 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59738270 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 197040 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1470367053 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17961 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 369185264 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 173801333 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 72 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15881 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 192528 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11555967 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 14465 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11570432 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 973002630 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 242753693 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 38353897 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11788816 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59730385 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 188341 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1470365584 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17995 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 369184759 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 173801249 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15707 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 184002 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45366 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11555966 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 14467 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11570433 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 973002254 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 242753622 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 38353727 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 173580763 # number of nop insts executed -system.cpu.iew.exec_refs 378231547 # number of memory reference insts executed -system.cpu.iew.exec_branches 128483828 # Number of branches executed -system.cpu.iew.exec_stores 135477854 # Number of stores executed -system.cpu.iew.exec_rate 1.760097 # Inst execution rate -system.cpu.iew.wb_sent 971735885 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 971169686 # cumulative count of insts written-back -system.cpu.iew.wb_producers 554962956 # num instructions producing a value -system.cpu.iew.wb_consumers 830927766 # num instructions consuming a value +system.cpu.iew.exec_nop 173580681 # number of nop insts executed +system.cpu.iew.exec_refs 378231388 # number of memory reference insts executed +system.cpu.iew.exec_branches 128483769 # Number of branches executed +system.cpu.iew.exec_stores 135477766 # Number of stores executed +system.cpu.iew.exec_rate 1.760045 # Inst execution rate +system.cpu.iew.wb_sent 971735602 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 971169531 # cumulative count of insts written-back +system.cpu.iew.wb_producers 554965093 # num instructions producing a value +system.cpu.iew.wb_consumers 830941176 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.756781 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667884 # average fanout of values written-back +system.cpu.iew.wb_rate 1.756730 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667875 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 534548617 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 534547076 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11554520 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 481206030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.929709 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.612045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11554519 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 481220935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.929649 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.612057 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 204042568 42.40% 42.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 101511322 21.10% 63.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52351761 10.88% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25424969 5.28% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20905527 4.34% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8991227 1.87% 85.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10032438 2.08% 87.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6244738 1.30% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 51701480 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 204061483 42.40% 42.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 101508829 21.09% 63.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52351815 10.88% 74.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25424424 5.28% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20903892 4.34% 84.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8988981 1.87% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10032197 2.08% 87.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6246270 1.30% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 51703044 10.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 481206030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 481220935 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -598,137 +597,137 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 51701480 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1890019657 # The number of ROB reads -system.cpu.rob.rob_writes 2997637733 # The number of ROB writes -system.cpu.timesIdled 3185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 241858 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 51703044 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1890031457 # The number of ROB reads +system.cpu.rob.rob_writes 2997634424 # The number of ROB writes +system.cpu.timesIdled 3187 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 243250 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.656249 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656249 # CPI: Total CPI of All Threads -system.cpu.ipc 1.523813 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.523813 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234257247 # number of integer regfile reads -system.cpu.int_regfile_writes 703449538 # number of integer regfile writes -system.cpu.fp_regfile_reads 36844878 # number of floating regfile reads -system.cpu.fp_regfile_writes 24462480 # number of floating regfile writes +system.cpu.cpi 0.656268 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.656268 # CPI: Total CPI of All Threads +system.cpu.ipc 1.523768 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.523768 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234256884 # number of integer regfile reads +system.cpu.int_regfile_writes 703449505 # number of integer regfile writes +system.cpu.fp_regfile_reads 36844868 # number of floating regfile reads +system.cpu.fp_regfile_writes 24462479 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777154 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.899235 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288564425 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781250 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 369.362464 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 369553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.899235 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999243 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999243 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777152 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.896824 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288563683 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781248 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 369.362460 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 369982500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.896824 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 582801760 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 582801760 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 191156368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 191156368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408043 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408043 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 582801420 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 582801420 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 191154367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 191154367 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97409302 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97409302 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 288564411 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 288564411 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 288564411 # number of overall hits -system.cpu.dcache.overall_hits::total 288564411 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1552672 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1552672 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 893157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 893157 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 288563669 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 288563669 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 288563669 # number of overall hits +system.cpu.dcache.overall_hits::total 288563669 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554504 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554504 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 891898 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 891898 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2445829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2445829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2445829 # number of overall misses -system.cpu.dcache.overall_misses::total 2445829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83271101000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83271101000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62352545333 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62352545333 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2446402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2446402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2446402 # number of overall misses +system.cpu.dcache.overall_misses::total 2446402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83607056000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83607056000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61973215333 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61973215333 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 82500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623646333 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623646333 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623646333 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623646333 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 192709040 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 192709040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 145580271333 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145580271333 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145580271333 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145580271333 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 192708871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 192708871 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291010240 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291010240 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 291010240 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 291010240 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008057 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008057 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009086 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 291010071 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 291010071 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 291010071 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 291010071 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009073 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009073 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.066667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.008407 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008407 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008407 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008407 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 82500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 82500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59539.586101 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59539.586101 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22515 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 72899 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59507.910529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59507.910529 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 23437 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 62248 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 339 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.026393 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 141.003868 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.135693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 120.402321 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88880 # number of writebacks -system.cpu.dcache.writebacks::total 88880 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840227 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840227 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824352 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824352 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 88616 # number of writebacks +system.cpu.dcache.writebacks::total 88616 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842060 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842060 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823094 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 823094 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1664579 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1664579 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1664579 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1664579 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712445 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712445 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68805 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68805 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781250 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781250 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781250 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781250 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24193547500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24193547500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5688085497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5688085497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29881632997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29881632997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29881632997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29881632997 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1665154 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1665154 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1665154 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1665154 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712444 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712444 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68804 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68804 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781248 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781248 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781248 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781248 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24228621500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24228621500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5666649497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5666649497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29895270997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29895270997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29895270997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29895270997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003697 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003697 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses @@ -737,69 +736,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002685 system.cpu.dcache.demand_mshr_miss_rate::total 0.002685 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4598 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.391736 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 194819915 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6300 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30923.796032 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4602 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.296070 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 194819661 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6304 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30904.134042 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.391736 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801461 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801461 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.296070 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801414 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801414 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1702 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1535 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.831055 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 389662608 # Number of tag accesses -system.cpu.icache.tags.data_accesses 389662608 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 194819915 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 194819915 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 194819915 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 194819915 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 194819915 # number of overall hits -system.cpu.icache.overall_hits::total 194819915 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8239 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8239 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8239 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8239 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8239 # number of overall misses -system.cpu.icache.overall_misses::total 8239 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351244499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351244499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351244499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351244499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351244499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351244499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 194828154 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 194828154 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 194828154 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 194828154 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 194828154 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 194828154 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 389662112 # Number of tag accesses +system.cpu.icache.tags.data_accesses 389662112 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 194819661 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 194819661 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 194819661 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 194819661 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 194819661 # number of overall hits +system.cpu.icache.overall_hits::total 194819661 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8243 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8243 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8243 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8243 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8243 # number of overall misses +system.cpu.icache.overall_misses::total 8243 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 351192999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351192999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 351192999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351192999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 351192999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351192999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 194827904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 194827904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 194827904 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 194827904 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 194827904 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 194827904 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42631.933366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42631.933366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42604.998059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42604.998059 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 510 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -808,135 +807,141 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 46.363636 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 4602 # number of writebacks +system.cpu.icache.writebacks::total 4602 # number of writebacks system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1938 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 1938 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits::cpu.inst 1938 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 1938 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 1938 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 1938 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6301 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6301 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6301 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261165999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 261165999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261165999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 261165999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261165999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 261165999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6305 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6305 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6305 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6305 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6305 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6305 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261344999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 261344999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261344999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 261344999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261344999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 261344999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41448.341374 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41448.341374 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41450.436003 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259305 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32630.134515 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207948 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292043 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.136199 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259749 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32631.179257 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207901 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292487 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.129760 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2512.609153 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 65.430826 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001997 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.917117 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995793 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2522.721637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 62.286398 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30046.171221 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001901 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.916936 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995825 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 159 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370387 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.431519 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370387 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73475.963198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428232 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312733 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312733 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370935 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370935 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1569303 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1569307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781754 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1986 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1986 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1989 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1989 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68805 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712445 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339654 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2356853 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 403200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55688320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259305 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001086 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032938 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712444 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17211 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339648 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2356859 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 697984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55671296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56369280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259749 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1047302 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001899 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1826622 99.89% 99.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1986 0.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1045313 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1989 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1047302 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877871500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9450000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9456000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171875499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171872499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225456 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191030 # Transaction distribution -system.membus.trans_dist::ReadExReq 66627 # Transaction distribution -system.membus.trans_dist::ReadExResp 66627 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225456 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 841879 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 841879 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22961024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22961024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 225504 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191079 # Transaction distribution +system.membus.trans_dist::ReadExReq 66626 # Transaction distribution +system.membus.trans_dist::ReadExResp 66626 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225504 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842022 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22964032 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549796 # Request fanout histogram +system.membus.snoop_fanout::samples 549892 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549796 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549892 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549796 # Request fanout histogram -system.membus.reqLayer0.occupancy 880960000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549892 # Request fanout histogram +system.membus.reqLayer0.occupancy 880924000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551840500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551641250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f1fff22ed..5e6b1a1be 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.286279 # Number of seconds simulated -sim_ticks 1286278511500 # Number of ticks simulated -final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.288319 # Number of seconds simulated +sim_ticks 1288319411500 # Number of ticks simulated +final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1389844 # Simulator instruction rate (inst/s) -host_op_rate 1389844 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1925210162 # Simulator tick rate (ticks/s) -host_mem_usage 305148 # Number of bytes of host memory used -host_seconds 668.12 # Real time elapsed on the host +host_inst_rate 1465054 # Simulator instruction rate (inst/s) +host_op_rate 1465054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032611527 # Simulator tick rate (ticks/s) +host_mem_usage 306300 # Number of bytes of host memory used +host_seconds 633.82 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18509184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18646976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory +system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289206 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14389717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14496842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107125 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3317876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3317876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3317876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14389717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17814717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572557023 # number of cpu cycles simulated +system.cpu.numCycles 2576638823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572557023 # Number of busy cycles +system.cpu.num_busy_cycles 2576638823 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261358 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046537500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261358 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18597166000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18597166000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696410000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696410000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22293576000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22293576000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22293576000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22293576000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28562.173298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28562.173298 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 89031 # number of writebacks -system.cpu.dcache.writebacks::total 89031 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks +system.cpu.dcache.writebacks::total 88866 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17885652000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17885652000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3627396000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3627396000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21513048000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21513048000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21513048000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21513048000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -228,24 +228,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486224 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486224 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id @@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170684500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170684500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170684500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170684500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170684500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170684500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27672.584306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27672.584306 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,93 +298,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 4618 # number of writebacks +system.cpu.icache.writebacks::total 4618 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164516500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 164516500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164516500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 164516500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164516500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 164516500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258580 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.927159 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207050 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291314 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.143467 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258847 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2486.879631 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.811890 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.075894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001520 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.919227 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996641 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902296 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902296 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 89031 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 89031 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4015 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4015 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488956 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488956 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491322 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495337 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491322 # number of overall hits -system.cpu.l2cache.overall_hits::total 495337 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits +system.cpu.l2cache.overall_hits::total 495307 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2153 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2153 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222558 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222558 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289206 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289206 # number of overall misses -system.cpu.l2cache.overall_misses::total 291359 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499032000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3499032000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113105000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 113105000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11684343000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11684343000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 113105000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15183375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15296480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 113105000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15183375000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15296480000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 89031 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 89031 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses +system.cpu.l2cache.overall_misses::total 291389 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) @@ -399,28 +405,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 780528 system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.349060 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312795 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312795 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370526 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370526 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,58 +437,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 238 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 238 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2153 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2153 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222558 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222558 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289206 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291359 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289206 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291359 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2832552000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2832552000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91575000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91575000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9458763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9458763000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91575000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12291315000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12382890000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91575000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12291315000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12382890000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.349060 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312795 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312795 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -491,8 +497,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution @@ -500,51 +507,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55651776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258580 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000941 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030656 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258847 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1824608 99.91% 99.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224711 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190417 # Transaction distribution +system.membus.trans_dist::ReadResp 224741 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 190447 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224711 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839818 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839818 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22914688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22914688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 548514 # Request fanout histogram +system.membus.snoop_fanout::samples 548519 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548514 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548514 # Request fanout histogram -system.membus.reqLayer0.occupancy 815261292 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548519 # Request fanout histogram +system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456808792 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index ca22b895a..c95abda26 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.542258 # Number of seconds simulated -sim_ticks 542257676500 # Number of ticks simulated -final_tick 542257676500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.542265 # Number of seconds simulated +sim_ticks 542265386500 # Number of ticks simulated +final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169610 # Simulator instruction rate (inst/s) -host_op_rate 208813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 143560034 # Simulator tick rate (ticks/s) -host_mem_usage 325880 # Number of bytes of host memory used -host_seconds 3777.22 # Real time elapsed on the host +host_inst_rate 179877 # Simulator instruction rate (inst/s) +host_op_rate 221452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152251725 # Simulator tick rate (ticks/s) +host_mem_usage 325476 # Number of bytes of host memory used +host_seconds 3561.64 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470592 # Number of bytes read from this memory -system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164608 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18474304 # Number of bytes read from this memory +system.physmem.bytes_read::total 18637888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2572 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288603 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288661 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291217 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34062389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34365950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7801221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7801221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7801221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34062389 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42167171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291175 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 301668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34068750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34370418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 301668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 301668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 301668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34068750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42171528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291217 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291217 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18614336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20864 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18637888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 326 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18135 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 18283 # Per bank write bursts +system.physmem.perBankRdBursts::1 18129 # Per bank write bursts system.physmem.perBankRdBursts::2 18220 # Per bank write bursts -system.physmem.perBankRdBursts::3 18173 # Per bank write bursts -system.physmem.perBankRdBursts::4 18273 # Per bank write bursts -system.physmem.perBankRdBursts::5 18400 # Per bank write bursts -system.physmem.perBankRdBursts::6 18176 # Per bank write bursts -system.physmem.perBankRdBursts::7 17989 # Per bank write bursts +system.physmem.perBankRdBursts::3 18184 # Per bank write bursts +system.physmem.perBankRdBursts::4 18283 # Per bank write bursts +system.physmem.perBankRdBursts::5 18405 # Per bank write bursts +system.physmem.perBankRdBursts::6 18181 # Per bank write bursts +system.physmem.perBankRdBursts::7 17993 # Per bank write bursts system.physmem.perBankRdBursts::8 18030 # Per bank write bursts -system.physmem.perBankRdBursts::9 18057 # Per bank write bursts -system.physmem.perBankRdBursts::10 18104 # Per bank write bursts -system.physmem.perBankRdBursts::11 18195 # Per bank write bursts -system.physmem.perBankRdBursts::12 18214 # Per bank write bursts -system.physmem.perBankRdBursts::13 18267 # Per bank write bursts +system.physmem.perBankRdBursts::9 18058 # Per bank write bursts +system.physmem.perBankRdBursts::10 18107 # Per bank write bursts +system.physmem.perBankRdBursts::11 18199 # Per bank write bursts +system.physmem.perBankRdBursts::12 18220 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18257 # Per bank write bursts +system.physmem.perBankRdBursts::15 18260 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4098 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::5 4222 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4092 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts -system.physmem.perBankWrBursts::11 4096 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542257582000 # Total gap between requests +system.physmem.totGap 542265360500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291175 # Read request sizes (log2) +system.physmem.readPktSize::6 291217 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 374 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,43 +193,42 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.748588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.953680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.656452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45849 41.30% 41.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43580 39.26% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9433 8.50% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1634 1.47% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 515 0.46% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111013 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.510331 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.246707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.588684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 111115 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.591972 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.871353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.553383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45879 41.29% 41.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43676 39.31% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9414 8.47% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1626 1.46% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 693 0.62% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 670 0.60% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 551 0.50% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8091 7.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111115 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.511200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.259636 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.474106 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.447598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.427351 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833980 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3118 77.62% 77.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 2868100000 # Total ticks spent queuing -system.physmem.totMemAccLat 8321518750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9861.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.444749 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.424614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.831636 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3124 77.75% 77.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 77.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 893 22.22% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads +system.physmem.totQLat 2873170250 # Total ticks spent queuing +system.physmem.totMemAccLat 8327545250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9876.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28611.13 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28626.83 # Average memory access latency per DRAM burst system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s @@ -239,49 +238,49 @@ system.physmem.busUtil 0.33 # Da system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing -system.physmem.readRowHits 194250 # Number of row buffer hits during reads -system.physmem.writeRowHits 51642 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.79 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing +system.physmem.readRowHits 194203 # Number of row buffer hits during reads +system.physmem.writeRowHits 51643 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1517768.15 # Average gap between requests -system.physmem.pageHitRate 68.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 419905080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229114875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135859400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 107383469355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231154143750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375955146300 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.324021 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 383844481500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states +system.physmem.avgGap 1517611.52 # Average gap between requests +system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136101200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215537760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 107646010785 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 230928516000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375994196925 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.386081 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383467912500 # Time in different power states +system.physmem_0.memoryStateTime::REF 18107180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 140298894750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140682990000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 419254920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228760125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132255800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107988829875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230623125750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 376021977270 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.447269 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382962347750 # Time in different power states -system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states +system.physmem_1.actEnergy 419141520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228698250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132419600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35417644080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 107856715275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230743687500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376010934465 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.416947 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 383162755000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18107180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141184235750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 140991278500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 154805770 # Number of BP lookups -system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted +system.cpu.branchPred.lookups 154805774 # Number of BP lookups +system.cpu.branchPred.condPredicted 105138294 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90693367 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 90693368 # Number of BTB lookups system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.615653 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 91.615652 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19277596 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -401,24 +400,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1084515353 # number of cpu cycles simulated +system.cpu.numCycles 1084530773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed system.cpu.discardedOps 23906784 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.692823 # CPI: cycles per instruction -system.cpu.ipc 0.590729 # IPC: instructions per cycle -system.cpu.tickCycles 1025899498 # Number of cycles that the object actually ticked -system.cpu.idleCycles 58615855 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.692847 # CPI: cycles per instruction +system.cpu.ipc 0.590721 # IPC: instructions per cycle +system.cpu.tickCycles 1025899528 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58631245 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 778339 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.484054 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.484104 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484104 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -454,14 +453,14 @@ system.cpu.dcache.demand_misses::cpu.data 851588 # n system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses system.cpu.dcache.overall_misses::total 851729 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762143500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24762143500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105570000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10105570000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34867713500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34867713500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34867713500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34867713500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24770851500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24770851500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105356000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105356000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34876207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34876207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34876207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34876207500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -486,14 +485,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34686.897304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34686.897304 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73381.912978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73381.912978 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40944.345740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40944.345740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40937.567583 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40937.567583 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40954.320047 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40947.540239 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,8 +501,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88920 # number of writebacks -system.cpu.dcache.writebacks::total 88920 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88693 # number of writebacks +system.cpu.dcache.writebacks::total 88693 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 902 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -522,16 +521,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782296 system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24033231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24033231500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067791500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067791500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29101023000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29101023000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29102878000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29102878000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24041947500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24041947500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067670500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067670500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29109618000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29109618000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29111406000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29111406000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -542,24 +541,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33708.426254 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33708.426254 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73105.096506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73105.096506 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13345.323741 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37199.503768 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37199.503768 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37195.266060 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37195.266060 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 23591 # number of replacements -system.cpu.icache.tags.tagsinuse 1713.095615 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 291576499 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1713.095631 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576507 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11505.662497 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662813 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095615 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095631 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id @@ -567,44 +566,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 58 system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 583229026 # Number of tag accesses -system.cpu.icache.tags.data_accesses 583229026 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 291576499 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 291576499 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 291576499 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 291576499 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 291576499 # number of overall hits -system.cpu.icache.overall_hits::total 291576499 # number of overall hits +system.cpu.icache.tags.tag_accesses 583229042 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583229042 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291576507 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291576507 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291576507 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291576507 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291576507 # number of overall hits +system.cpu.icache.overall_hits::total 291576507 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 25343 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 25343 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 25343 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 25343 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 25343 # number of overall misses system.cpu.icache.overall_misses::total 25343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499290500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499290500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499290500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499290500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499290500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499290500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 291601842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 291601842 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 291601842 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 291601842 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 291601842 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 291601842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 498728500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 498728500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 498728500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 498728500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 498728500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 498728500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291601850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291601850 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291601850 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291601850 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291601850 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291601850 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19701.317918 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19701.317918 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19701.317918 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19701.317918 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19701.317918 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19679.142169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19679.142169 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,93 +612,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 23591 # number of writebacks +system.cpu.icache.writebacks::total 23591 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25343 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 25343 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 25343 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 25343 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 25343 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 25343 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 473948500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 473948500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473948500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 473948500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 473386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 473386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 473386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 473386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 473386500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 473386500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18701.357377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18701.357377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18701.357377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18701.357377 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18679.181628 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18679.181628 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18679.181628 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18679.181628 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18679.181628 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18679.181628 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258395 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32574.709394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1245326 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291139 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.277428 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258813 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32576.208282 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1245284 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291557 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.271151 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.156414 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.726448 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29895.826532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.079015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002738 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.912348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994101 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2603.470497 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 85.754116 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29886.983669 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079452 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002617 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.912078 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994147 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2812 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29412 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29319 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13211317 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13211317 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 88920 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 88920 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 13211735 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13211735 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88693 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88693 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 22257 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 22257 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22765 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22765 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490574 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490574 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22765 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493805 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 516570 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22765 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493805 # number of overall hits -system.cpu.l2cache.overall_hits::total 516570 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22781 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 22781 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490516 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490516 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 22781 # 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number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291208 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288630 # number of overall misses -system.cpu.l2cache.overall_misses::total 291208 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4929880500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 195624000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 195624000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17812302500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17812302500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 195624000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22742183000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22937807000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 195624000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22742183000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22937807000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 88920 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 88920 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2562 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2562 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222597 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222597 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2562 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288688 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291250 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2562 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288688 # number of overall misses +system.cpu.l2cache.overall_misses::total 291250 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4929759500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4929759500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194891500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 194891500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17821559500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 17821559500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 194891500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22751319000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22946210500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 194891500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22751319000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22946210500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88693 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88693 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 22257 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 22257 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25343 # number of ReadCleanReq accesses(hits+misses) @@ -714,28 +719,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 782435 system.cpu.l2cache.overall_accesses::total 807778 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101724 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101724 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312067 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312067 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368887 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360505 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368887 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360505 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74592.312115 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74592.312115 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75882.079131 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75882.079131 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80041.262430 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80041.262430 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78767.777671 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75882.079131 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78793.552299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78767.777671 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.101093 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.101093 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312148 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312148 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101093 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368961 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.360557 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101093 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368961 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.360557 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74590.481306 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74590.481306 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76070.062451 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76070.062451 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80061.993198 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,58 +761,54 @@ system.cpu.l2cache.demand_mshr_hits::total 32 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2573 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2573 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222512 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222512 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2573 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288603 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2573 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288603 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268970500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169583000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169583000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15585424500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15585424500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169583000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19854395000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20023978000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169583000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19854395000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20023978000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222570 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222570 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288661 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291218 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288661 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291218 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4268849500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4268849500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169007000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15594098500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15594098500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169007000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19862948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20031955000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169007000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19862948000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20031955000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101527 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312029 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312029 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101527 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368852 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64592.312115 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64592.312115 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65908.666926 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65908.666926 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70043.074081 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70043.074081 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65908.666926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68794.832348 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68769.328516 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100896 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312110 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312110 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360517 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100896 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360517 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1609708 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 801990 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -816,8 +817,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 2028 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution @@ -825,51 +827,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55766720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258395 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.068609 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258813 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.071523 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1859313 99.53% 99.53% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8775 0.47% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1061152 99.49% 99.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5424 0.51% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1066591 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 917138000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 38015495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173665973 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225084 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190644 # Transaction distribution +system.membus.trans_dist::ReadResp 225126 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190686 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225084 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839092 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22865472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225126 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839218 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22868160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 547917 # Request fanout histogram +system.membus.snoop_fanout::samples 548001 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 547917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548001 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 547917 # Request fanout histogram -system.membus.reqLayer0.occupancy 917954000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548001 # Request fanout histogram +system.membus.reqLayer0.occupancy 918049500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554429500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554665000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 8ea31b650..52d6cf15b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410968 # Number of seconds simulated -sim_ticks 410968419000 # Number of ticks simulated -final_tick 410968419000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.452586 # Number of seconds simulated +sim_ticks 452585997000 # Number of ticks simulated +final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85599 # Simulator instruction rate (inst/s) -host_op_rate 105384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54910730 # Simulator tick rate (ticks/s) -host_mem_usage 322152 # Number of bytes of host memory used -host_seconds 7484.30 # Real time elapsed on the host +host_inst_rate 89374 # Simulator instruction rate (inst/s) +host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63138171 # Simulator tick rate (ticks/s) +host_mem_usage 323296 # Number of bytes of host memory used +host_seconds 7168.18 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7007424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12927040 # Number of bytes read from this memory -system.physmem.bytes_read::total 20160896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244672 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244672 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 201985 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315014 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 550972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17051004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31455069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49057044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 550972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 550972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10328463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10328463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10328463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 550972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17051004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31455069 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59385507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315014 # Number of read requests accepted -system.physmem.writeReqs 66323 # Number of write requests accepted -system.physmem.readBursts 315014 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20141440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19456 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory +system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 954063 # Number of read requests accepted +system.physmem.writeReqs 66305 # Number of write requests accepted +system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20160896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 304 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 67 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19880 # Per bank write bursts -system.physmem.perBankRdBursts::1 19436 # Per bank write bursts -system.physmem.perBankRdBursts::2 19769 # Per bank write bursts -system.physmem.perBankRdBursts::3 19866 # Per bank write bursts -system.physmem.perBankRdBursts::4 19687 # Per bank write bursts -system.physmem.perBankRdBursts::5 20154 # Per bank write bursts -system.physmem.perBankRdBursts::6 19548 # Per bank write bursts -system.physmem.perBankRdBursts::7 19410 # Per bank write bursts -system.physmem.perBankRdBursts::8 19409 # Per bank write bursts -system.physmem.perBankRdBursts::9 19464 # Per bank write bursts -system.physmem.perBankRdBursts::10 19401 # Per bank write bursts -system.physmem.perBankRdBursts::11 19757 # Per bank write bursts -system.physmem.perBankRdBursts::12 19512 # Per bank write bursts -system.physmem.perBankRdBursts::13 19953 # Per bank write bursts -system.physmem.perBankRdBursts::14 19499 # Per bank write bursts -system.physmem.perBankRdBursts::15 19965 # Per bank write bursts -system.physmem.perBankWrBursts::0 4261 # Per bank write bursts -system.physmem.perBankWrBursts::1 4104 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts +system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19636 # Per bank write bursts +system.physmem.perBankRdBursts::1 19225 # Per bank write bursts +system.physmem.perBankRdBursts::2 656809 # Per bank write bursts +system.physmem.perBankRdBursts::3 20104 # Per bank write bursts +system.physmem.perBankRdBursts::4 19566 # Per bank write bursts +system.physmem.perBankRdBursts::5 20746 # Per bank write bursts +system.physmem.perBankRdBursts::6 19449 # Per bank write bursts +system.physmem.perBankRdBursts::7 19830 # Per bank write bursts +system.physmem.perBankRdBursts::8 19282 # Per bank write bursts +system.physmem.perBankRdBursts::9 19792 # Per bank write bursts +system.physmem.perBankRdBursts::10 19287 # Per bank write bursts +system.physmem.perBankRdBursts::11 19476 # Per bank write bursts +system.physmem.perBankRdBursts::12 19427 # Per bank write bursts +system.physmem.perBankRdBursts::13 20933 # Per bank write bursts +system.physmem.perBankRdBursts::14 19357 # Per bank write bursts +system.physmem.perBankRdBursts::15 20857 # Per bank write bursts +system.physmem.perBankWrBursts::0 4254 # Per bank write bursts +system.physmem.perBankWrBursts::1 4108 # Per bank write bursts +system.physmem.perBankWrBursts::2 4140 # Per bank write bursts +system.physmem.perBankWrBursts::3 4154 # Per bank write bursts system.physmem.perBankWrBursts::4 4243 # Per bank write bursts -system.physmem.perBankWrBursts::5 4228 # Per bank write bursts +system.physmem.perBankWrBursts::5 4230 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts -system.physmem.perBankWrBursts::9 4094 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4153 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410968364500 # Total gap between requests +system.physmem.totGap 452585986500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315014 # Read request sizes (log2) +system.physmem.readPktSize::6 954063 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 121710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1023 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66305 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 8035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 900 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,112 +197,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.576479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.708862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.239774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54117 39.64% 39.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57190 41.89% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14847 10.88% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1353 0.99% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1460 1.07% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1428 1.05% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1211 0.89% 96.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1099 0.81% 97.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3810 2.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136515 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.350768 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.698276 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 557.584511 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4013 99.48% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.22% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 4 0.10% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.07% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11264-12287 2 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.416708 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.380496 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.197000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3413 84.61% 84.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 10 0.25% 84.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 440 10.91% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 77 1.91% 97.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 18 0.45% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.35% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.25% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.10% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads -system.physmem.totQLat 8815753021 # Total ticks spent queuing -system.physmem.totMemAccLat 14716565521 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1573550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28012.31 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.396271 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.276876 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3401 84.41% 84.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.22% 84.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 462 11.47% 96.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 50 1.24% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.89% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.40% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.45% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.25% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.15% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.10% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads +system.physmem.totQLat 15106541272 # Total ticks spent queuing +system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46762.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.01 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.31 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.06 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.46 # Data bus utilization in percentage -system.physmem.busUtilRead 0.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.readRowHits 218109 # Number of row buffer hits during reads -system.physmem.writeRowHits 26303 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.70 # Row buffer hit rate for writes -system.physmem.avgGap 1077703.88 # Average gap between requests -system.physmem.pageHitRate 64.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 518041440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282661500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1230403200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96374724480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 162040566750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 287505134730 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.583184 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 268934392735 # Time in different power states -system.physmem_0.memoryStateTime::REF 13723060000 # Time in different power states +system.physmem.busUtil 1.13 # Data bus utilization in percentage +system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing +system.physmem.readRowHits 788463 # Number of row buffer hits during reads +system.physmem.writeRowHits 25883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes +system.physmem.avgGap 443551.72 # Average gap between requests +system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.925147 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states +system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128308892015 # Time in different power states +system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 513943920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280425750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1224030600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26842305360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96023770920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 162348426750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 287445609300 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.438325 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 269449023468 # Time in different power states -system.physmem_1.memoryStateTime::REF 13723060000 # Time in different power states +system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) +system.physmem_1.averagePower 696.586172 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states +system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127794271282 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234596987 # Number of BP lookups -system.cpu.branchPred.condPredicted 161823961 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514568 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 122849584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 109536151 # Number of BTB hits +system.cpu.branchPred.lookups 234612390 # Number of BP lookups +system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups +system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.162818 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25674290 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300140 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,129 +419,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 821936839 # number of cpu cycles simulated +system.cpu.numCycles 905171995 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 85359069 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200718249 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234596987 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135210441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 720713354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31063509 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3414 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 371348285 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652804 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 821609958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.824964 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.165392 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 139667844 17.00% 17.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223418217 27.19% 44.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 99581089 12.12% 56.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 358942808 43.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 821609958 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285420 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.460840 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121271680 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 161528221 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484660379 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38631604 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518074 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181978 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13827 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248136929 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39965779 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518074 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178276857 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 80769172 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 209944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464321622 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82514289 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190649625 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25545503 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24955076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2266892 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41524383 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1701930 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225389846 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812446196 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358179405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876479 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350611616 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7266 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108773290 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366116518 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236097454 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1660812 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5332652 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168559259 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12361 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017121345 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18467813 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379846662 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032147150 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 207 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 821609958 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.237961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084868 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263952395 32.13% 32.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227112360 27.64% 59.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217754382 26.50% 86.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96663071 11.77% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16127742 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 821609958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63877670 18.90% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18143 0.01% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 157438093 46.58% 65.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116037067 34.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456371832 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195828 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -565,90 +563,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550148 0.25% 46.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322111232 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215588105 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017121345 # Type of FU issued -system.cpu.iq.rate 1.237469 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338007862 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332318 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3150451328 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504870795 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934275536 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876995 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565857 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued +system.cpu.iq.rate 1.123679 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321318894 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810313 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960669 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113875580 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1094 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18373 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107116958 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 20149 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518074 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35327155 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 46316 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168577176 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366116518 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236097454 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6621 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 106 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 49932 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18373 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437332 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784565 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221897 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974752675 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42368670 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497765117 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613949 # Number of branches executed -system.cpu.iew.exec_stores 194467406 # Number of stores executed -system.cpu.iew.exec_rate 1.185922 # Inst execution rate -system.cpu.iew.wb_sent 963726327 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960427986 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536047777 # num instructions producing a value -system.cpu.iew.wb_consumers 893284950 # num instructions consuming a value +system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed +system.cpu.iew.exec_branches 150611064 # Number of branches executed +system.cpu.iew.exec_stores 194473249 # Number of stores executed +system.cpu.iew.exec_rate 1.076871 # Inst execution rate +system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536045857 # num instructions producing a value +system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.168494 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600086 # average fanout of values written-back +system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357420302 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500888 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770788105 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.023277 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.776928 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 432159906 56.07% 56.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174391468 22.63% 78.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72936790 9.46% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32897876 4.27% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8538896 1.11% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14258442 1.85% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7269703 0.94% 96.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5974810 0.78% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360214 2.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770788105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -694,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360214 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1894569512 # The number of ROB reads -system.cpu.rob.rob_writes 2343126520 # The number of ROB writes -system.cpu.timesIdled 647387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 326881 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1977784350 # The number of ROB reads +system.cpu.rob.rob_writes 2343138350 # The number of ROB writes +system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.282975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.282975 # CPI: Total CPI of All Threads -system.cpu.ipc 0.779439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.779439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995803218 # number of integer regfile reads -system.cpu.int_regfile_writes 567908989 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889842 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794442903 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898512 # number of cc regfile writes -system.cpu.misc_regfile_reads 715818410 # number of misc regfile reads +system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads +system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995811618 # number of integer regfile reads +system.cpu.int_regfile_writes 567906414 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes +system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads +system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes +system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756184 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.933181 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258467 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 257783000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.933181 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756185 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839346712 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839346712 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286294274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286294274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907939 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907939 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414202213 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414202213 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414205370 # number of overall hits -system.cpu.dcache.overall_hits::total 414205370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3033975 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3033975 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043538 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043538 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits +system.cpu.dcache.overall_hits::total 414203768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4077513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4077513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4078159 # number of overall misses -system.cpu.dcache.overall_misses::total 4078159 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35335718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35335718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10020788350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10020788350 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses +system.cpu.dcache.overall_misses::total 4080391 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45356506350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45356506350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45356506350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45356506350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328249 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -776,309 +774,305 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418279726 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418279726 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418283529 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418283529 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008101 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.169866 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009750 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11646.674083 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11646.674083 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9602.705747 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9602.705747 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11123.571243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11123.571243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11121.809216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11121.809216 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 355417 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4792 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 74.168823 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735485 # number of writebacks -system.cpu.dcache.writebacks::total 735485 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 998769 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 998769 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322672 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322672 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks +system.cpu.dcache.writebacks::total 2756185 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1321441 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1321441 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1321441 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1321441 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035206 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035206 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720866 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720866 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756072 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756072 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756713 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168551 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11855.365255 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11855.365255 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8265.747518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8265.747518 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9238.689548 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9238.689548 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10916.480720 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10916.480720 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10916.090594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10916.090594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169351 # number of replacements -system.cpu.icache.tags.tagsinuse 510.555311 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 366173734 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169861 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.828545 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 247765500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.555311 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997178 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169363 # number of replacements +system.cpu.icache.tags.tagsinuse 510.872217 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364909729 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169873 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.583886 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 747866384 # 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number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 371348253 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8048.143078 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8048.143078 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8048.143078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8048.143078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8048.143078 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 82369 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 103 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3794 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 745337941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745337941 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364909744 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364909744 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364909744 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364909744 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364909744 # 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miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013981 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013981 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.828318 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8111.828318 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8111.828318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8111.828318 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 80154 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.710332 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 20.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4612 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4612 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4612 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4612 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4612 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4612 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169879 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169879 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169879 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169879 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169879 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169879 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39015177435 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39015177435 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39015177435 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39015177435 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39015177435 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39015177435 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013922 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013922 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013922 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7546.632607 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7546.632607 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7546.632607 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7546.632607 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7546.632607 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7546.632607 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks +system.cpu.icache.writebacks::total 5169363 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4154 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1349974 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355118 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4500 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790050 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 298717 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16361.529179 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14361886 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315081 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 45.581568 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 18036523000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 748.333626 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.076161 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8786.065763 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6700.053629 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007756 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.536259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.408939 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998628 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6481 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9883 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1434 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 10044 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4867 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1968 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7658 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.385681 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.613037 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 244381666 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 244381666 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 735261 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735261 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6546111 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6546111 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718464 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718464 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5166212 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 5166212 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286380 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1286380 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5166212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2004844 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7171056 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5166212 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2004844 # number of overall hits +system.cpu.l2cache.overall_hits::total 7171056 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 174 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 174 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2385 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2385 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3664 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3664 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 749468 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 749468 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3664 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 751853 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 755517 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3664 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 751853 # number of overall misses +system.cpu.l2cache.overall_misses::total 755517 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195908500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 195908500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 270114500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 270114500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 54154115500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 54154115500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 270114500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 54350024000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 54620138500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 270114500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 54350024000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 54620138500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 735261 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 735261 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6546111 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926559 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169863 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926559 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003443 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003443 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.000686 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72295.048953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73721.206332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72288.098870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72295.048953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1087,159 +1081,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7911839500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240756500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7671083000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17000279164 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24912118664 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.writebacks::writebacks 66305 # number of writebacks +system.cpu.l2cache.writebacks::total 66305 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1019 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1019 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 872 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 872 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1891 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1892 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 1891 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1892 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200528 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 200528 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 174 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1366 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3663 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3663 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 748596 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 748596 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3663 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 749962 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 753625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3663 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 749962 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200528 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 954153 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16518025996 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2993500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2993500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133767000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 248088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 248088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49620654000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49620654000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 248088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49754421000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 50002509000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 248088000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49754421000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16518025996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66520534996 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000684 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.053105 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.053105 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039718 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039751 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84133.974542 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17187.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17187.500000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 101015.976761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 101015.976761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68048.756360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68048.756360 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69667.055145 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69667.055145 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69998.314592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68048.756360 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70061.310975 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84133.974542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79063.250502 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15852127 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925581 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644320 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 9549 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 9495 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 54 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 801808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6778141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 245737 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23134399 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330871168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223499584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554370752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 544470 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 16396581 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.079179 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.270031 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 15098363 92.08% 92.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1298164 7.92% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 54 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 16396581 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8661548500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7754847439 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135063977 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 313637 # Transaction distribution -system.membus.trans_dist::Writeback 66323 # Transaction distribution -system.membus.trans_dist::CleanEvict 231789 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 313637 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 928172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 928172 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24405568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24405568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadResp 952696 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution +system.membus.trans_dist::CleanEvict 227453 # Transaction distribution +system.membus.trans_dist::UpgradeReq 174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 174 # Transaction distribution +system.membus.trans_dist::ReadExReq 1366 # Transaction distribution +system.membus.trans_dist::ReadExResp 1366 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 613142 # Request fanout histogram +system.membus.snoop_fanout::samples 1247995 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 613142 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 613142 # Request fanout histogram -system.membus.reqLayer0.occupancy 975944720 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1649749525 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 1247995 # Request fanout histogram +system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 24851d5c1..dd5f11d63 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.043724 # Number of seconds simulated -sim_ticks 1043723537500 # Number of ticks simulated -final_tick 1043723537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.045756 # Number of seconds simulated +sim_ticks 1045756396500 # Number of ticks simulated +final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 832063 # Simulator instruction rate (inst/s) -host_op_rate 1022241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1358287943 # Simulator tick rate (ticks/s) -host_mem_usage 323064 # Number of bytes of host memory used -host_seconds 768.41 # Real time elapsed on the host +host_inst_rate 734670 # Simulator instruction rate (inst/s) +host_op_rate 902587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1201635964 # Simulator tick rate (ticks/s) +host_mem_usage 323928 # Number of bytes of host memory used +host_seconds 870.28 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 113216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18469760 # Number of bytes read from this memory -system.physmem.bytes_read::total 18582976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 113216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 113216 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory +system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288590 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290359 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 108473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17696027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17804500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108473 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17696027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21857558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087447075 # number of cpu cycles simulated +system.cpu.numCycles 2091512793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366787 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087447074.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364860 # Number of branches fetched @@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730744 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640237 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996538500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 782004 # n system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18611031000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18611031000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3677169000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22288200000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22288200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22288200000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22288200000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26114.111363 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26114.111363 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.996942 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.996942 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28501.388740 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28501.388740 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28496.323562 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28496.323562 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,8 +304,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 89072 # number of writebacks -system.cpu.dcache.writebacks::total 89072 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks +system.cpu.dcache.writebacks::total 88995 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17898311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17898311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3607846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3607846000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1752000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21506157000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21506157000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21507909000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21507909000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,26 +342,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25114.091879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25114.091879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52043.996942 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52043.996942 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27501.374036 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27501.374036 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27498.726574 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27498.726574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464458 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464458 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207225000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207225000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207225000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207225000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207225000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207225000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20300.254702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20300.254702 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20300.254702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20300.254702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20300.254702 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,93 +413,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 8769 # number of writebacks +system.cpu.icache.writebacks::total 8769 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 197017000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 197017000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 197017000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 197017000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 197017000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 197017000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19300.254702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19300.254702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19300.254702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19300.254702 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257579 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.728627 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218059 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290322 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.195545 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257772 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2506.605810 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 48.754609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30071.368207 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001488 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.917705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12984085 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12984085 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 89072 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 89072 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8439 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8439 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490322 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490322 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8439 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501991 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8439 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493552 # number of overall hits -system.cpu.l2cache.overall_hits::total 501991 # number of overall hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits +system.cpu.l2cache.overall_hits::total 501982 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1769 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 1769 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222497 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222497 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1769 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288590 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290359 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1769 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288590 # number of overall misses -system.cpu.l2cache.overall_misses::total 290359 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469946000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3469946000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 93021000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11681407500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 11681407500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 93021000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15151353500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15244374500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 93021000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15151353500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15244374500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 89072 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 89072 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses +system.cpu.l2cache.overall_misses::total 290368 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) @@ -514,28 +520,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 782142 system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.173295 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.173295 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312137 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312137 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173295 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368974 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366453 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173295 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368974 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366453 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.960767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.960767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52583.945732 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52501.415749 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52501.415749 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.814995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52583.945732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.311549 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.814995 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,58 +552,54 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 184 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 184 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1769 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1769 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222497 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222497 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1769 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290359 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1769 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288590 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290359 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2809016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2809016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 75331000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9456437500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9456437500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75331000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12265453500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12340784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75331000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12265453500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12340784500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.173295 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312137 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312137 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366453 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368974 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366453 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.960767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.960767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42583.945732 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42501.415749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42501.415749 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42583.945732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.311549 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.814995 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -606,8 +608,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 888114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution @@ -615,51 +618,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55757696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56411008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257579 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1836744 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002089 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045741 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1832914 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3823 0.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1836744 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 878654500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224266 # Transaction distribution -system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190085 # Transaction distribution +system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190094 # Transaction distribution system.membus.trans_dist::ReadExReq 66093 # Transaction distribution system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836901 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 546599 # Request fanout histogram +system.membus.snoop_fanout::samples 546561 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546599 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546599 # Request fanout histogram -system.membus.reqLayer0.occupancy 811365948 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 546561 # Request fanout histogram +system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1452169448 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 15844baba..e086bc978 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059549 # Number of seconds simulated -sim_ticks 59549031000 # Number of ticks simulated -final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059474 # Number of seconds simulated +sim_ticks 59473862000 # Number of ticks simulated +final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320796 # Simulator instruction rate (inst/s) -host_op_rate 320796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216005540 # Simulator tick rate (ticks/s) -host_mem_usage 307628 # Number of bytes of host memory used -host_seconds 275.68 # Real time elapsed on the host +host_inst_rate 342067 # Simulator instruction rate (inst/s) +host_op_rate 342067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 230037089 # Simulator tick rate (ticks/s) +host_mem_usage 307480 # Number of bytes of host memory used +host_seconds 258.54 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 500352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147264 # Number of bytes read from this memory -system.physmem.bytes_read::total 10647616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 500352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158551 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166369 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114385 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114385 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8402353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170401832 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178804186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8402353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122934662 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122934662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8402353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170401832 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301738848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166369 # Number of read requests accepted -system.physmem.writeReqs 114385 # Number of write requests accepted -system.physmem.readBursts 166369 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114385 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10647296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7318592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10647616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7320640 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 432448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10149376 # Number of bytes read from this memory +system.physmem.bytes_read::total 10581824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7325760 # Number of bytes written to this memory +system.physmem.bytes_written::total 7325760 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158584 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165341 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114465 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114465 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7271228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170652715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 177923942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7271228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 123176127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 123176127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7271228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170652715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301100070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165341 # Number of read requests accepted +system.physmem.writeReqs 114465 # Number of write requests accepted +system.physmem.readBursts 165341 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114465 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10581376 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7323904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10581824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10447 # Per bank write bursts -system.physmem.perBankRdBursts::1 10506 # Per bank write bursts -system.physmem.perBankRdBursts::2 10283 # Per bank write bursts -system.physmem.perBankRdBursts::3 10092 # Per bank write bursts -system.physmem.perBankRdBursts::4 10413 # Per bank write bursts -system.physmem.perBankRdBursts::5 10414 # Per bank write bursts -system.physmem.perBankRdBursts::6 9828 # Per bank write bursts -system.physmem.perBankRdBursts::7 10274 # Per bank write bursts -system.physmem.perBankRdBursts::8 10580 # Per bank write bursts -system.physmem.perBankRdBursts::9 10645 # Per bank write bursts -system.physmem.perBankRdBursts::10 10558 # Per bank write bursts -system.physmem.perBankRdBursts::11 10261 # Per bank write bursts -system.physmem.perBankRdBursts::12 10296 # Per bank write bursts -system.physmem.perBankRdBursts::13 10620 # Per bank write bursts -system.physmem.perBankRdBursts::14 10515 # Per bank write bursts -system.physmem.perBankRdBursts::15 10632 # Per bank write bursts -system.physmem.perBankWrBursts::0 7162 # Per bank write bursts -system.physmem.perBankWrBursts::1 7273 # Per bank write bursts -system.physmem.perBankWrBursts::2 7295 # Per bank write bursts -system.physmem.perBankWrBursts::3 7000 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10312 # Per bank write bursts +system.physmem.perBankRdBursts::1 10359 # Per bank write bursts +system.physmem.perBankRdBursts::2 10206 # Per bank write bursts +system.physmem.perBankRdBursts::3 10057 # Per bank write bursts +system.physmem.perBankRdBursts::4 10348 # Per bank write bursts +system.physmem.perBankRdBursts::5 10339 # Per bank write bursts +system.physmem.perBankRdBursts::6 9776 # Per bank write bursts +system.physmem.perBankRdBursts::7 10207 # Per bank write bursts +system.physmem.perBankRdBursts::8 10534 # Per bank write bursts +system.physmem.perBankRdBursts::9 10607 # Per bank write bursts +system.physmem.perBankRdBursts::10 10498 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10274 # Per bank write bursts +system.physmem.perBankRdBursts::13 10561 # Per bank write bursts +system.physmem.perBankRdBursts::14 10464 # Per bank write bursts +system.physmem.perBankRdBursts::15 10564 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7296 # Per bank write bursts +system.physmem.perBankWrBursts::3 7002 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7181 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts system.physmem.perBankWrBursts::6 6833 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6994 # Per bank write bursts -system.physmem.perBankWrBursts::10 7113 # Per bank write bursts -system.physmem.perBankWrBursts::11 6992 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7295 # Per bank write bursts -system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::7 7099 # Per bank write bursts +system.physmem.perBankWrBursts::8 7225 # Per bank write bursts +system.physmem.perBankWrBursts::9 7000 # Per bank write bursts +system.physmem.perBankWrBursts::10 7115 # Per bank write bursts +system.physmem.perBankWrBursts::11 7034 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7299 # Per bank write bursts +system.physmem.perBankWrBursts::14 7308 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59549007000 # Total gap between requests +system.physmem.totGap 59473838000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166369 # Read request sizes (log2) +system.physmem.readPktSize::6 165341 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114385 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1588 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114465 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,122 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54768 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.014023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.067660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.383666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11850 21.64% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5663 10.34% 67.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2902 5.30% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2048 3.74% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1635 2.99% 86.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1469 2.68% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6030 11.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54768 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.634839 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.413145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7035 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 327.237051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.297949 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.344141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19597 35.82% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11811 21.59% 57.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5572 10.18% 67.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3684 6.73% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2893 5.29% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2049 3.74% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1621 2.96% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1502 2.75% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5985 10.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.479761 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.363256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7038 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.247940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.232365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.745442 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6264 89.00% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 17 0.24% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 601 8.54% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 122 1.73% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 6 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7041 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7041 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.252805 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.237164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.745060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6251 88.78% 88.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.23% 89.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 606 8.61% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 134 1.90% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 28 0.40% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads -system.physmem.totQLat 2001235750 # Total ticks spent queuing -system.physmem.totMemAccLat 5120560750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7041 # Writes before turning the bus around for reads +system.physmem.totQLat 1980163000 # Total ticks spent queuing +system.physmem.totMemAccLat 5080175500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11976.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30726.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 177.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 123.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 177.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 123.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.36 # Data bus utilization in percentage -system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 144462 # Number of row buffer hits during reads -system.physmem.writeRowHits 81475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes -system.physmem.avgGap 212103.86 # Average gap between requests -system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199614240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108916500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641355000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12587581890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24683289750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42478615620 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.426150 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40913813750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing +system.physmem.readRowHits 143867 # Number of row buffer hits during reads +system.physmem.writeRowHits 81182 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.92 # Row buffer hit rate for writes +system.physmem.avgGap 212553.83 # Average gap between requests +system.physmem.pageHitRate 80.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199175760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108677250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 636448800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369204480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12421725570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24786732000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42406345140 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.051581 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41087166750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16639693750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16398707250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214137000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116840625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655777200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13157757450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24183135750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42588370425 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.269477 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40075806250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1988220000 # Time in different power states +system.physmem_1.actEnergy 214341120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116952000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 652938000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 372237120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3884381280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13062187260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24224923500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42527960280 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.096508 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40147172500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1985880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17478332750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17338598750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14666095 # Number of BP lookups -system.cpu.branchPred.condPredicted 9488989 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9897774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6385513 # Number of BTB hits +system.cpu.branchPred.lookups 14666171 # Number of BP lookups +system.cpu.branchPred.condPredicted 9489023 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386095 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9897790 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6385525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.514637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708089 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84886 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.514654 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708105 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84877 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569916 # DTB read hits -system.cpu.dtb.read_misses 97322 # DTB read misses +system.cpu.dtb.read_hits 20569903 # DTB read hits +system.cpu.dtb.read_misses 97320 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667238 # DTB read accesses -system.cpu.dtb.write_hits 14665322 # DTB write hits +system.cpu.dtb.read_accesses 20667223 # DTB read accesses +system.cpu.dtb.write_hits 14665328 # DTB write hits system.cpu.dtb.write_misses 9407 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674729 # DTB write accesses -system.cpu.dtb.data_hits 35235238 # DTB hits -system.cpu.dtb.data_misses 106729 # DTB misses +system.cpu.dtb.write_accesses 14674735 # DTB write accesses +system.cpu.dtb.data_hits 35235231 # DTB hits +system.cpu.dtb.data_misses 106727 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35341967 # DTB accesses -system.cpu.itb.fetch_hits 25606453 # ITB hits -system.cpu.itb.fetch_misses 5227 # ITB misses +system.cpu.dtb.data_accesses 35341958 # DTB accesses +system.cpu.itb.fetch_hits 25606544 # ITB hits +system.cpu.itb.fetch_misses 5228 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25611680 # ITB accesses +system.cpu.itb.fetch_accesses 25611772 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,65 +320,65 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119098062 # number of cpu cycles simulated +system.cpu.numCycles 118947724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1106110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1106117 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.346683 # CPI: cycles per instruction -system.cpu.ipc 0.742565 # IPC: instructions per cycle -system.cpu.tickCycles 91473495 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27624567 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.344983 # CPI: cycles per instruction +system.cpu.ipc 0.743504 # IPC: instructions per cycle +system.cpu.tickCycles 91473408 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27474316 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 200766 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.715334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616231 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4070.683377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616213 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.973411 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.973324 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.715334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.683377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993819 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993819 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 686 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3361 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176386 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282965 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282965 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333266 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333266 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616231 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616231 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616231 # number of overall hits -system.cpu.dcache.overall_hits::total 34616231 # number of overall hits +system.cpu.dcache.tags.tag_accesses 70176360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616213 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616213 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616213 # number of overall hits +system.cpu.dcache.overall_hits::total 34616213 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280111 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280111 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses -system.cpu.dcache.overall_misses::total 369531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4765724000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21723340000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26489064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26489064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26489064000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369536 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369536 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369536 # number of overall misses +system.cpu.dcache.overall_misses::total 369536 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4768019500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21708920500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26476940000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26476940000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26476940000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985762 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985762 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985762 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985762 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses @@ -389,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71682.927819 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71649.149203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,16 +403,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168453 # number of writebacks -system.cpu.dcache.writebacks::total 168453 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168423 # number of writebacks +system.cpu.dcache.writebacks::total 168423 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 28115 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136554 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136554 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164669 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136559 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136559 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164674 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61305 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61305 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses @@ -423,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204862 system.cpu.dcache.demand_mshr_misses::total 204862 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204862 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204862 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678183500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10981560500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13659744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13659744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13659744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2680071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10970928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13650999500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13650999500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13650999500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -439,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43686.216459 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43686.216459 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76496.168769 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76496.168769 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66677.783093 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66677.783093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66677.783093 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66677.783093 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 152851 # number of replacements -system.cpu.icache.tags.tagsinuse 1932.369225 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25451553 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 154899 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 164.310635 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42309465500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1932.369225 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.943540 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.943540 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 152856 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.301021 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25451639 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.305886 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42254913500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.301021 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943506 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943506 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1041 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51367805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51367805 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25451553 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25451553 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25451553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25451553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25451553 # number of overall hits -system.cpu.icache.overall_hits::total 25451553 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 154900 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154900 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 154900 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25606453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25606453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25606453 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 51367992 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51367992 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25451639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25451639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25451639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25451639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25451639 # number of overall hits +system.cpu.icache.overall_hits::total 25451639 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 154905 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154905 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 154905 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 154905 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 154905 # number of overall misses +system.cpu.icache.overall_misses::total 154905 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2479923000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2479923000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2479923000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2479923000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2479923000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25606544 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25606544 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25606544 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25606544 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25606544 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16468.450613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16468.450613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16468.450613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16468.450613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16009.315387 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,129 +508,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154900 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154900 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154900 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 154900 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154900 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2396064000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2396064000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2396064000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2396064000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 152856 # number of writebacks +system.cpu.icache.writebacks::total 152856 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154905 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154905 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154905 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154905 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154905 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2325019000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2325019000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325019000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2325019000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164521 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.449231 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133370 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30430.165732 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 403981 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165480 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.441268 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 25961.899693 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2481.819774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1981.860360 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.792294 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1089 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11867 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18864 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 125 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.979919 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 6016150 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 6016150 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 168423 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 168423 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 152856 # 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number of writebacks +system.cpu.l2cache.writebacks::total 114465 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 115 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 115 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130883 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130883 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6758 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6758 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27701 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27701 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6758 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165342 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6758 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158584 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165342 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9313621000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9313621000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 469343000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 469343000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1957795000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1957795000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 469343000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11271416000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11740759000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 469343000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11271416000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11740759000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050478 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.462445 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.462445 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911708 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043627 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459581 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.774102 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459581 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 713379 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 353617 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 713389 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 353622 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4036 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4036 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 216208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 282888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 152856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 154900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154905 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462665 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1073140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9913536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132445 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004759 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.068819 # Request fanout histogram +system.cpu.toL2Bus.pkt_count::total 1073155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19696640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23890240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43586880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133370 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 493137 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008184 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.090096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 841799 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 489101 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4036 0.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 232349997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 493137 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 677973500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 232357497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307296493 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307299487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35487 # Transaction distribution -system.membus.trans_dist::Writeback 114385 # Transaction distribution -system.membus.trans_dist::CleanEvict 16125 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35487 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 463248 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17968256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34458 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114465 # Transaction distribution +system.membus.trans_dist::CleanEvict 14983 # Transaction distribution +system.membus.trans_dist::ReadExReq 130883 # Transaction distribution +system.membus.trans_dist::ReadExResp 130883 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34458 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 460130 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17907584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17907584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296879 # Request fanout histogram +system.membus.snoop_fanout::samples 294789 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296879 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294789 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296879 # Request fanout histogram -system.membus.reqLayer0.occupancy 824874000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294789 # Request fanout histogram +system.membus.reqLayer0.occupancy 822943500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 878418750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 872924250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index bea1e6fc8..b43434371 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022357 # Number of seconds simulated -sim_ticks 22356634500 # Number of ticks simulated -final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022297 # Number of seconds simulated +sim_ticks 22296591500 # Number of ticks simulated +final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 213363 # Simulator instruction rate (inst/s) -host_op_rate 213363 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59931818 # Simulator tick rate (ticks/s) -host_mem_usage 308400 # Number of bytes of host memory used -host_seconds 373.03 # Real time elapsed on the host +host_inst_rate 221726 # Simulator instruction rate (inst/s) +host_op_rate 221726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62113736 # Simulator tick rate (ticks/s) +host_mem_usage 308500 # Number of bytes of host memory used +host_seconds 358.96 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 471552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10150720 # Number of bytes read from this memory -system.physmem.bytes_read::total 10622272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 471552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7318272 # Number of bytes written to this memory -system.physmem.bytes_written::total 7318272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7368 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158605 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165973 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114348 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114348 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21092262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 454036139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 475128401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21092262 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327342293 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327342293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21092262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 454036139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 802470694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165973 # Number of read requests accepted -system.physmem.writeReqs 114348 # Number of write requests accepted -system.physmem.readBursts 165973 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114348 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10621952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 7316672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10622272 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7318272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 409984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153216 # Number of bytes read from this memory +system.physmem.bytes_read::total 10563200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 409984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7322432 # Number of bytes written to this memory +system.physmem.bytes_written::total 7322432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6406 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165050 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114413 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114413 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18387743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 455370768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 473758511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18387743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 328410376 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 328410376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18387743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 455370768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802168888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165050 # Number of read requests accepted +system.physmem.writeReqs 114413 # Number of write requests accepted +system.physmem.readBursts 165050 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114413 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10562816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7320896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10563200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10420 # Per bank write bursts -system.physmem.perBankRdBursts::1 10451 # Per bank write bursts -system.physmem.perBankRdBursts::2 10285 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts -system.physmem.perBankRdBursts::4 10402 # Per bank write bursts -system.physmem.perBankRdBursts::5 10375 # Per bank write bursts -system.physmem.perBankRdBursts::6 9822 # Per bank write bursts -system.physmem.perBankRdBursts::7 10280 # Per bank write bursts -system.physmem.perBankRdBursts::8 10559 # Per bank write bursts -system.physmem.perBankRdBursts::9 10640 # Per bank write bursts -system.physmem.perBankRdBursts::10 10517 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10263 # Per bank write bursts -system.physmem.perBankRdBursts::13 10582 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10613 # Per bank write bursts -system.physmem.perBankWrBursts::0 7161 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10292 # Per bank write bursts +system.physmem.perBankRdBursts::1 10329 # Per bank write bursts +system.physmem.perBankRdBursts::2 10209 # Per bank write bursts +system.physmem.perBankRdBursts::3 10020 # Per bank write bursts +system.physmem.perBankRdBursts::4 10344 # Per bank write bursts +system.physmem.perBankRdBursts::5 10314 # Per bank write bursts +system.physmem.perBankRdBursts::6 9779 # Per bank write bursts +system.physmem.perBankRdBursts::7 10195 # Per bank write bursts +system.physmem.perBankRdBursts::8 10531 # Per bank write bursts +system.physmem.perBankRdBursts::9 10599 # Per bank write bursts +system.physmem.perBankRdBursts::10 10453 # Per bank write bursts +system.physmem.perBankRdBursts::11 10204 # Per bank write bursts +system.physmem.perBankRdBursts::12 10247 # Per bank write bursts +system.physmem.perBankRdBursts::13 10532 # Per bank write bursts +system.physmem.perBankRdBursts::14 10447 # Per bank write bursts +system.physmem.perBankRdBursts::15 10549 # Per bank write bursts +system.physmem.perBankWrBursts::0 7163 # Per bank write bursts system.physmem.perBankWrBursts::1 7267 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 7000 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6835 # Per bank write bursts -system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6995 # Per bank write bursts -system.physmem.perBankWrBursts::10 7101 # Per bank write bursts -system.physmem.perBankWrBursts::11 6988 # Per bank write bursts -system.physmem.perBankWrBursts::12 6991 # Per bank write bursts -system.physmem.perBankWrBursts::13 7292 # Per bank write bursts +system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::6 6836 # Per bank write bursts +system.physmem.perBankWrBursts::7 7102 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 7001 # Per bank write bursts +system.physmem.perBankWrBursts::10 7100 # Per bank write bursts +system.physmem.perBankWrBursts::11 7020 # Per bank write bursts +system.physmem.perBankWrBursts::12 6992 # Per bank write bursts +system.physmem.perBankWrBursts::13 7297 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22356603500 # Total gap between requests +system.physmem.totGap 22296560500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165973 # Read request sizes (log2) +system.physmem.readPktSize::6 165050 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114348 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43039 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32162 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114413 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43023 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32167 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6088 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,125 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.051408 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.164629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.365120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18284 34.97% 34.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10551 20.18% 55.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5984 11.44% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2964 5.67% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2982 5.70% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1592 3.04% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1956 3.74% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 963 1.84% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7012 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52288 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.745743 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 338.273336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6986 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52310 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.858612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.924906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.625607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18434 35.24% 35.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10645 20.35% 55.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5863 11.21% 66.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2906 5.56% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2975 5.69% 78.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1493 2.85% 80.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2022 3.87% 84.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 988 1.89% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6984 13.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52310 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.610300 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.218951 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6987 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6989 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.357562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.328073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.050353 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6097 87.24% 87.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 474 6.78% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 201 2.88% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 97 1.39% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.70% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 24 0.34% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6989 # Writes before turning the bus around for reads -system.physmem.totQLat 5746744750 # Total ticks spent queuing -system.physmem.totMemAccLat 8858644750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 829840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34625.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6990 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6990 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.364664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.334270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.064891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6098 87.24% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.37% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 456 6.52% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 208 2.98% 97.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 103 1.47% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.82% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.30% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.11% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6990 # Writes before turning the bus around for reads +system.physmem.totQLat 5731685000 # Total ticks spent queuing +system.physmem.totMemAccLat 8826260000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 825220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34728.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53375.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 475.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.27 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 475.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53478.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 473.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 328.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 473.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 328.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.27 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 3.70 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.57 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 145973 # Number of row buffer hits during reads -system.physmem.writeRowHits 82020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.73 # Row buffer hit rate for writes -system.physmem.avgGap 79753.58 # Average gap between requests -system.physmem.pageHitRate 81.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190882440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104152125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640161600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6647542920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7581572250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16993287015 # Total energy per rank (pJ) -system.physmem_0.averagePower 760.170138 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12528806000 # Time in different power states -system.physmem_0.memoryStateTime::REF 746460000 # Time in different power states +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 145441 # Number of row buffer hits during reads +system.physmem.writeRowHits 81669 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.12 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.38 # Row buffer hit rate for writes +system.physmem.avgGap 79783.59 # Average gap between requests +system.physmem.pageHitRate 81.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190375920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 103875750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 635356800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 369036000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6553881090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7626357750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16934890590 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.674656 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12601715000 # Time in different power states +system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9079331500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8946212500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204271200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111457500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654100200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371699280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6857633520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7397282250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17056519710 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.998761 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12224344750 # Time in different power states -system.physmem_1.memoryStateTime::REF 746460000 # Time in different power states +system.physmem_1.actEnergy 204815520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111754500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 651565200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371893680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6747677955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7456388250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17000102385 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.598381 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12320846000 # Time in different power states +system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9383970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9227273000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16500558 # Number of BP lookups -system.cpu.branchPred.condPredicted 10689411 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 329507 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9043813 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7288978 # Number of BTB hits +system.cpu.branchPred.lookups 16493971 # Number of BP lookups +system.cpu.branchPred.condPredicted 10685365 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 327092 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8977635 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7282355 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.596293 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974529 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2931 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.116630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1973286 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2952 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22520885 # DTB read hits -system.cpu.dtb.read_misses 225850 # DTB read misses -system.cpu.dtb.read_acv 12 # DTB read access violations -system.cpu.dtb.read_accesses 22746735 # DTB read accesses -system.cpu.dtb.write_hits 15825785 # DTB write hits -system.cpu.dtb.write_misses 44675 # DTB write misses -system.cpu.dtb.write_acv 5 # DTB write access violations -system.cpu.dtb.write_accesses 15870460 # DTB write accesses -system.cpu.dtb.data_hits 38346670 # DTB hits -system.cpu.dtb.data_misses 270525 # DTB misses -system.cpu.dtb.data_acv 17 # DTB access violations -system.cpu.dtb.data_accesses 38617195 # DTB accesses -system.cpu.itb.fetch_hits 13761847 # ITB hits -system.cpu.itb.fetch_misses 29330 # ITB misses +system.cpu.dtb.read_hits 22518673 # DTB read hits +system.cpu.dtb.read_misses 225961 # DTB read misses +system.cpu.dtb.read_acv 15 # DTB read access violations +system.cpu.dtb.read_accesses 22744634 # DTB read accesses +system.cpu.dtb.write_hits 15824450 # DTB write hits +system.cpu.dtb.write_misses 44763 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15869213 # DTB write accesses +system.cpu.dtb.data_hits 38343123 # DTB hits +system.cpu.dtb.data_misses 270724 # DTB misses +system.cpu.dtb.data_acv 19 # DTB access violations +system.cpu.dtb.data_accesses 38613847 # DTB accesses +system.cpu.itb.fetch_hits 13750650 # ITB hits +system.cpu.itb.fetch_misses 29320 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13791177 # ITB accesses +system.cpu.itb.fetch_accesses 13779970 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,141 +324,141 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44713274 # number of cpu cycles simulated +system.cpu.numCycles 44593188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15584768 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105191572 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16500558 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9263507 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27593237 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 896542 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 162 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 325871 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13761847 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 191924 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15564341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105145283 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16493971 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9255641 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27572822 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 891924 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 262 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4803 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 325760 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13750650 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190232 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.393046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.394343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.128103 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24416716 55.55% 55.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1522401 3.46% 59.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379227 3.14% 62.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1505485 3.42% 65.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4199085 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1828470 4.16% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669319 1.52% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1052182 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7384298 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24384273 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1520929 3.46% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1376099 3.13% 62.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1504413 3.43% 65.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4198532 9.56% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1828676 4.16% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 668520 1.52% 80.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050487 2.39% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7382110 16.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43957183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369030 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.352580 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14931500 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9767964 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18310970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 595597 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 351152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3708003 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98860 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103215952 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 311866 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 351152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15279451 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4431592 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96231 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18542963 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5255794 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102192828 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5698 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 95463 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 341437 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4753642 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61435412 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123253139 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122935807 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 317331 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43914039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369876 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.357878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14911775 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9756593 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18301996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 594945 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348730 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3706760 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98994 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103174683 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312811 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 348730 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15258388 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4434115 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96788 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18534618 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5241400 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102158813 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5649 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 94745 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 345515 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4735615 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61411273 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123213365 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122896091 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 317273 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8888531 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5692 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5745 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2361848 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23156457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16385404 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1258348 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502815 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90834629 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5552 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88691609 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70456 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11248424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4497706 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 969 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43957183 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.017682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245665 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8864392 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5712 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5765 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2362727 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23149705 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16384887 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1256801 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 494099 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90814957 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5561 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88678954 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70817 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11228761 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4483589 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 978 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43914039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.019376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17476881 39.76% 39.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5730177 13.04% 52.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5107740 11.62% 64.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4380373 9.97% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4328154 9.85% 84.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2635103 5.99% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1947598 4.43% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378142 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 973015 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17441953 39.72% 39.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5726957 13.04% 52.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5104887 11.62% 64.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4381256 9.98% 74.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4320313 9.84% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2639459 6.01% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1947949 4.44% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377906 3.14% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 973359 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43957183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43914039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243362 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1165216 46.16% 55.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1115524 44.19% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 242855 9.63% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1163309 46.14% 55.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1115010 44.23% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49430492 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43978 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49423838 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43986 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121147 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120628 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39084 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121174 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120676 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39089 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -481,84 +480,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22917985 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16018139 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22912706 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16017331 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88691609 # Type of FU issued -system.cpu.iq.rate 1.983563 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524102 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223325364 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101690449 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86898361 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 609595 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 418176 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299341 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90910760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 304951 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1670602 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88678954 # Type of FU issued +system.cpu.iq.rate 1.988621 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2521174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223254204 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101651163 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86893480 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 609734 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418232 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299390 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90895107 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305021 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1671418 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2879819 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5660 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20258 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1772027 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2873067 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20361 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1771510 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3047 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205936 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3045 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 204833 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 351152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1286887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2706445 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100341607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125884 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23156457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16385404 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5552 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3769 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2705021 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20258 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 121859 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 151192 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 273051 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87981340 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22747403 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 710269 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 348730 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1277507 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2721681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100319642 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124919 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23149705 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16384887 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5561 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3725 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2720217 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20361 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118662 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150973 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 269635 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87973235 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22745315 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 705719 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9501426 # number of nop insts executed -system.cpu.iew.exec_refs 38618193 # number of memory reference insts executed -system.cpu.iew.exec_branches 15127263 # Number of branches executed -system.cpu.iew.exec_stores 15870790 # Number of stores executed -system.cpu.iew.exec_rate 1.967678 # Inst execution rate -system.cpu.iew.wb_sent 87600358 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87197702 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33849535 # num instructions producing a value -system.cpu.iew.wb_consumers 44277575 # num instructions consuming a value +system.cpu.iew.exec_nop 9499124 # number of nop insts executed +system.cpu.iew.exec_refs 38614853 # number of memory reference insts executed +system.cpu.iew.exec_branches 15126858 # Number of branches executed +system.cpu.iew.exec_stores 15869538 # Number of stores executed +system.cpu.iew.exec_rate 1.972795 # Inst execution rate +system.cpu.iew.wb_sent 87594856 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87192870 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33852684 # num instructions producing a value +system.cpu.iew.wb_consumers 44279326 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.950152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764485 # average fanout of values written-back +system.cpu.iew.wb_rate 1.955296 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8791000 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8765402 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 232388 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42666920 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.070472 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884283 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 229860 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42628268 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.072350 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.885151 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21190783 49.67% 49.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6285871 14.73% 64.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2905995 6.81% 71.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1744112 4.09% 75.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1680276 3.94% 79.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1128586 2.65% 81.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203447 2.82% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 797041 1.87% 86.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5730809 13.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21157300 49.63% 49.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6282680 14.74% 64.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2903206 6.81% 71.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1743375 4.09% 75.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1680050 3.94% 79.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128930 2.65% 81.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1204133 2.82% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 796945 1.87% 86.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5731649 13.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42666920 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42628268 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,333 +603,339 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5730809 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132750441 # The number of ROB reads -system.cpu.rob.rob_writes 195556891 # The number of ROB writes -system.cpu.timesIdled 46372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 756091 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5731649 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132685351 # The number of ROB reads +system.cpu.rob.rob_writes 195501271 # The number of ROB writes +system.cpu.timesIdled 46319 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 679149 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.561783 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.561783 # CPI: Total CPI of All Threads -system.cpu.ipc 1.780048 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.780048 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116466074 # number of integer regfile reads -system.cpu.int_regfile_writes 57713698 # number of integer regfile writes -system.cpu.fp_regfile_reads 255059 # number of floating regfile reads -system.cpu.fp_regfile_writes 240376 # number of floating regfile writes -system.cpu.misc_regfile_reads 38265 # number of misc regfile reads +system.cpu.cpi 0.560274 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.560274 # CPI: Total CPI of All Threads +system.cpu.ipc 1.784841 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.784841 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116453986 # number of integer regfile reads +system.cpu.int_regfile_writes 57709287 # number of integer regfile writes +system.cpu.fp_regfile_reads 255067 # number of floating regfile reads +system.cpu.fp_regfile_writes 240450 # number of floating regfile writes +system.cpu.misc_regfile_reads 38270 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201297 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.745765 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33997888 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205393 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.526031 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 229746500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.745765 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993834 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993834 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201399 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.676822 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33995451 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205495 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.432011 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 229821500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.676822 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993818 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993818 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2788 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2778 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1242 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70843209 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70843209 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20436554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20436554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561278 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561278 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33997832 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33997832 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33997832 # number of overall hits -system.cpu.dcache.overall_hits::total 33997832 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268921 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268921 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052099 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321020 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321020 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321020 # number of overall misses -system.cpu.dcache.overall_misses::total 1321020 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17355062000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89131929604 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106486991604 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106486991604 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106486991604 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20705475 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20705475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70838999 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70838999 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20434147 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20434147 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561246 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561246 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33995393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33995393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33995393 # number of overall hits +system.cpu.dcache.overall_hits::total 33995393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269170 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052131 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052131 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321301 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321301 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321301 # number of overall misses +system.cpu.dcache.overall_misses::total 1321301 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17282869000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89120990413 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106403859413 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106403859413 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106403859413 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20703317 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20703317 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35318852 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35318852 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35318852 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35318852 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012988 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071996 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037403 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037403 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037403 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80609.674043 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6869550 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35316694 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35316694 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35316694 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35316694 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071998 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037413 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037413 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037413 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037413 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80529.613928 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6870751 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88969 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 89149 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.212849 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.070421 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168788 # number of writebacks -system.cpu.dcache.writebacks::total 168788 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206925 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206925 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908702 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908702 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115627 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115627 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115627 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205393 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205393 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205393 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3212836500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14233206202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17446042702 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17446042702 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002994 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005815 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005815 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168802 # number of writebacks +system.cpu.dcache.writebacks::total 168802 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207068 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207068 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908738 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908738 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115806 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205495 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205495 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205495 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205495 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3198491500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3198491500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14240616218 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17439107718 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17439107718 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005819 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005819 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005819 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 91498 # number of replacements -system.cpu.icache.tags.tagsinuse 1915.935564 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13655300 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93546 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.974173 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18815415500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1915.935564 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935515 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935515 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91476 # number of replacements +system.cpu.icache.tags.tagsinuse 1915.700741 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13644579 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93524 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.893878 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18771424500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1915.700741 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935401 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935401 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1476 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1477 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27617236 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27617236 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13655300 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13655300 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13655300 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13655300 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13655300 # number of overall hits -system.cpu.icache.overall_hits::total 13655300 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106545 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106545 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106545 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106545 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106545 # number of overall misses -system.cpu.icache.overall_misses::total 106545 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2015171999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2015171999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2015171999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2015171999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2015171999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13761845 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13761845 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13761845 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13761845 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13761845 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007742 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 133079 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30599.466713 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 282960 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 165171 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.713134 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26451.406117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2221.195572 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1924.780395 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.807233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.067786 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106197.631209 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82604.026846 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82604.026846 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98379.055994 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98379.055994 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82604.026846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104824.585235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 103962.020830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82604.026846 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104824.585235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 103962.020830 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -939,122 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114348 # number of writebacks -system.cpu.l2cache.writebacks::total 114348 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2056 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 2056 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130783 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130783 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 7369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 7369 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7369 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158605 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165974 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7369 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158605 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165974 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12573700500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12573700500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 525566500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 525566500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2477938500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2477938500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 525566500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15051639000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15577205500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 525566500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15051639000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15577205500 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 114413 # number of writebacks +system.cpu.l2cache.writebacks::total 114413 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 112 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130784 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130784 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6407 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6407 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158644 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165051 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6407 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158644 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165051 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12581111000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12581111000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 465184000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 465184000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2462240500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2462240500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 465184000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15043351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15508535500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 465184000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15043351500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15508535500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912022 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078773 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448785 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.078773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96141.704197 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71321.278328 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89063.996118 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.068506 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448624 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.551973 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.068506 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772009 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.551973 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 591735 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 292795 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 591895 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 292875 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4025 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4025 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4047 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 93547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61994 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612083 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 890674 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5986944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23947584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132064 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.074364 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 155625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283215 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 91476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 51263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 93525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612389 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11840000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23955008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35795008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133079 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 432099 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009366 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.096323 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 719774 99.44% 99.44% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4025 0.56% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428052 99.06% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4047 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140327982 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432099 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 556225500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 140299972 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308097983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308258967 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35190 # Transaction distribution -system.membus.trans_dist::Writeback 114348 # Transaction distribution -system.membus.trans_dist::CleanEvict 15746 # Transaction distribution -system.membus.trans_dist::ReadExReq 130783 # Transaction distribution -system.membus.trans_dist::ReadExResp 130783 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35190 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462040 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34266 # Transaction distribution +system.membus.trans_dist::WritebackDirty 114413 # Transaction distribution +system.membus.trans_dist::CleanEvict 14730 # Transaction distribution +system.membus.trans_dist::ReadExReq 130784 # Transaction distribution +system.membus.trans_dist::ReadExResp 130784 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34266 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 459243 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17885632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17885632 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296067 # Request fanout histogram +system.membus.snoop_fanout::samples 294193 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296067 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294193 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296067 # Request fanout histogram -system.membus.reqLayer0.occupancy 778875000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294193 # Request fanout histogram +system.membus.reqLayer0.occupancy 777045500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 857731250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 852834000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 67f744153..c1732fe78 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056991 # Number of seconds simulated -sim_ticks 56991022500 # Number of ticks simulated -final_tick 56991022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056961 # Number of seconds simulated +sim_ticks 56960656500 # Number of ticks simulated +final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186679 # Simulator instruction rate (inst/s) -host_op_rate 238735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150024942 # Simulator tick rate (ticks/s) -host_mem_usage 325676 # Number of bytes of host memory used -host_seconds 379.88 # Real time elapsed on the host +host_inst_rate 199606 # Simulator instruction rate (inst/s) +host_op_rate 255266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 160327771 # Simulator tick rate (ticks/s) +host_mem_usage 325784 # Number of bytes of host memory used +host_seconds 355.28 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory -system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory -system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5592460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139037758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144630218 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5592460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5592460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96752923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96752923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96752923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5592460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139037758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241383141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128791 # Number of read requests accepted -system.physmem.writeReqs 86157 # Number of write requests accepted -system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5512640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory +system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory +system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128278 # Number of read requests accepted +system.physmem.writeReqs 86211 # Number of write requests accepted +system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8144 # Per bank write bursts -system.physmem.perBankRdBursts::1 8370 # Per bank write bursts -system.physmem.perBankRdBursts::2 8248 # Per bank write bursts -system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8315 # Per bank write bursts -system.physmem.perBankRdBursts::5 8436 # Per bank write bursts -system.physmem.perBankRdBursts::6 8084 # Per bank write bursts -system.physmem.perBankRdBursts::7 7955 # Per bank write bursts -system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7629 # Per bank write bursts -system.physmem.perBankRdBursts::10 7815 # Per bank write bursts -system.physmem.perBankRdBursts::11 7829 # Per bank write bursts -system.physmem.perBankRdBursts::12 7881 # Per bank write bursts -system.physmem.perBankRdBursts::13 7878 # Per bank write bursts -system.physmem.perBankRdBursts::14 7975 # Per bank write bursts -system.physmem.perBankRdBursts::15 7995 # Per bank write bursts -system.physmem.perBankWrBursts::0 5393 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8061 # Per bank write bursts +system.physmem.perBankRdBursts::1 8314 # Per bank write bursts +system.physmem.perBankRdBursts::2 8233 # Per bank write bursts +system.physmem.perBankRdBursts::3 8140 # Per bank write bursts +system.physmem.perBankRdBursts::4 8284 # Per bank write bursts +system.physmem.perBankRdBursts::5 8402 # Per bank write bursts +system.physmem.perBankRdBursts::6 8056 # Per bank write bursts +system.physmem.perBankRdBursts::7 7915 # Per bank write bursts +system.physmem.perBankRdBursts::8 8035 # Per bank write bursts +system.physmem.perBankRdBursts::9 7586 # Per bank write bursts +system.physmem.perBankRdBursts::10 7763 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7871 # Per bank write bursts +system.physmem.perBankRdBursts::13 7867 # Per bank write bursts +system.physmem.perBankRdBursts::14 7968 # Per bank write bursts +system.physmem.perBankRdBursts::15 7962 # Per bank write bursts +system.physmem.perBankWrBursts::0 5394 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5464 # Per bank write bursts -system.physmem.perBankWrBursts::3 5326 # Per bank write bursts -system.physmem.perBankWrBursts::4 5352 # Per bank write bursts -system.physmem.perBankWrBursts::5 5547 # Per bank write bursts -system.physmem.perBankWrBursts::6 5252 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts +system.physmem.perBankWrBursts::2 5465 # Per bank write bursts +system.physmem.perBankWrBursts::3 5335 # Per bank write bursts +system.physmem.perBankWrBursts::4 5367 # Per bank write bursts +system.physmem.perBankWrBursts::5 5560 # Per bank write bursts +system.physmem.perBankWrBursts::6 5259 # Per bank write bursts +system.physmem.perBankWrBursts::7 5181 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts @@ -79,27 +79,27 @@ system.physmem.perBankWrBursts::11 5270 # Pe system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56990990500 # Total gap between requests +system.physmem.totGap 56960630500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128791 # Read request sizes (log2) +system.physmem.readPktSize::6 128278 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86211 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.683203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.343519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.125731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12148 31.42% 31.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8177 21.15% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4090 10.58% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2852 7.38% 70.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2693 6.97% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1623 4.20% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1296 3.35% 85.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1161 3.00% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4622 11.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.322124 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.056892 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273380 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256688 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.768255 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4654 87.93% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 4 0.08% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 500 9.45% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 109 2.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 18 0.34% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.09% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads -system.physmem.totQLat 1683428000 # Total ticks spent queuing -system.physmem.totMemAccLat 4098128000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13071.72 # Average queueing delay per DRAM burst +system.physmem.totQLat 1678352000 # Total ticks spent queuing +system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31821.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.62 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing -system.physmem.readRowHits 112096 # Number of row buffer hits during reads -system.physmem.writeRowHits 64153 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.46 # Row buffer hit rate for writes -system.physmem.avgGap 265138.50 # Average gap between requests -system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151963560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82916625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512397600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 278957520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11726025750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23906742000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40381153695 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.591931 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39643767750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1902940000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 111810 # Number of row buffer hits during reads +system.physmem.writeRowHits 63793 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 265564.34 # Average gap between requests +system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.261877 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15441187500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140313600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76560000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491751000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3722150640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11059172775 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24491665500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40260752475 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.479908 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40617302250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1902940000 # Time in different power states +system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.217322 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14467595250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800541 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905717 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381681 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9438549 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732145 # Number of BTB hits +system.cpu.branchPred.lookups 14800638 # Number of BP lookups +system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.326059 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714124 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,67 +404,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113982045 # number of cpu cycles simulated +system.cpu.numCycles 113921313 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144890 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.607302 # CPI: cycles per instruction -system.cpu.ipc 0.622161 # IPC: instructions per cycle -system.cpu.tickCycles 95587829 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18394216 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156435 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.142814 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624094 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.519395 # Average number of references to valid blocks. +system.cpu.cpi 1.606446 # CPI: cycles per instruction +system.cpu.ipc 0.622492 # IPC: instructions per cycle +system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156436 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.142814 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1110 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016729 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83415 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83415 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42508841 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42508841 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592256 # number of overall hits -system.cpu.dcache.overall_hits::total 42592256 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51701 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51701 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207714 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207714 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 304005 # number of overall misses -system.cpu.dcache.overall_misses::total 304005 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1492164500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1492164500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16804934500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16804934500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18297099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18297099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18297099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18297099000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits +system.cpu.dcache.overall_hits::total 42592421 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses +system.cpu.dcache.overall_misses::total 303842 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) @@ -473,28 +473,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768256 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768256 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896261 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896261 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002256 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002256 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348346 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348346 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28861.424344 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28861.424344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80904.197599 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80904.197599 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70532.155041 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70532.155041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60186.835743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60186.835743 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,36 +503,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks -system.cpu.dcache.writebacks::total 128400 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100686 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100686 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122869 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122869 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122869 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122869 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks +system.cpu.dcache.writebacks::total 128377 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 578376000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8484284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8484284000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1716349500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1716349500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9062660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9062660000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779009500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10779009500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -543,70 +543,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19594.010434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19594.010434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79271.629854 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79271.629854 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71559.287054 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71559.287054 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66370.746855 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66370.746855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67145.968691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67145.968691 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42866 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.547846 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941084 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.381758 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42868 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.547846 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904564 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904564 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50016894 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50016894 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941084 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941084 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941084 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941084 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941084 # number of overall hits -system.cpu.icache.overall_hits::total 24941084 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44909 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44909 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44909 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44909 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44909 # number of overall misses -system.cpu.icache.overall_misses::total 44909 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 929470000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 929470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 929470000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 929470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 929470000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 929470000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24985993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24985993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24985993 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24985993 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24985993 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24985993 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits +system.cpu.icache.overall_hits::total 24941232 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses +system.cpu.icache.overall_misses::total 44911 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20696.742301 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20696.742301 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20696.742301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20696.742301 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20696.742301 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,132 +752,133 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 86157 # number of writebacks -system.cpu.l2cache.writebacks::total 86157 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 10 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 10 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 65 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.writebacks::writebacks 86211 # number of writebacks +system.cpu.l2cache.writebacks::total 86211 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1374 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1374 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4981 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4981 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7251042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7251042000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 343845500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 343845500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1655136500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1655136500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 343845500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8906178500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9250024000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 343845500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8906178500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9250024000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110913 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.626908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110913 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.626908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70896.808635 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70896.808635 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69031.419394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69031.419394 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76857.975389 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76857.975389 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69031.419394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71933.660983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71821.417479 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 404741 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 199337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 98411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 72584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44909 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129104 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21365696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95654 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 500395 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.038076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.191682 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96386 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 481371 96.20% 96.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18995 3.80% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 500395 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 330770500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67369485 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240829933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26515 # Transaction distribution -system.membus.trans_dist::Writeback 86157 # Transaction distribution -system.membus.trans_dist::CleanEvict 7510 # Transaction distribution -system.membus.trans_dist::ReadExReq 102276 # Transaction distribution -system.membus.trans_dist::ReadExResp 102276 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 351249 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13756672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13756672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 26001 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution +system.membus.trans_dist::CleanEvict 6908 # Transaction distribution +system.membus.trans_dist::ReadExReq 102277 # Transaction distribution +system.membus.trans_dist::ReadExResp 102277 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 222458 # Request fanout histogram +system.membus.snoop_fanout::samples 221397 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222458 # Request fanout histogram -system.membus.reqLayer0.occupancy 591531500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 221397 # Request fanout histogram +system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 679686000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 4fc60452d..6b580b547 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033346 # Number of seconds simulated -sim_ticks 33346420000 # Number of ticks simulated -final_tick 33346420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033788 # Number of seconds simulated +sim_ticks 33787619000 # Number of ticks simulated +final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116263 # Simulator instruction rate (inst/s) -host_op_rate 148687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54676178 # Simulator tick rate (ticks/s) -host_mem_usage 326572 # Number of bytes of host memory used -host_seconds 609.89 # Real time elapsed on the host +host_inst_rate 117892 # Simulator instruction rate (inst/s) +host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56175899 # Simulator tick rate (ticks/s) +host_mem_usage 326928 # Number of bytes of host memory used +host_seconds 601.46 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 581760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2519040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6191552 # Number of bytes read from this memory -system.physmem.bytes_read::total 9292352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 581760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6257152 # Number of bytes written to this memory -system.physmem.bytes_written::total 6257152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9090 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96743 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145193 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97768 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97768 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17445951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75541542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 185673665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278661158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17445951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187640892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187640892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17445951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75541542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 185673665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466302050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145193 # Number of read requests accepted -system.physmem.writeReqs 97768 # Number of write requests accepted -system.physmem.readBursts 145193 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97768 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9285376 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 6255360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9292352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6257152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9137 # Per bank write bursts -system.physmem.perBankRdBursts::1 9395 # Per bank write bursts -system.physmem.perBankRdBursts::2 9161 # Per bank write bursts -system.physmem.perBankRdBursts::3 9548 # Per bank write bursts -system.physmem.perBankRdBursts::4 9715 # Per bank write bursts -system.physmem.perBankRdBursts::5 9765 # Per bank write bursts -system.physmem.perBankRdBursts::6 9098 # Per bank write bursts -system.physmem.perBankRdBursts::7 9032 # Per bank write bursts -system.physmem.perBankRdBursts::8 9205 # Per bank write bursts -system.physmem.perBankRdBursts::9 8593 # Per bank write bursts -system.physmem.perBankRdBursts::10 8826 # Per bank write bursts -system.physmem.perBankRdBursts::11 8653 # Per bank write bursts -system.physmem.perBankRdBursts::12 8623 # Per bank write bursts -system.physmem.perBankRdBursts::13 8667 # Per bank write bursts -system.physmem.perBankRdBursts::14 8699 # Per bank write bursts -system.physmem.perBankRdBursts::15 8967 # Per bank write bursts -system.physmem.perBankWrBursts::0 5976 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6094 # Per bank write bursts -system.physmem.perBankWrBursts::3 6205 # Per bank write bursts -system.physmem.perBankWrBursts::4 6124 # Per bank write bursts -system.physmem.perBankWrBursts::5 6340 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6041 # Per bank write bursts -system.physmem.perBankWrBursts::8 6001 # Per bank write bursts -system.physmem.perBankWrBursts::9 6103 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory +system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory +system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152624 # Number of read requests accepted +system.physmem.writeReqs 97338 # Number of write requests accepted +system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9027 # Per bank write bursts +system.physmem.perBankRdBursts::1 9355 # Per bank write bursts +system.physmem.perBankRdBursts::2 9548 # Per bank write bursts +system.physmem.perBankRdBursts::3 12185 # Per bank write bursts +system.physmem.perBankRdBursts::4 10599 # Per bank write bursts +system.physmem.perBankRdBursts::5 10432 # Per bank write bursts +system.physmem.perBankRdBursts::6 9787 # Per bank write bursts +system.physmem.perBankRdBursts::7 9285 # Per bank write bursts +system.physmem.perBankRdBursts::8 9499 # Per bank write bursts +system.physmem.perBankRdBursts::9 9569 # Per bank write bursts +system.physmem.perBankRdBursts::10 9134 # Per bank write bursts +system.physmem.perBankRdBursts::11 8776 # Per bank write bursts +system.physmem.perBankRdBursts::12 8706 # Per bank write bursts +system.physmem.perBankRdBursts::13 8772 # Per bank write bursts +system.physmem.perBankRdBursts::14 8686 # Per bank write bursts +system.physmem.perBankRdBursts::15 9110 # Per bank write bursts +system.physmem.perBankWrBursts::0 5979 # Per bank write bursts +system.physmem.perBankWrBursts::1 6226 # Per bank write bursts +system.physmem.perBankWrBursts::2 6146 # Per bank write bursts +system.physmem.perBankWrBursts::3 6158 # Per bank write bursts +system.physmem.perBankWrBursts::4 6081 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6021 # Per bank write bursts +system.physmem.perBankWrBursts::7 5966 # Per bank write bursts +system.physmem.perBankWrBursts::8 5954 # Per bank write bursts +system.physmem.perBankWrBursts::9 6102 # Per bank write bursts system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5916 # Per bank write bursts -system.physmem.perBankWrBursts::12 6074 # Per bank write bursts -system.physmem.perBankWrBursts::13 6102 # Per bank write bursts -system.physmem.perBankWrBursts::14 6204 # Per bank write bursts -system.physmem.perBankWrBursts::15 6028 # Per bank write bursts +system.physmem.perBankWrBursts::11 5872 # Per bank write bursts +system.physmem.perBankWrBursts::12 6030 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 6151 # Per bank write bursts +system.physmem.perBankWrBursts::15 5988 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33346162500 # Total gap between requests +system.physmem.totGap 33787609500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145193 # Read request sizes (log2) +system.physmem.readPktSize::6 152624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97768 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97338 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.437436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.610569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.212794 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52129 58.86% 58.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22374 25.26% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4601 5.19% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1696 1.91% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1069 1.21% 92.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 812 0.92% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 692 0.78% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 790 0.89% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4403 4.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5908 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.550271 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.061813 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.955752 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5907 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5908 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5908 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.543670 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.503041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.228970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4711 79.74% 79.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 80.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 768 13.00% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.76% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 108 1.83% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 1.03% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 38 0.64% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.17% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5908 # Writes before turning the bus around for reads -system.physmem.totQLat 7011292666 # Total ticks spent queuing -system.physmem.totMemAccLat 9731617666 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 725420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 48325.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads +system.physmem.totQLat 6712073801 # Total ticks spent queuing +system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 67075.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.64 # Data bus utilization in percentage -system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.62 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.60 # Average write queue length when enqueuing -system.physmem.readRowHits 118088 # Number of row buffer hits during reads -system.physmem.writeRowHits 36158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.98 # Row buffer hit rate for writes -system.physmem.avgGap 137249.03 # Average gap between requests -system.physmem.pageHitRate 63.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342241200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186738750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583385400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317818080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11790659475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9661917750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25060414575 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.639504 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15978647517 # Time in different power states -system.physmem_0.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem.busUtil 3.70 # Data bus utilization in percentage +system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 121004 # Number of row buffer hits during reads +system.physmem.writeRowHits 33280 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes +system.physmem.avgGap 135170.98 # Average gap between requests +system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) +system.physmem_0.averagePower 766.158096 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states +system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16249048233 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 326909520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178373250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 547528800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315329760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2177653920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11234568330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10149705000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24930068580 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.730472 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16793127980 # Time in different power states -system.physmem_1.memoryStateTime::REF 1113320000 # Time in different power states +system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) +system.physmem_1.averagePower 756.923807 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states +system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15434548270 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17208509 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519539 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648302 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9342884 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675123 # Number of BTB hits +system.cpu.branchPred.lookups 17216173 # Number of BP lookups +system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.149398 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872388 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,95 +412,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66692841 # number of cpu cycles simulated +system.cpu.numCycles 67575239 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5046776 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88195647 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17208509 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9547511 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60140641 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322595 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6428 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13633 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763338 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69414 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.694437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296898 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20089005 30.50% 30.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265359 12.55% 43.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9198123 13.96% 57.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316313 42.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65868800 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258026 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8616725 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19555814 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5627882 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492094 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179727 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171045 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101400911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3043244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13372904 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5353130 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 801467 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13616322 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99196979 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981006 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3848899 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63135 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4311075 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5311261 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103921430 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457681852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115406862 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10292204 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12699652 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320213 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21993792 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1400092 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2341142 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98161647 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34523 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94891012 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 695609 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7513585 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20245943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65868800 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.440606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.149928 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17598833 26.72% 26.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17429188 26.46% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17113322 25.98% 79.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11675618 17.73% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050869 3.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 970 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65868800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6712111 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available @@ -527,13 +528,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11183885 37.33% 59.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12062879 40.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494737 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89878 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -554,91 +555,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24064392 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21241967 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94891012 # Type of FU issued -system.cpu.iq.rate 1.422807 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29958914 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315719 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286305140 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105721004 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93462242 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124849808 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363438 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued +system.cpu.iq.rate 1.404542 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453951 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2082 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11760 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438054 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 138729 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 184462 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 624554 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 468032 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98206039 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320213 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21993792 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18603 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1634 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 463552 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11760 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302690 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221650 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524340 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93974044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23757485 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916968 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9869 # number of nop insts executed -system.cpu.iew.exec_refs 44742217 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251815 # Number of branches executed -system.cpu.iew.exec_stores 20984732 # Number of stores executed -system.cpu.iew.exec_rate 1.409057 # Inst execution rate -system.cpu.iew.wb_sent 93584291 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93462299 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44972986 # num instructions producing a value -system.cpu.iew.wb_consumers 76550519 # num instructions consuming a value +system.cpu.iew.exec_nop 9890 # number of nop insts executed +system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed +system.cpu.iew.exec_branches 14253415 # Number of branches executed +system.cpu.iew.exec_stores 20991444 # Number of stores executed +system.cpu.iew.exec_rate 1.390923 # Inst execution rate +system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44975266 # num instructions producing a value +system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.401384 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587494 # average fanout of values written-back +system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6533064 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479099 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64811353 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.399263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.164401 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31214732 48.16% 48.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16807105 25.93% 74.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4339311 6.70% 80.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161583 6.42% 87.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1937068 2.99% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1261836 1.95% 92.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 738743 1.14% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580049 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3770926 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64811353 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,386 +685,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3770926 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158236329 # The number of ROB reads -system.cpu.rob.rob_writes 195501562 # The number of ROB writes -system.cpu.timesIdled 24613 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 824041 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158912055 # The number of ROB reads +system.cpu.rob.rob_writes 195546008 # The number of ROB writes +system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940559 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940559 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063197 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063197 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102271310 # number of integer regfile reads -system.cpu.int_regfile_writes 56791274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36 # number of floating regfile reads -system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346086877 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805113 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208470 # number of misc regfile reads +system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102290506 # number of integer regfile reads +system.cpu.int_regfile_writes 56802248 # number of integer regfile writes +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.fp_regfile_writes 24 # number of floating regfile writes +system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes +system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485016 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.742621 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40419295 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248124 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152905500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.742621 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997544 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997544 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485017 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84611982 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84611982 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21497006 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21497006 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830802 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830802 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60196 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60196 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15349 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15349 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40327808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40327808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40388004 # number of overall hits -system.cpu.dcache.overall_hits::total 40388004 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 555640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 555640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019099 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68639 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68639 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits +system.cpu.dcache.overall_hits::total 40381259 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1574739 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1574739 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1643378 # number of overall misses -system.cpu.dcache.overall_misses::total 1643378 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9002363000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14580629410 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5329000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23582992410 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23582992410 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23582992410 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22052646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22052646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses +system.cpu.dcache.overall_misses::total 1652083 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128835 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41902547 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41902547 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42031382 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42031382 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025196 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051340 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532767 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036230 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039099 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039099 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16201.790728 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16201.790728 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14307.372895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14307.372895 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9235.701906 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14975.810220 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14975.810220 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14350.315271 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14350.315271 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3096615 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130248 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.774760 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 253749 # number of writebacks -system.cpu.dcache.writebacks::total 253749 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256216 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 256216 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870580 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870580 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks +system.cpu.dcache.writebacks::total 485017 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1126796 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1126796 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1126796 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299424 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299424 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148519 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148519 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485538 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485538 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3220458500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2349684961 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2014368500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5570143461 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7584511961 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013578 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447942 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485539 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485539 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3625766000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2305447971 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10755.512250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.770144 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53580.755420 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12434.938064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12434.938064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15620.841131 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15620.841131 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322602 # number of replacements -system.cpu.icache.tags.tagsinuse 510.289801 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22429330 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323114 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.416150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1108313500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.289801 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996660 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996660 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 323105 # number of replacements +system.cpu.icache.tags.tagsinuse 510.281102 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22444187 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323617 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 350 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45849556 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45849556 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22429330 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22429330 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22429330 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22429330 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22429330 # number of overall hits -system.cpu.icache.overall_hits::total 22429330 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 333886 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 333886 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 333886 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 333886 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 333886 # number of overall misses -system.cpu.icache.overall_misses::total 333886 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3387462898 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3387462898 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3387462898 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3387462898 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3387462898 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22763216 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22763216 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22763216 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22763216 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22763216 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10145.567343 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10145.567343 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10145.567343 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10145.567343 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 275055 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45880575 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45880575 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22444187 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22444187 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22444187 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22444187 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22444187 # number of overall hits +system.cpu.icache.overall_hits::total 22444187 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334287 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334287 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334287 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334287 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334287 # number of overall misses +system.cpu.icache.overall_misses::total 334287 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3550514898 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3550514898 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3550514898 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3550514898 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3550514898 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22778474 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22778474 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22778474 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22778474 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22778474 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014676 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014676 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10621.157562 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16465 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16440 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.705436 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.901277 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10762 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 10762 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 10762 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 10762 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 10762 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323124 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323124 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323124 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323124 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323124 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3106237439 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3106237439 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3106237439 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014195 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014195 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014195 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9613.143682 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9613.143682 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9613.143682 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 323105 # number of writebacks +system.cpu.icache.writebacks::total 323105 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10659 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10659 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10659 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10659 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10659 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3274041434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3274041434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3274041434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014208 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014208 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014208 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10116.681604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10116.681604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10116.681604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 824554 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825997 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 1265 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 822385 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826178 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3328 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78883 # 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number of writebacks +system.cpu.l2cache.writebacks::total 97338 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3200 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3200 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 27 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 27 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 107 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3307 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3334 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3307 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3334 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112837 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8287 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 11515 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36313 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 56115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11515 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112837 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168952 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10338050198 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 173000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 653811000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 801316000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2775072500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 801316000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3428883500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4230199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 801316000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3428883500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10338050198 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14568249698 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056032 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028133 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.092103 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059915 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028133 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.081066 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.198976 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 94466.292379 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17333.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80754.565113 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71826.512651 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80537.939812 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78940.753354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71826.512651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80583.752541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 94466.292379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89791.262138 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208803 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1616280 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 807659 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 20376 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 20194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 182 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 351517 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 505600 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 141126 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323124 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336969 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2345110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20679232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47313728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 67992960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 270457 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1886726 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.095537 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.294284 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318372 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1706655 90.46% 90.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 179889 9.53% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 182 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1886726 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1061889000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485111148 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728499095 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 136869 # Transaction distribution -system.membus.trans_dist::Writeback 97768 # Transaction distribution -system.membus.trans_dist::CleanEvict 30364 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8324 # Transaction distribution -system.membus.trans_dist::ReadExResp 8324 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 136869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 418530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15549504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15549504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 144336 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution +system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 8287 # Transaction distribution +system.membus.trans_dist::ReadExResp 8287 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 273331 # Request fanout histogram +system.membus.snoop_fanout::samples 277799 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 273331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 273331 # Request fanout histogram -system.membus.reqLayer0.occupancy 739892708 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 277799 # Request fanout histogram +system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 756443702 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 617d9f369..ce3c1254b 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.208801 # Number of seconds simulated -sim_ticks 1208800797500 # Number of ticks simulated -final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.208729 # Number of seconds simulated +sim_ticks 1208728699500 # Number of ticks simulated +final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309355 # Simulator instruction rate (inst/s) -host_op_rate 309355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 204748768 # Simulator tick rate (ticks/s) -host_mem_usage 299532 # Number of bytes of host memory used -host_seconds 5903.82 # Real time elapsed on the host +host_inst_rate 339450 # Simulator instruction rate (inst/s) +host_op_rate 339450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 224654099 # Simulator tick rate (ticks/s) +host_mem_usage 299384 # Number of bytes of host memory used +host_seconds 5380.40 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data 124969728 # Nu system.physmem.bytes_read::total 125030976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65417024 # Number of bytes written to this memory -system.physmem.bytes_written::total 65417024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65416576 # Number of bytes written to this memory +system.physmem.bytes_written::total 65416576 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1952652 # Number of read requests responded to by this memory system.physmem.num_reads::total 1953609 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022141 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022141 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103383228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103433896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50668 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54117291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54117291 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54117291 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103383228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157551187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 1022134 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022134 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103389394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103440066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54120148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54120148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54120148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103389394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157560214 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 1953609 # Number of read requests accepted -system.physmem.writeReqs 1022141 # Number of write requests accepted +system.physmem.writeReqs 1022134 # Number of write requests accepted system.physmem.readBursts 1953609 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022141 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124949504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 81472 # Total number of bytes read from write queue -system.physmem.bytesWritten 65415744 # Total number of bytes written to DRAM +system.physmem.writeBursts 1022134 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124947712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83264 # Total number of bytes read from write queue +system.physmem.bytesWritten 65415296 # Total number of bytes written to DRAM system.physmem.bytesReadSys 125030976 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65417024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1273 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118329 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 897725 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118310 # Per bank write bursts system.physmem.perBankRdBursts::1 113529 # Per bank write bursts -system.physmem.perBankRdBursts::2 115744 # Per bank write bursts -system.physmem.perBankRdBursts::3 117255 # Per bank write bursts +system.physmem.perBankRdBursts::2 115745 # Per bank write bursts +system.physmem.perBankRdBursts::3 117258 # Per bank write bursts system.physmem.perBankRdBursts::4 117308 # Per bank write bursts -system.physmem.perBankRdBursts::5 117125 # Per bank write bursts -system.physmem.perBankRdBursts::6 119396 # Per bank write bursts -system.physmem.perBankRdBursts::7 124121 # Per bank write bursts -system.physmem.perBankRdBursts::8 126643 # Per bank write bursts -system.physmem.perBankRdBursts::9 129581 # Per bank write bursts -system.physmem.perBankRdBursts::10 128162 # Per bank write bursts -system.physmem.perBankRdBursts::11 129917 # Per bank write bursts -system.physmem.perBankRdBursts::12 125585 # Per bank write bursts -system.physmem.perBankRdBursts::13 124851 # Per bank write bursts -system.physmem.perBankRdBursts::14 122145 # Per bank write bursts -system.physmem.perBankRdBursts::15 122645 # Per bank write bursts -system.physmem.perBankWrBursts::0 61422 # Per bank write bursts -system.physmem.perBankWrBursts::1 61663 # Per bank write bursts -system.physmem.perBankWrBursts::2 60725 # Per bank write bursts -system.physmem.perBankWrBursts::3 61394 # Per bank write bursts -system.physmem.perBankWrBursts::4 61815 # Per bank write bursts +system.physmem.perBankRdBursts::5 117123 # Per bank write bursts +system.physmem.perBankRdBursts::6 119399 # Per bank write bursts +system.physmem.perBankRdBursts::7 124116 # Per bank write bursts +system.physmem.perBankRdBursts::8 126646 # Per bank write bursts +system.physmem.perBankRdBursts::9 129571 # Per bank write bursts +system.physmem.perBankRdBursts::10 128166 # Per bank write bursts +system.physmem.perBankRdBursts::11 129914 # Per bank write bursts +system.physmem.perBankRdBursts::12 125584 # Per bank write bursts +system.physmem.perBankRdBursts::13 124843 # Per bank write bursts +system.physmem.perBankRdBursts::14 122159 # Per bank write bursts +system.physmem.perBankRdBursts::15 122637 # Per bank write bursts +system.physmem.perBankWrBursts::0 61419 # Per bank write bursts +system.physmem.perBankWrBursts::1 61661 # Per bank write bursts +system.physmem.perBankWrBursts::2 60723 # Per bank write bursts +system.physmem.perBankWrBursts::3 61396 # Per bank write bursts +system.physmem.perBankWrBursts::4 61819 # Per bank write bursts system.physmem.perBankWrBursts::5 63308 # Per bank write bursts system.physmem.perBankWrBursts::6 64356 # Per bank write bursts system.physmem.perBankWrBursts::7 65855 # Per bank write bursts -system.physmem.perBankWrBursts::8 65579 # Per bank write bursts -system.physmem.perBankWrBursts::9 66031 # Per bank write bursts -system.physmem.perBankWrBursts::10 65643 # Per bank write bursts -system.physmem.perBankWrBursts::11 65948 # Per bank write bursts -system.physmem.perBankWrBursts::12 64510 # Per bank write bursts -system.physmem.perBankWrBursts::13 64527 # Per bank write bursts -system.physmem.perBankWrBursts::14 64896 # Per bank write bursts +system.physmem.perBankWrBursts::8 65578 # Per bank write bursts +system.physmem.perBankWrBursts::9 66028 # Per bank write bursts +system.physmem.perBankWrBursts::10 65644 # Per bank write bursts +system.physmem.perBankWrBursts::11 65946 # Per bank write bursts +system.physmem.perBankWrBursts::12 64498 # Per bank write bursts +system.physmem.perBankWrBursts::13 64533 # Per bank write bursts +system.physmem.perBankWrBursts::14 64901 # Per bank write bursts system.physmem.perBankWrBursts::15 64449 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1208800695000 # Total gap between requests +system.physmem.totGap 1208728583000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -96,9 +96,9 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1830062 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122257 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1022134 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1829960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122331 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1831783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.923052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.128953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.461416 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1453465 79.35% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261783 14.29% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48685 2.66% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20654 1.13% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13128 0.72% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7168 0.39% 98.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5621 0.31% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4509 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16770 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1831783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59616 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.746846 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 147.774131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59455 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 113 0.19% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1831742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.922688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.125561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.468112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1453729 79.36% 79.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261245 14.26% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48901 2.67% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20697 1.13% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13090 0.71% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7260 0.40% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5482 0.30% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4525 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16813 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831742 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59619 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.744729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 150.866534 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59458 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 115 0.19% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1536-2047 8 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 9 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 3 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes @@ -225,103 +225,104 @@ system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59616 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.145079 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.109083 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.114634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27440 46.03% 46.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1214 2.04% 48.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26474 44.41% 92.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3953 6.63% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 450 0.75% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 71 0.12% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59616 # Writes before turning the bus around for reads -system.physmem.totQLat 36544132750 # Total ticks spent queuing -system.physmem.totMemAccLat 73150432750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18718.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59619 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.144098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.107874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.119193 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27514 46.15% 46.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1196 2.01% 48.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26405 44.29% 92.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3955 6.63% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 448 0.75% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 78 0.13% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59619 # Writes before turning the bus around for reads +system.physmem.totQLat 36502723500 # Total ticks spent queuing +system.physmem.totMemAccLat 73108498500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18697.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37468.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37447.22 # Average memory access latency per DRAM burst system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.43 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 723493 # Number of row buffer hits during reads -system.physmem.writeRowHits 419177 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes -system.physmem.avgGap 406217.15 # Average gap between requests +system.physmem.avgWrQLen 24.64 # Average write queue length when enqueuing +system.physmem.readRowHits 723641 # Number of row buffer hits during reads +system.physmem.writeRowHits 419030 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.00 # Row buffer hit rate for writes +system.physmem.avgGap 406193.88 # Average gap between requests system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6716750040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3664893375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353886800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243486240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 415155955455 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 361108109250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 876196004040 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.847786 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 597970225000 # Time in different power states -system.physmem_0.memoryStateTime::REF 40364480000 # Time in different power states +system.physmem_0.actEnergy 6715147320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3664018875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353699600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243479760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414818688735 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361357239750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876100111320 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.815145 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 598389652500 # Time in different power states +system.physmem_0.memoryStateTime::REF 40361880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 570465308750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 569973346500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7131529440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3891211500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379857840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426545221500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351117525000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 878892508560 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.078515 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 581276348750 # Time in different power states -system.physmem_1.memoryStateTime::REF 40364480000 # Time in different power states +system.physmem_1.actEnergy 7132791960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3891900375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7873632000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379818960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78947837280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426678504030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 350953893000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 878858377605 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.097114 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581002634000 # Time in different power states +system.physmem_1.memoryStateTime::REF 40361880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587159309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587357637250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246104681 # Number of BP lookups -system.cpu.branchPred.condPredicted 186361047 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15590665 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167674402 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165200232 # Number of BTB hits +system.cpu.branchPred.lookups 246098302 # Number of BP lookups +system.cpu.branchPred.condPredicted 186353272 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15586995 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167674122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165197435 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.524420 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18413418 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104179 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.522916 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18413853 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104375 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452862393 # DTB read hits -system.cpu.dtb.read_misses 4979628 # DTB read misses +system.cpu.dtb.read_hits 452860961 # DTB read hits +system.cpu.dtb.read_misses 4979889 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457842021 # DTB read accesses -system.cpu.dtb.write_hits 161378642 # DTB write hits -system.cpu.dtb.write_misses 1709394 # DTB write misses +system.cpu.dtb.read_accesses 457840850 # DTB read accesses +system.cpu.dtb.write_hits 161378751 # DTB write hits +system.cpu.dtb.write_misses 1709377 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163088036 # DTB write accesses -system.cpu.dtb.data_hits 614241035 # DTB hits -system.cpu.dtb.data_misses 6689022 # DTB misses +system.cpu.dtb.write_accesses 163088128 # DTB write accesses +system.cpu.dtb.data_hits 614239712 # DTB hits +system.cpu.dtb.data_misses 6689266 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620930057 # DTB accesses -system.cpu.itb.fetch_hits 597998986 # ITB hits +system.cpu.dtb.data_accesses 620928978 # DTB accesses +system.cpu.itb.fetch_hits 597989879 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 597999005 # ITB accesses +system.cpu.itb.fetch_accesses 597989898 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -335,82 +336,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2417601595 # number of cpu cycles simulated +system.cpu.numCycles 2417457399 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 51825441 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 51810559 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.323713 # CPI: cycles per instruction -system.cpu.ipc 0.755451 # IPC: instructions per cycle -system.cpu.tickCycles 2075284528 # Number of cycles that the object actually ticked -system.cpu.idleCycles 342317067 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121986 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.726688 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601540360 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126082 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.914415 # Average number of references to valid blocks. +system.cpu.cpi 1.323634 # CPI: cycles per instruction +system.cpu.ipc 0.755496 # IPC: instructions per cycle +system.cpu.tickCycles 2075240271 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342217128 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121937 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.725777 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601539424 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126033 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.914667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.725777 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1547 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2403 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231278878 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231278878 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443058336 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443058336 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482024 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482024 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601540360 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601540360 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601540360 # number of overall hits -system.cpu.dcache.overall_hits::total 601540360 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289560 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289560 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246478 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9536038 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9536038 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9536038 # number of overall misses -system.cpu.dcache.overall_misses::total 9536038 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 185462944500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 185462944500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108451503000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108451503000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 293914447500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 293914447500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 293914447500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 293914447500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450347896 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450347896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231276891 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231276891 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443057425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443057425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158481999 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158481999 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601539424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601539424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601539424 # number of overall hits +system.cpu.dcache.overall_hits::total 601539424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289502 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289502 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246503 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246503 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536005 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536005 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536005 # number of overall misses +system.cpu.dcache.overall_misses::total 9536005 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185435901500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108411798000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293847699500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293847699500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293847699500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293847699500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450346927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450346927 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611076398 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611076398 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611076398 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611076398 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 611075429 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611075429 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611075429 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611075429 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016186 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25442.268738 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25442.268738 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48276.236402 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48276.236402 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30821.442563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30821.442563 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30814.549646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30814.549646 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,32 +420,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3686591 # number of writebacks -system.cpu.dcache.writebacks::total 3686591 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50801 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50801 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359155 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 359155 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 409956 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 409956 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 409956 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 409956 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238759 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238759 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126082 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126082 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126082 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126082 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176998396500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176998396500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83275965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83275965000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260274361500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260274361500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260274361500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260274361500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3686592 # number of writebacks +system.cpu.dcache.writebacks::total 3686592 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50797 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50797 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359175 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359175 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409972 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409972 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409972 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409972 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238705 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238705 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887328 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887328 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126033 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126033 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126033 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126033 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83260117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83260117500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260233934000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260233934000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -453,66 +454,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24451.483535 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24451.483535 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44123.854263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44123.854263 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 749.172343 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 597998029 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 749.290154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 597988922 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624867.323929 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 624857.807732 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 749.172343 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.365807 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.365807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 749.290154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.365864 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.365864 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1195998929 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1195998929 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 597998029 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 597998029 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 597998029 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 597998029 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 597998029 # number of overall hits -system.cpu.icache.overall_hits::total 597998029 # number of overall hits +system.cpu.icache.tags.tag_accesses 1195980715 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1195980715 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 597988922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 597988922 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 597988922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 597988922 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 597988922 # number of overall hits +system.cpu.icache.overall_hits::total 597988922 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses system.cpu.icache.overall_misses::total 957 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 77181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 77181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 77181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 77181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 77181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 77181000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 597998986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 597998986 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 597998986 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 597998986 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 597998986 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 597998986 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 76621000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 76621000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 76621000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 76621000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 76621000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 76621000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 597989879 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 597989879 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 597989879 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 597989879 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 597989879 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 597989879 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80648.902821 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80648.902821 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80648.902821 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80648.902821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80648.902821 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80648.902821 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80063.740857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80063.740857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -521,125 +522,131 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 3 # number of writebacks +system.cpu.icache.writebacks::total 3 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76224000 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75664000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79648.902821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79648.902821 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79648.902821 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79648.902821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79648.902821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79648.902821 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1920882 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.193345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.451609 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001304 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.485968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.781155 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.451615 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001306 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.485958 # 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Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149830233 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149830233 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3686591 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3686591 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1106811 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1106811 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6066619 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6066619 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7173430 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7173430 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7173430 # number of overall hits -system.cpu.l2cache.overall_hits::total 7173430 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60948826000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65216500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65216500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90691390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90691390500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65216500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151640216500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 151705433000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65216500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151640216500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 151705433000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60931169500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60931169500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64657500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64657500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90667791500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90667791500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64657500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151598961000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 151663618500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64657500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151598961000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 151663618500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413555 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413555 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413552 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413552 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161926 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161926 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161927 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161927 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214046 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214047 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214046 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78088.262576 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78088.262576 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68146.812957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68146.812957 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77372.490061 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77372.490061 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213965 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214047 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18249028 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121989 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18248930 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121940 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1267 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1267 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1268 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1268 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239662 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4708726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6334096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887328 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238705 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1917 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374150 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376067 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007925 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374003 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27375920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820008000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820069440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920885 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11047875 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010713 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20168643 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1267 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11046607 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1268 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11047875 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811060000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1435500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689049500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1173097 # Transaction distribution -system.membus.trans_dist::Writeback 1022141 # Transaction distribution -system.membus.trans_dist::CleanEvict 897719 # Transaction distribution -system.membus.trans_dist::ReadExReq 780512 # Transaction distribution -system.membus.trans_dist::ReadExResp 780512 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173097 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827078 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827078 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190448000 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1173100 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022134 # Transaction distribution +system.membus.trans_dist::CleanEvict 897725 # Transaction distribution +system.membus.trans_dist::ReadExReq 780509 # Transaction distribution +system.membus.trans_dist::ReadExResp 780509 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173100 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827077 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190447552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190447552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3873469 # Request fanout histogram +system.membus.snoop_fanout::samples 3873468 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873469 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873468 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873469 # Request fanout histogram -system.membus.reqLayer0.occupancy 8428000500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3873468 # Request fanout histogram +system.membus.reqLayer0.occupancy 8428126500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10685481750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10685578000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index bb4922b1c..5a6b26759 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.669557 # Number of seconds simulated -sim_ticks 669556582000 # Number of ticks simulated -final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.669525 # Number of seconds simulated +sim_ticks 669525393000 # Number of ticks simulated +final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160543 # Simulator instruction rate (inst/s) -host_op_rate 160543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61918292 # Simulator tick rate (ticks/s) -host_mem_usage 299292 # Number of bytes of host memory used -host_seconds 10813.55 # Real time elapsed on the host +host_inst_rate 166227 # Simulator instruction rate (inst/s) +host_op_rate 166227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64107392 # Simulator tick rate (ticks/s) +host_mem_usage 299384 # Number of bytes of host memory used +host_seconds 10443.81 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125490304 # Number of bytes read from this memory -system.physmem.bytes_read::total 125551168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65555584 # Number of bytes written to this memory -system.physmem.bytes_written::total 65555584 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960786 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961737 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024306 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024306 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 90902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 187423001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 187513903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 90902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90902 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97908953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97908953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97908953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 90902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 187423001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 285422856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961737 # Number of read requests accepted -system.physmem.writeReqs 1024306 # Number of write requests accepted -system.physmem.readBursts 1961737 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024306 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125467392 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue -system.physmem.bytesWritten 65553984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125551168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65555584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 60992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125490432 # Number of bytes read from this memory +system.physmem.bytes_read::total 125551424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65555904 # Number of bytes written to this memory +system.physmem.bytes_written::total 65555904 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960788 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961741 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024311 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024311 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 91097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187431923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187523021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97913992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97913992 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97913992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187431923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 285437013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961741 # Number of read requests accepted +system.physmem.writeReqs 1024311 # Number of write requests accepted +system.physmem.readBursts 1961741 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024311 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125468352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83072 # Total number of bytes read from write queue +system.physmem.bytesWritten 65554688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125551424 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118679 # Per bank write bursts -system.physmem.perBankRdBursts::1 113901 # Per bank write bursts -system.physmem.perBankRdBursts::2 116111 # Per bank write bursts -system.physmem.perBankRdBursts::3 117641 # Per bank write bursts -system.physmem.perBankRdBursts::4 117753 # Per bank write bursts -system.physmem.perBankRdBursts::5 117515 # Per bank write bursts -system.physmem.perBankRdBursts::6 119854 # Per bank write bursts -system.physmem.perBankRdBursts::7 124644 # Per bank write bursts -system.physmem.perBankRdBursts::8 127345 # Per bank write bursts -system.physmem.perBankRdBursts::9 130108 # Per bank write bursts -system.physmem.perBankRdBursts::10 128796 # Per bank write bursts -system.physmem.perBankRdBursts::11 130507 # Per bank write bursts -system.physmem.perBankRdBursts::12 126297 # Per bank write bursts -system.physmem.perBankRdBursts::13 125432 # Per bank write bursts -system.physmem.perBankRdBursts::14 122623 # Per bank write bursts -system.physmem.perBankRdBursts::15 123222 # Per bank write bursts -system.physmem.perBankWrBursts::0 61508 # Per bank write bursts -system.physmem.perBankWrBursts::1 61766 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 118677 # Per bank write bursts +system.physmem.perBankRdBursts::1 113900 # Per bank write bursts +system.physmem.perBankRdBursts::2 116118 # Per bank write bursts +system.physmem.perBankRdBursts::3 117645 # Per bank write bursts +system.physmem.perBankRdBursts::4 117762 # Per bank write bursts +system.physmem.perBankRdBursts::5 117513 # Per bank write bursts +system.physmem.perBankRdBursts::6 119856 # Per bank write bursts +system.physmem.perBankRdBursts::7 124646 # Per bank write bursts +system.physmem.perBankRdBursts::8 127338 # Per bank write bursts +system.physmem.perBankRdBursts::9 130111 # Per bank write bursts +system.physmem.perBankRdBursts::10 128791 # Per bank write bursts +system.physmem.perBankRdBursts::11 130502 # Per bank write bursts +system.physmem.perBankRdBursts::12 126296 # Per bank write bursts +system.physmem.perBankRdBursts::13 125424 # Per bank write bursts +system.physmem.perBankRdBursts::14 122633 # Per bank write bursts +system.physmem.perBankRdBursts::15 123231 # Per bank write bursts +system.physmem.perBankWrBursts::0 61509 # Per bank write bursts +system.physmem.perBankWrBursts::1 61765 # Per bank write bursts system.physmem.perBankWrBursts::2 60825 # Per bank write bursts -system.physmem.perBankWrBursts::3 61511 # Per bank write bursts -system.physmem.perBankWrBursts::4 61967 # Per bank write bursts -system.physmem.perBankWrBursts::5 63434 # Per bank write bursts +system.physmem.perBankWrBursts::3 61513 # Per bank write bursts +system.physmem.perBankWrBursts::4 61969 # Per bank write bursts +system.physmem.perBankWrBursts::5 63433 # Per bank write bursts system.physmem.perBankWrBursts::6 64481 # Per bank write bursts -system.physmem.perBankWrBursts::7 65996 # Per bank write bursts +system.physmem.perBankWrBursts::7 65997 # Per bank write bursts system.physmem.perBankWrBursts::8 65770 # Per bank write bursts -system.physmem.perBankWrBursts::9 66159 # Per bank write bursts +system.physmem.perBankWrBursts::9 66158 # Per bank write bursts system.physmem.perBankWrBursts::10 65809 # Per bank write bursts -system.physmem.perBankWrBursts::11 66083 # Per bank write bursts -system.physmem.perBankWrBursts::12 64701 # Per bank write bursts -system.physmem.perBankWrBursts::13 64659 # Per bank write bursts -system.physmem.perBankWrBursts::14 65023 # Per bank write bursts -system.physmem.perBankWrBursts::15 64589 # Per bank write bursts +system.physmem.perBankWrBursts::11 66082 # Per bank write bursts +system.physmem.perBankWrBursts::12 64703 # Per bank write bursts +system.physmem.perBankWrBursts::13 64664 # Per bank write bursts +system.physmem.perBankWrBursts::14 65021 # Per bank write bursts +system.physmem.perBankWrBursts::15 64593 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 669556486500 # Total gap between requests +system.physmem.totGap 669525297500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961737 # Read request sizes (log2) +system.physmem.readPktSize::6 1961741 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024306 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1024311 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 61428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,149 +193,148 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.945804 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.951779 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.536097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1374979 77.70% 77.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 270914 15.31% 93.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53662 3.03% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21295 1.20% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12785 0.72% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6489 0.37% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4949 0.28% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3948 0.22% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20571 1.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769592 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60107 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.574625 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 148.683386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59945 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 118 0.20% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1769975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.923423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.935475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.553027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1375598 77.72% 77.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270762 15.30% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53515 3.02% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21283 1.20% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12968 0.73% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6460 0.36% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4828 0.27% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3885 0.22% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20676 1.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60095 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.621932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 151.728866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59931 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 120 0.20% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 12 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-8703 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-9727 2 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60107 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60107 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.040960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.998792 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.235687 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31915 53.10% 53.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1364 2.27% 55.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21027 34.98% 90.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4732 7.87% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 816 1.36% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 161 0.27% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 44 0.07% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 14 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60095 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60095 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044546 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.002519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.231700 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31758 52.85% 52.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1379 2.29% 55.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21272 35.40% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4591 7.64% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 816 1.36% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 185 0.31% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 43 0.07% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60107 # Writes before turning the bus around for reads -system.physmem.totQLat 40555708000 # Total ticks spent queuing -system.physmem.totMemAccLat 77313733000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9802140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20687.17 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60095 # Writes before turning the bus around for reads +system.physmem.totQLat 40550197000 # Total ticks spent queuing +system.physmem.totMemAccLat 77308503250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9802215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20684.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39437.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 187.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 39434.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 97.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 187.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 97.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.23 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing -system.physmem.readRowHits 792895 # Number of row buffer hits during reads -system.physmem.writeRowHits 422217 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 792754 # Number of row buffer hits during reads +system.physmem.writeRowHits 422001 # Number of row buffer hits during writes system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes -system.physmem.avgGap 224228.68 # Average gap between requests -system.physmem.pageHitRate 40.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6483387960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3537562875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379541000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249642240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 304280359155 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134820686250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 503483271000 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.966482 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 222309059500 # Time in different power states -system.physmem_0.memoryStateTime::REF 22357920000 # Time in different power states +system.physmem.writeRowHitRate 41.20 # Row buffer hit rate for writes +system.physmem.avgGap 224217.56 # Average gap between requests +system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6484552200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3538198125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379689200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249668160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 304192019700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134879490000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 503453674665 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.957257 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 222404009750 # Time in different power states +system.physmem_0.memoryStateTime::REF 22356880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 424888778500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 424763715750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6894704880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3761991750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7911610200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387698640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 311328000180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128638545000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 505654642170 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.209486 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 211980924500 # Time in different power states -system.physmem_1.memoryStateTime::REF 22357920000 # Time in different power states +system.physmem_1.actEnergy 6896443680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3762940500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7911594600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387744000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43730057280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 311181502770 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128748364500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 505618647330 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.190855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212167441250 # Time in different power states +system.physmem_1.memoryStateTime::REF 22356880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 435216639250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 435000017500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 409355418 # Number of BP lookups -system.cpu.branchPred.condPredicted 318166975 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963047 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282312141 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278580615 # Number of BTB hits +system.cpu.branchPred.lookups 409350195 # Number of BP lookups +system.cpu.branchPred.condPredicted 318164532 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15963584 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282308187 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278578841 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.678227 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172204 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.678981 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172152 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 644928587 # DTB read hits -system.cpu.dtb.read_misses 12158902 # DTB read misses +system.cpu.dtb.read_hits 644938332 # DTB read hits +system.cpu.dtb.read_misses 12159455 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657087489 # DTB read accesses -system.cpu.dtb.write_hits 218092717 # DTB write hits -system.cpu.dtb.write_misses 7512154 # DTB write misses +system.cpu.dtb.read_accesses 657097787 # DTB read accesses +system.cpu.dtb.write_hits 218091822 # DTB write hits +system.cpu.dtb.write_misses 7511788 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225604871 # DTB write accesses -system.cpu.dtb.data_hits 863021304 # DTB hits -system.cpu.dtb.data_misses 19671056 # DTB misses +system.cpu.dtb.write_accesses 225603610 # DTB write accesses +system.cpu.dtb.data_hits 863030154 # DTB hits +system.cpu.dtb.data_misses 19671243 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882692360 # DTB accesses -system.cpu.itb.fetch_hits 420625120 # ITB hits +system.cpu.dtb.data_accesses 882701397 # DTB accesses +system.cpu.itb.fetch_hits 420624983 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420625157 # ITB accesses +system.cpu.itb.fetch_accesses 420625020 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -349,98 +348,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1339113165 # number of cpu cycles simulated +system.cpu.numCycles 1339050787 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431760554 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410003764 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409355418 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304752819 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 884588278 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380492 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 431760433 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3409990757 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409350195 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304750993 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 884524854 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45382362 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420625120 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8288982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1339040790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150665 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420624983 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8290664 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1338978167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546711 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 714026661 53.32% 53.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47659433 3.56% 56.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24224234 1.81% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45105968 3.37% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142792146 10.66% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65943853 4.92% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43594254 3.26% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29429342 2.20% 83.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226264899 16.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 713970324 53.32% 53.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47658259 3.56% 56.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24222568 1.81% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45103345 3.37% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142790906 10.66% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65943786 4.92% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43594409 3.26% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29428241 2.20% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226266329 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1339040790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305691 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769612 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 403558275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524215531 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34807834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689538 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62027781 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256129377 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2069 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689538 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372008249 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212535269 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7646 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537155328 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 194644760 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173788478 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1809495 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20462310 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 148566154 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30882701 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371842618 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117718959 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117582524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136434 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1338978167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305702 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546573 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353776569 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 403484138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524228681 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34798314 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22690465 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62024721 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256106209 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2093 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22690465 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372012141 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212467548 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7342 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537162613 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194638058 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173768927 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1816422 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20455726 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 148599653 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30860374 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371827952 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117690277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117553850 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136426 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995639655 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 143 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 142 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99637264 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717251547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272457871 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90453848 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58428187 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884203449 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620051581 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1544935 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148159789 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502731368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1339040790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.956663 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.148213 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 995624989 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 146 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99592668 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717246268 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272455740 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90411000 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58626283 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884178650 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620049271 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148134993 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502709027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1338978167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956753 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.148253 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 535540081 39.99% 39.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169652118 12.67% 52.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 157969981 11.80% 64.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149186997 11.14% 75.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125999252 9.41% 85.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84166081 6.29% 91.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68019052 5.08% 96.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34101039 2.55% 98.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14406189 1.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 535496202 39.99% 39.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169647302 12.67% 52.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157966093 11.80% 64.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149142376 11.14% 75.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126023638 9.41% 85.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84181895 6.29% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68010869 5.08% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34104922 2.55% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14404870 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1339040790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1338978167 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13157777 35.84% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13158801 35.84% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.84% # attempts to use FU when none available @@ -469,17 +468,17 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.84% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18965028 51.65% 87.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4592425 12.51% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18966749 51.66% 87.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4591786 12.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716938805 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716928227 65.53% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 896154 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896664 0.03% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued @@ -503,84 +502,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671533572 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230682699 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671542182 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230681845 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620051581 # Type of FU issued -system.cpu.iq.rate 1.956557 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36715230 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6615464746 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031257680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518620612 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1939371 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1248863 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 886699 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655799836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 966975 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69396280 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620049271 # Type of FU issued +system.cpu.iq.rate 1.956647 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36717336 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014014 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6615397697 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031207578 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518612422 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1941117 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1249905 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 887144 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655798760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 967847 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69398293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272655884 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 373351 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 145486 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111729369 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272650605 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 374228 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 146038 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111727238 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 229 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6306976 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 239 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6310160 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689538 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149806110 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21267531 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035207367 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6595956 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717251547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272457871 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 801675 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20722786 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 145486 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10633585 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701131 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19334716 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2574896999 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657087498 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45154582 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22690465 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149836338 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21229362 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035183152 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6595413 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717246268 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272455740 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 801803 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20684202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 146038 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10633994 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701055 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19335049 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2574897906 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657097795 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45151365 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151003796 # number of nop insts executed -system.cpu.iew.exec_refs 882692437 # number of memory reference insts executed -system.cpu.iew.exec_branches 315488895 # Number of branches executed -system.cpu.iew.exec_stores 225604939 # Number of stores executed -system.cpu.iew.exec_rate 1.922837 # Inst execution rate -system.cpu.iew.wb_sent 2549331117 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519507311 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487495376 # num instructions producing a value -system.cpu.iew.wb_consumers 1918378348 # num instructions consuming a value +system.cpu.iew.exec_nop 151004377 # number of nop insts executed +system.cpu.iew.exec_refs 882701473 # number of memory reference insts executed +system.cpu.iew.exec_branches 315482828 # Number of branches executed +system.cpu.iew.exec_stores 225603678 # Number of stores executed +system.cpu.iew.exec_rate 1.922928 # Inst execution rate +system.cpu.iew.wb_sent 2549323154 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519499566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487497634 # num instructions producing a value +system.cpu.iew.wb_consumers 1918379503 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.881475 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775392 # average fanout of values written-back +system.cpu.iew.wb_rate 1.881556 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775393 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 998666714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 998640819 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15962339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1201055691 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.515150 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.548433 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15962868 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1200994355 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.515228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548533 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 712334289 59.31% 59.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159635442 13.29% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79514551 6.62% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52029279 4.33% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28475742 2.37% 85.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19476450 1.62% 87.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19964545 1.66% 89.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23047887 1.92% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106577506 8.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 712309125 59.31% 59.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159609736 13.29% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79494019 6.62% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52028691 4.33% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28473987 2.37% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19488340 1.62% 87.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19957354 1.66% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23050317 1.92% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106582786 8.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1201055691 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1200994355 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -626,138 +625,138 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106577506 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3827145825 # The number of ROB reads -system.cpu.rob.rob_writes 5775013033 # The number of ROB writes -system.cpu.timesIdled 710 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 72375 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 106582786 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3827053314 # The number of ROB reads +system.cpu.rob.rob_writes 5774960362 # The number of ROB writes +system.cpu.timesIdled 711 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 72620 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.771359 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.771359 # CPI: Total CPI of All Threads -system.cpu.ipc 1.296413 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.296413 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463596666 # number of integer regfile reads -system.cpu.int_regfile_writes 2019349968 # number of integer regfile writes -system.cpu.fp_regfile_reads 39643 # number of floating regfile reads +system.cpu.cpi 0.771323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771323 # CPI: Total CPI of All Threads +system.cpu.ipc 1.296473 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.296473 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463595596 # number of integer regfile reads +system.cpu.int_regfile_writes 2019348323 # number of integer regfile writes +system.cpu.fp_regfile_reads 39740 # number of floating regfile reads system.cpu.fp_regfile_writes 588 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9207223 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.441459 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712346742 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211319 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.333848 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 9207181 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.441061 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712353360 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211277 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.334919 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441459 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997911 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441061 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997910 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997910 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 707 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2960 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 698 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2969 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470153653 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470153653 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 556848599 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556848599 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498140 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1470163219 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470163219 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 556855010 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556855010 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498347 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498347 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712346739 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712346739 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712346739 # number of overall hits -system.cpu.dcache.overall_hits::total 712346739 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12894062 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12894062 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230362 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230362 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 712353357 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712353357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712353357 # number of overall hits +system.cpu.dcache.overall_hits::total 712353357 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12892455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12892455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230155 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230155 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18124424 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18124424 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18124424 # number of overall misses -system.cpu.dcache.overall_misses::total 18124424 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412011773000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315105865697 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 18122610 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18122610 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18122610 # number of overall misses +system.cpu.dcache.overall_misses::total 18122610 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 411787652500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315044398573 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 727117638697 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 727117638697 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 727117638697 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 727117638697 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569742661 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569742661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 726832051073 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 726832051073 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 726832051073 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 726832051073 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569747465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569747465 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730471163 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730471163 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730471163 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730471163 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022631 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022631 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032542 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032542 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 730475967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730475967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730475967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730475967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022628 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022628 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032540 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032540 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024812 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024812 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024812 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024812 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.024809 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024809 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024809 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024809 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40118.110164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40118.110164 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15661523 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9569226 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1103711 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 68026 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.189877 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.670126 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40106.367188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40106.367188 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15689743 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9578184 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1104687 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68028 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.202886 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.797672 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3727748 # number of writebacks -system.cpu.dcache.writebacks::total 3727748 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5561934 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5561934 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351172 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3351172 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8913106 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8913106 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8913106 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8913106 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332128 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332128 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879190 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879190 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3727717 # number of writebacks +system.cpu.dcache.writebacks::total 3727717 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5560371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5560371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350963 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3350963 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8911334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8911334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8911334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8911334 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332084 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7332084 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879192 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879192 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211318 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211318 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211318 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211318 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84331903655 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84331903655 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9211276 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211276 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211276 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211276 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84332021587 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84332021587 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267291757155 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267291757155 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267288661587 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267288661587 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses @@ -768,201 +767,208 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967 # 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Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 441367.786988 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 755.106219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368704 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368704 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 950 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 755.122971 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.368712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.368712 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 952 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 886 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.463867 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841251191 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841251191 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 420623640 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420623640 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420623640 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420623640 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420623640 # number of overall hits -system.cpu.icache.overall_hits::total 420623640 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1480 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1480 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1480 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1480 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1480 # number of overall misses -system.cpu.icache.overall_misses::total 1480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114807500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114807500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114807500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114807500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114807500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114807500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420625120 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420625120 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76540.485830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76540.485830 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 57.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.411033 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.411033 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162077 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162077 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162079 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162079 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.212867 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.212948 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.212868 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.212950 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.212867 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.212948 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89760.492403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89760.492403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82271.293375 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82271.293375 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89621.269891 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89621.269891 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82271.293375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89676.114069 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 89672.524401 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82271.293375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89676.114069 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 89672.524401 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.212868 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.212950 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89759.410396 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89759.410396 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81567.156348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89618.015334 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89669.777254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -971,122 +977,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1024306 # number of writebacks -system.cpu.l2cache.writebacks::total 1024306 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 241 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 241 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772416 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 772416 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 951 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 951 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188370 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188370 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1960786 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 951 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960786 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961737 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61608280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61608280500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68730000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68730000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94619528500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94619528500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68730000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156227809000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156296539000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68730000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156227809000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1024311 # number of writebacks +system.cpu.l2cache.writebacks::total 1024311 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772417 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 772417 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188371 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188371 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 953 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960788 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 953 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960788 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961741 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61607524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61607524500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68203500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68203500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94615740500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94615740500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68203500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68203500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411033 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411033 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162077 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162079 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162079 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212948 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212950 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.212948 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212868 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212950 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18419494 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207224 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18419412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207182 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1279 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1280 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 951 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828100288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000063 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007928 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7333022 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4752028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6384190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 953 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332069 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629735 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828095616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828156672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929037 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11141267 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000115 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010718 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20347246 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1279 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11139987 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1280 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11141267 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12937424000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1426500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1429500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13816978500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13816915500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1189321 # Transaction distribution -system.membus.trans_dist::Writeback 1024306 # Transaction distribution -system.membus.trans_dist::CleanEvict 903687 # Transaction distribution -system.membus.trans_dist::ReadExReq 772416 # Transaction distribution -system.membus.trans_dist::ReadExResp 772416 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189321 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851467 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191106752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191106752 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1189324 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1024311 # Transaction distribution +system.membus.trans_dist::CleanEvict 903686 # Transaction distribution +system.membus.trans_dist::ReadExReq 772417 # Transaction distribution +system.membus.trans_dist::ReadExResp 772417 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851479 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851479 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191107328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191107328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3889730 # Request fanout histogram +system.membus.snoop_fanout::samples 3889738 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889730 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889738 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889730 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475633500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3889738 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475624000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684578250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10684646000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index d971ffdfc..2fb4a6971 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623057 # Number of seconds simulated -sim_ticks 2623057163500 # Number of ticks simulated -final_tick 2623057163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.636720 # Number of seconds simulated +sim_ticks 2636719559500 # Number of ticks simulated +final_tick 2636719559500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1405944 # Simulator instruction rate (inst/s) -host_op_rate 1405944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2026548224 # Simulator tick rate (ticks/s) -host_mem_usage 297224 # Number of bytes of host memory used -host_seconds 1294.35 # Real time elapsed on the host +host_inst_rate 1488641 # Simulator instruction rate (inst/s) +host_op_rate 1488641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2156924734 # Simulator tick rate (ticks/s) +host_mem_usage 297352 # Number of bytes of host memory used +host_seconds 1222.44 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 1951440 # Nu system.physmem.num_reads::total 1952242 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1021962 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47613206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47632774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24934862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24934862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24934862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47613206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72567635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 19467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47366494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47385960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24805660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24805660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47366494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72191620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246114327 # number of cpu cycles simulated +system.cpu.numCycles 5273439119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246114327 # Number of busy cycles +system.cpu.num_busy_cycles 5273439119 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -129,19 +129,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.260769 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4079.293901 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977438500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.260769 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995913 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995913 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 41036287500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.293901 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995921 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995921 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 9111734 # n system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143001525000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143001525000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57421337000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57421337000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200422862000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200422862000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200422862000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200422862000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151181633000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62898029000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214079662000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214079662000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214079662000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19799.685396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19799.685396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30392.594690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30392.594690 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21996.127411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21996.127411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21996.127411 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20932.285660 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20932.285660 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33291.358266 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33291.358266 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23494.942017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23494.942017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135779111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135779111000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55532017000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55532017000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191311128000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191311128000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191311128000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191311128000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143959219000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61008709000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204967928000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204967928000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204967928000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses @@ -228,26 +228,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18799.685396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18799.685396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29392.594690 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29392.594690 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20996.127411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20996.127411 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19932.285660 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32291.358266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22494.942017 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22494.942017 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.447387 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.605858 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.447387 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299047 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299047 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 612.605858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.299124 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.299124 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses @@ -264,12 +265,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44163500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44163500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44163500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44163500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44163500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44163500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 49759500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 49759500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 49759500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 49759500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 49759500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -282,12 +283,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55066.708229 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55066.708229 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55066.708229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55066.708229 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55066.708229 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62044.264339 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62044.264339 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62044.264339 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62044.264339 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,55 +297,59 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 1 # number of writebacks +system.cpu.icache.writebacks::total 1 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43361500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 43361500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43361500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 43361500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43361500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 43361500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48957500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48957500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48957500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48957500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54066.708229 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54066.708229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54066.708229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54066.708229 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61044.264339 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61044.264339 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61044.264339 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1919524 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30534.757407 # Cycle average of tags in use +system.cpu.l2cache.tags.replacements 1919525 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30540.825713 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 14380256 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1949316 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.377078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167130000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15101.273798 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.972607 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15394.511002 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.460854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001189 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.469803 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.931847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.sampled_refs 1949317 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.377074 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 218471945000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15091.675189 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.824340 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15410.326183 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.460561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001185 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.470286 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.932032 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1062 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1058 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27302 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149600036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149600036 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3679426 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3679426 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 149600037 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149600037 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3679426 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1106935 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1106935 # number of ReadExReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6053359 # number of ReadSharedReq hits @@ -365,20 +370,22 @@ system.cpu.l2cache.demand_misses::total 1952242 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1951440 # number of overall misses system.cpu.l2cache.overall_misses::total 1952242 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41075219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41075219500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 42150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 42150500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61385220500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61385220500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102460440000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102502590500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42150500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102460440000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102502590500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 3679426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3679426 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46551911500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 47746500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69565328500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47746500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116117240000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116164986500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47746500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116117240000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116164986500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3679426 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) @@ -403,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.214237 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214237 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.008947 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.008947 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52556.733167 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52556.733167 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52508.411067 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52508.411067 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52505.063665 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52556.733167 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52505.042430 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52505.063665 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.005113 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59534.289277 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.607948 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59503.374326 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59534.289277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59503.361620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59503.374326 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -425,8 +432,8 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021962 # number of writebacks system.cpu.l2cache.writebacks::total 1021962 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782385 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 782385 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses @@ -439,18 +446,18 @@ system.cpu.l2cache.demand_mshr_misses::total 1952242 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1951440 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1952242 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33251369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33251369500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34130500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34130500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49694670500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49694670500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82946040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82980170500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82946040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82980170500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38728061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 39726500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57874778500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39726500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96602840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96642566500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39726500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96602840000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96642566500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414109 # mshr miss rate for ReadExReq accesses @@ -465,18 +472,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214237 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214168 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214237 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.008947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.008947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42556.733167 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42556.733167 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42508.411067 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42508.411067 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42556.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42505.042430 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.063665 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.005113 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49534.289277 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.607948 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49534.289277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49503.361620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.374326 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -485,7 +492,8 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1122 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1122 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4701388 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 6325775 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution @@ -494,29 +502,29 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818634240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818685568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919524 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20139699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007464 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 818685632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919525 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032061 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000102 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010084 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20138577 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11030939 99.99% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1122 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20139699 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12789513500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11032061 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12789514500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadResp 1169857 # Transaction distribution -system.membus.trans_dist::Writeback 1021962 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021962 # Transaction distribution system.membus.trans_dist::CleanEvict 896683 # Transaction distribution system.membus.trans_dist::ReadExReq 782385 # Transaction distribution system.membus.trans_dist::ReadExResp 782385 # Transaction distribution @@ -526,19 +534,19 @@ system.membus.pkt_count::total 5823129 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190349056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 190349056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3872712 # Request fanout histogram +system.membus.snoop_fanout::samples 3870887 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3872712 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870887 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3872712 # Request fanout histogram -system.membus.reqLayer0.occupancy 7960873524 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870887 # Request fanout histogram +system.membus.reqLayer0.occupancy 7958742500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9761522024 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9761210000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 766f60b6c..144dc4013 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.116866 # Number of seconds simulated -sim_ticks 1116865669500 # Number of ticks simulated -final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116861 # Number of seconds simulated +sim_ticks 1116860578500 # Number of ticks simulated +final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226280 # Simulator instruction rate (inst/s) -host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 163622006 # Simulator tick rate (ticks/s) -host_mem_usage 317884 # Number of bytes of host memory used -host_seconds 6825.89 # Real time elapsed on the host +host_inst_rate 237615 # Simulator instruction rate (inst/s) +host_op_rate 255994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171817202 # Simulator tick rate (ticks/s) +host_mem_usage 317996 # Number of bytes of host memory used +host_seconds 6500.28 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory -system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 50176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50176 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045808 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2046591 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 44926 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117231922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117276848 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 44926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 44926 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60175704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60175704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60175704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 44926 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117231922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177452552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046592 # Number of read requests accepted system.physmem.writeReqs 1050123 # Number of write requests accepted -system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 130898112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127282 # Per bank write bursts -system.physmem.perBankRdBursts::1 124660 # Per bank write bursts -system.physmem.perBankRdBursts::2 121599 # Per bank write bursts -system.physmem.perBankRdBursts::3 123658 # Per bank write bursts -system.physmem.perBankRdBursts::4 122616 # Per bank write bursts -system.physmem.perBankRdBursts::5 122675 # Per bank write bursts -system.physmem.perBankRdBursts::6 123246 # Per bank write bursts -system.physmem.perBankRdBursts::7 123764 # Per bank write bursts -system.physmem.perBankRdBursts::8 131397 # Per bank write bursts -system.physmem.perBankRdBursts::9 133514 # Per bank write bursts -system.physmem.perBankRdBursts::10 132084 # Per bank write bursts -system.physmem.perBankRdBursts::11 133304 # Per bank write bursts -system.physmem.perBankRdBursts::12 133248 # Per bank write bursts -system.physmem.perBankRdBursts::13 133365 # Per bank write bursts -system.physmem.perBankRdBursts::14 129309 # Per bank write bursts -system.physmem.perBankRdBursts::15 129545 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 127279 # Per bank write bursts +system.physmem.perBankRdBursts::1 124661 # Per bank write bursts +system.physmem.perBankRdBursts::2 121601 # Per bank write bursts +system.physmem.perBankRdBursts::3 123659 # Per bank write bursts +system.physmem.perBankRdBursts::4 122620 # Per bank write bursts +system.physmem.perBankRdBursts::5 122678 # Per bank write bursts +system.physmem.perBankRdBursts::6 123247 # Per bank write bursts +system.physmem.perBankRdBursts::7 123768 # Per bank write bursts +system.physmem.perBankRdBursts::8 131395 # Per bank write bursts +system.physmem.perBankRdBursts::9 133511 # Per bank write bursts +system.physmem.perBankRdBursts::10 132082 # Per bank write bursts +system.physmem.perBankRdBursts::11 133309 # Per bank write bursts +system.physmem.perBankRdBursts::12 133249 # Per bank write bursts +system.physmem.perBankRdBursts::13 133361 # Per bank write bursts +system.physmem.perBankRdBursts::14 129308 # Per bank write bursts +system.physmem.perBankRdBursts::15 129555 # Per bank write bursts system.physmem.perBankWrBursts::0 66136 # Per bank write bursts system.physmem.perBankWrBursts::1 64410 # Per bank write bursts system.physmem.perBankWrBursts::2 62576 # Per bank write bursts @@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3 63006 # Pe system.physmem.perBankWrBursts::4 63000 # Per bank write bursts system.physmem.perBankWrBursts::5 63100 # Per bank write bursts system.physmem.perBankWrBursts::6 64443 # Per bank write bursts -system.physmem.perBankWrBursts::7 65436 # Per bank write bursts -system.physmem.perBankWrBursts::8 67310 # Per bank write bursts -system.physmem.perBankWrBursts::9 67797 # Per bank write bursts -system.physmem.perBankWrBursts::10 67549 # Per bank write bursts +system.physmem.perBankWrBursts::7 65435 # Per bank write bursts +system.physmem.perBankWrBursts::8 67311 # Per bank write bursts +system.physmem.perBankWrBursts::9 67795 # Per bank write bursts +system.physmem.perBankWrBursts::10 67548 # Per bank write bursts system.physmem.perBankWrBursts::11 67882 # Per bank write bursts -system.physmem.perBankWrBursts::12 67326 # Per bank write bursts +system.physmem.perBankWrBursts::12 67328 # Per bank write bursts system.physmem.perBankWrBursts::13 67793 # Per bank write bursts -system.physmem.perBankWrBursts::14 66482 # Per bank write bursts +system.physmem.perBankWrBursts::14 66483 # Per bank write bursts system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1116865575000 # Total gap between requests +system.physmem.totGap 1116860484000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2046591 # Read request sizes (log2) +system.physmem.readPktSize::6 2046592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1050123 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1916633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128632 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33960 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see @@ -193,54 +193,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1910141 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.711749 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.835384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.555895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485377 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305179 15.98% 93.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::384-511 21040 1.10% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13364 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7561 0.40% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5492 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5154 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14480 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910141 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.410579 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 159.595244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61092 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 21 0.03% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.175897 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.140866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.098115 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27038 44.22% 44.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1118 1.83% 46.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28658 46.87% 92.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3907 6.39% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 362 0.59% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 47 0.08% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 6 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads -system.physmem.totQLat 38113681000 # Total ticks spent queuing -system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 61138 # Writes before turning the bus around for reads +system.physmem.totQLat 38118822750 # Total ticks spent queuing +system.physmem.totMemAccLat 76467879000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18637.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 37387.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s @@ -250,46 +249,46 @@ system.physmem.busUtil 1.39 # Da system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 773150 # Number of row buffer hits during reads -system.physmem.writeRowHits 411758 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes -system.physmem.avgGap 360661.52 # Average gap between requests -system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing +system.physmem.readRowHits 773327 # Number of row buffer hits during reads +system.physmem.writeRowHits 411912 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.23 # Row buffer hit rate for writes +system.physmem.avgGap 360659.76 # Average gap between requests +system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7038745560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3840585375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7718170200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.167175 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states +system.physmem_0.actBackEnergy 420695682570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301084680000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816644156985 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.196552 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498171573500 # Time in different power states system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581394006750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 7401920400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038746250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234982600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486201120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.287251 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states +system.physmem_1.actBackEnergy 429157184085 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293662305750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818929186605 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.242498 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485776924250 # Time in different power states system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 593789084750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239639075 # Number of BP lookups -system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted +system.cpu.branchPred.lookups 239639085 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342301 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits +system.cpu.branchPred.BTBLookups 130646105 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079391 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. @@ -412,68 +411,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2233731339 # number of cpu cycles simulated +system.cpu.numCycles 2233721157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470128 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446190 # CPI: cycles per instruction -system.cpu.ipc 0.691472 # IPC: instructions per cycle -system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9221039 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. +system.cpu.cpi 1.446183 # CPI: cycles per instruction +system.cpu.ipc 0.691475 # IPC: instructions per cycle +system.cpu.tickCycles 1834122800 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399598357 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221041 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.616187 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218895 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616187 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841907 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841907 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331057 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331057 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits -system.cpu.dcache.overall_hits::total 624218772 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624218772 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218772 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218773 # number of overall hits +system.cpu.dcache.overall_hits::total 624218773 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7334498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7334498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254990 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254990 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses -system.cpu.dcache.overall_misses::total 9589497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589488 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589488 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589490 # number of overall misses +system.cpu.dcache.overall_misses::total 9589490 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190927662500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109073789000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300001451500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300001451500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300001451500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300001451500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222213 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,10 +481,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 633808260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808263 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses @@ -496,14 +495,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31284.407624 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31284.401100 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,36 +511,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3684564 # number of writebacks -system.cpu.dcache.writebacks::total 3684564 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3684566 # number of writebacks +system.cpu.dcache.writebacks::total 3684566 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890852 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 364137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364352 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7334283 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890853 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890853 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9225136 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9225137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9225137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84772423500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84772423500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 268360047000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 268360121000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -552,24 +551,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 661.384835 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 465281420 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567416.365854 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 661.384835 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id @@ -577,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32 system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses -system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits -system.cpu.icache.overall_hits::total 465281545 # number of overall hits +system.cpu.icache.tags.tag_accesses 930565300 # Number of tag accesses +system.cpu.icache.tags.data_accesses 930565300 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 465281420 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 465281420 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 465281420 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 465281420 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 465281420 # number of overall hits +system.cpu.icache.overall_hits::total 465281420 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62291000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62291000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62291000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62291000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62291000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62291000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 465282240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 465282240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 465282240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 465282240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 465282240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 465282240 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75964.634146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75964.634146 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -623,129 +622,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 29 # number of writebacks +system.cpu.icache.writebacks::total 29 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 61471000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 61471000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61471000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61471000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2013890 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2043665 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 784 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62422904500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62422904500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51986500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51986500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96191610000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96191610000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51986500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158614514500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158666501000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51986500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956098 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956098 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221765 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 18447027 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2013920 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11239877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.016091 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11236984 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2887 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11239877 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908108500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13837707496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1245436 # Transaction distribution -system.membus.trans_dist::Writeback 1050123 # Transaction distribution -system.membus.trans_dist::CleanEvict 962723 # Transaction distribution -system.membus.trans_dist::ReadExReq 801155 # Transaction distribution -system.membus.trans_dist::ReadExResp 801155 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1245433 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution +system.membus.trans_dist::CleanEvict 962724 # Transaction distribution +system.membus.trans_dist::ReadExReq 801159 # Transaction distribution +system.membus.trans_dist::ReadExResp 801159 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1245433 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4059437 # Request fanout histogram +system.membus.snoop_fanout::samples 4059439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4059437 # Request fanout histogram -system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059439 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663213500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191513500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 09d71d56d..41989d0e2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.770336 # Number of seconds simulated -sim_ticks 770336310500 # Number of ticks simulated -final_tick 770336310500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767966 # Number of seconds simulated +sim_ticks 767965542000 # Number of ticks simulated +final_tick 767965542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130811 # Simulator instruction rate (inst/s) -host_op_rate 140929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65240720 # Simulator tick rate (ticks/s) -host_mem_usage 314688 # Number of bytes of host memory used -host_seconds 11807.60 # Real time elapsed on the host +host_inst_rate 135762 # Simulator instruction rate (inst/s) +host_op_rate 146263 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 67501614 # Simulator tick rate (ticks/s) +host_mem_usage 354608 # Number of bytes of host memory used +host_seconds 11377.00 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238054976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63977600 # Number of bytes read from this memory -system.physmem.bytes_read::total 302099072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104804160 # Number of bytes written to this memory -system.physmem.bytes_written::total 104804160 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3719609 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 999650 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720298 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1637565 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1637565 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 86321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309027334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 83051518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 392165172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 86321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136049877 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136049877 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136049877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 86321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309027334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 83051518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 528215049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720298 # Number of read requests accepted -system.physmem.writeReqs 1637565 # Number of write requests accepted -system.physmem.readBursts 4720298 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1637565 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301639360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 459712 # Total number of bytes read from write queue -system.physmem.bytesWritten 104801536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302099072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104804160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7183 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296850 # Per bank write bursts -system.physmem.perBankRdBursts::1 294498 # Per bank write bursts -system.physmem.perBankRdBursts::2 288916 # Per bank write bursts -system.physmem.perBankRdBursts::3 292682 # Per bank write bursts -system.physmem.perBankRdBursts::4 290729 # Per bank write bursts -system.physmem.perBankRdBursts::5 289596 # Per bank write bursts -system.physmem.perBankRdBursts::6 284483 # Per bank write bursts -system.physmem.perBankRdBursts::7 281209 # Per bank write bursts -system.physmem.perBankRdBursts::8 297427 # Per bank write bursts -system.physmem.perBankRdBursts::9 303552 # Per bank write bursts -system.physmem.perBankRdBursts::10 295336 # Per bank write bursts -system.physmem.perBankRdBursts::11 302232 # Per bank write bursts -system.physmem.perBankRdBursts::12 303231 # Per bank write bursts -system.physmem.perBankRdBursts::13 302345 # Per bank write bursts -system.physmem.perBankRdBursts::14 297342 # Per bank write bursts -system.physmem.perBankRdBursts::15 292687 # Per bank write bursts -system.physmem.perBankWrBursts::0 104014 # Per bank write bursts -system.physmem.perBankWrBursts::1 101992 # Per bank write bursts -system.physmem.perBankWrBursts::2 99263 # Per bank write bursts -system.physmem.perBankWrBursts::3 99947 # Per bank write bursts -system.physmem.perBankWrBursts::4 99433 # Per bank write bursts -system.physmem.perBankWrBursts::5 98879 # Per bank write bursts -system.physmem.perBankWrBursts::6 102579 # Per bank write bursts -system.physmem.perBankWrBursts::7 104318 # Per bank write bursts -system.physmem.perBankWrBursts::8 105363 # Per bank write bursts -system.physmem.perBankWrBursts::9 104471 # Per bank write bursts -system.physmem.perBankWrBursts::10 102169 # Per bank write bursts -system.physmem.perBankWrBursts::11 102930 # Per bank write bursts -system.physmem.perBankWrBursts::12 102920 # Per bank write bursts -system.physmem.perBankWrBursts::13 102581 # Per bank write bursts -system.physmem.perBankWrBursts::14 104115 # Per bank write bursts -system.physmem.perBankWrBursts::15 102550 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235466816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63671744 # Number of bytes read from this memory +system.physmem.bytes_read::total 299203584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104705856 # Number of bytes written to this memory +system.physmem.bytes_written::total 104705856 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3679169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 994871 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4675056 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1636029 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1636029 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306611173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82909637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389605481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84670 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136341867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136341867 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136341867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306611173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82909637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525947348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4675056 # Number of read requests accepted +system.physmem.writeReqs 1636029 # Number of write requests accepted +system.physmem.readBursts 4675056 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1636029 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298722176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 481408 # Total number of bytes read from write queue +system.physmem.bytesWritten 104702912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299203584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104705856 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7522 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 3003359 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 301326 # Per bank write bursts +system.physmem.perBankRdBursts::1 298715 # Per bank write bursts +system.physmem.perBankRdBursts::2 284983 # Per bank write bursts +system.physmem.perBankRdBursts::3 287209 # Per bank write bursts +system.physmem.perBankRdBursts::4 287920 # Per bank write bursts +system.physmem.perBankRdBursts::5 285373 # Per bank write bursts +system.physmem.perBankRdBursts::6 281637 # Per bank write bursts +system.physmem.perBankRdBursts::7 277868 # Per bank write bursts +system.physmem.perBankRdBursts::8 293986 # Per bank write bursts +system.physmem.perBankRdBursts::9 298704 # Per bank write bursts +system.physmem.perBankRdBursts::10 291815 # Per bank write bursts +system.physmem.perBankRdBursts::11 297314 # Per bank write bursts +system.physmem.perBankRdBursts::12 299397 # Per bank write bursts +system.physmem.perBankRdBursts::13 298122 # Per bank write bursts +system.physmem.perBankRdBursts::14 294010 # Per bank write bursts +system.physmem.perBankRdBursts::15 289155 # Per bank write bursts +system.physmem.perBankWrBursts::0 103823 # Per bank write bursts +system.physmem.perBankWrBursts::1 101759 # Per bank write bursts +system.physmem.perBankWrBursts::2 99255 # Per bank write bursts +system.physmem.perBankWrBursts::3 99822 # Per bank write bursts +system.physmem.perBankWrBursts::4 99277 # Per bank write bursts +system.physmem.perBankWrBursts::5 98671 # Per bank write bursts +system.physmem.perBankWrBursts::6 102768 # Per bank write bursts +system.physmem.perBankWrBursts::7 104279 # Per bank write bursts +system.physmem.perBankWrBursts::8 105369 # Per bank write bursts +system.physmem.perBankWrBursts::9 104220 # Per bank write bursts +system.physmem.perBankWrBursts::10 102032 # Per bank write bursts +system.physmem.perBankWrBursts::11 102651 # Per bank write bursts +system.physmem.perBankWrBursts::12 102828 # Per bank write bursts +system.physmem.perBankWrBursts::13 102619 # Per bank write bursts +system.physmem.perBankWrBursts::14 104194 # Per bank write bursts +system.physmem.perBankWrBursts::15 102416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 770336158500 # Total gap between requests +system.physmem.totGap 767965500500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720298 # Read request sizes (log2) +system.physmem.readPktSize::6 4675056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1637565 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2783946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1045590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 328353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 232144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 151285 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 83614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1636029 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2763524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1029428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 149305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18003 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 23160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 60100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 75642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 85493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 114322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 105421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 73176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,114 +197,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4289513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.751761 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.903148 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.431882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3416049 79.64% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 675171 15.74% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96645 2.25% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35451 0.83% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23003 0.54% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12074 0.28% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6995 0.16% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5025 0.12% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19100 0.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4289513 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.769871 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.372187 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 98.540692 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 96215 97.52% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1195 1.21% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 729 0.74% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 403 0.41% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 87 0.09% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98662 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.597312 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.563431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.103098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 72815 73.80% 73.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1780 1.80% 75.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18354 18.60% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3927 3.98% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 986 1.00% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 404 0.41% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 201 0.20% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 116 0.12% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 44 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98662 # Writes before turning the bus around for reads -system.physmem.totQLat 131160021238 # Total ticks spent queuing -system.physmem.totMemAccLat 219530927488 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23565575000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27828.73 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 4246279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.006264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.933304 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.667614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3382951 79.67% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 666013 15.68% 95.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94842 2.23% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35210 0.83% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22787 0.54% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12374 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7276 0.17% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5157 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19669 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4246279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97783 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.733256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.725873 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 93691 95.82% 95.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1680 1.72% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 798 0.82% 98.35% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 374 0.38% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 374 0.38% 99.11% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 340 0.35% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 220 0.22% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 159 0.16% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 76 0.08% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 37 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 11 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1664-1791 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2304-2431 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3712-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97783 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97783 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.730751 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.687620 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.251075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68399 69.95% 69.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2006 2.05% 72.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18369 18.79% 90.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5745 5.88% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1950 1.99% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 718 0.73% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 317 0.32% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 149 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 75 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 97783 # Writes before turning the bus around for reads +system.physmem.totQLat 128413030932 # Total ticks spent queuing +system.physmem.totMemAccLat 215929293432 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23337670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27511.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46578.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 391.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 136.05 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 392.17 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46261.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.12 # Data bus utilization in percentage -system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing -system.physmem.readRowHits 1707273 # Number of row buffer hits during reads -system.physmem.writeRowHits 353841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.61 # Row buffer hit rate for writes -system.physmem.avgGap 121162.75 # Average gap between requests -system.physmem.pageHitRate 32.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16082924760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8775405375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18087474600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5251508640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409609386630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102893262750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 611014346355 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.182199 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 168633417027 # Time in different power states -system.physmem_0.memoryStateTime::REF 25723100000 # Time in different power states +system.physmem.busUtil 4.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing +system.physmem.readRowHits 1709654 # Number of row buffer hits during reads +system.physmem.writeRowHits 347571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes +system.physmem.avgGap 121685.18 # Average gap between requests +system.physmem.pageHitRate 32.64 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15953799960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8704950375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17977486800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5246246880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 414403163865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97263315750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609708236430 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.934243 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 159282861364 # Time in different power states +system.physmem_0.memoryStateTime::REF 25643800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 575976400473 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583033093643 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16345687680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8918778000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18674323200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5359543200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50314383600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410844304170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 101810001750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 612267021600 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.808347 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 166829398639 # Time in different power states -system.physmem_1.memoryStateTime::REF 25723100000 # Time in different power states +system.physmem_1.actEnergy 16147600560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8810694750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18427445400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354300880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410341742010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100825962000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 610067018400 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.401440 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165241048217 # Time in different power states +system.physmem_1.memoryStateTime::REF 25643800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 577780670361 # Time in different power states +system.physmem_1.memoryStateTime::ACT 577073869783 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286278310 # Number of BP lookups -system.cpu.branchPred.condPredicted 223407435 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630059 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158227088 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150348964 # Number of BTB hits +system.cpu.branchPred.lookups 286290965 # Number of BP lookups +system.cpu.branchPred.condPredicted 223414875 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14630075 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157650249 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150360830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.021002 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641238 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.376208 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641594 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -424,128 +433,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1540672622 # number of cpu cycles simulated +system.cpu.numCycles 1535931085 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926355 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067514794 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286278310 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166990202 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1512022873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284737 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 188 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1021 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656940964 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 966 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1540592805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.437738 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13926236 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067547876 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286290965 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 167002424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507284638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29284969 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 196 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 917 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656963855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 927 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535854471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442200 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228202 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 458181319 29.74% 29.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465421558 30.21% 59.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101422593 6.58% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515567335 33.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453416615 29.52% 29.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465436740 30.30% 59.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101431033 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515570083 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1540592805 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185814 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.341956 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74646858 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 543216907 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849967493 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58119883 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641664 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42201795 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 757 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037179352 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52470113 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139717275 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 462450514 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13916 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837848883 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 85920553 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976355004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26745374 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45156757 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125486 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1486003 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25049006 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985823032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128033727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432836892 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 151 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1535854471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186396 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346120 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74705927 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538395080 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849912555 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58199125 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14641784 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202960 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037254051 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52495885 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14641784 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139801946 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457449218 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13751 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837842602 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86105170 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976447004 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26743472 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45311241 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126368 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1599527 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25035305 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985923292 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128451044 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432959840 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 125 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310924087 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 156 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 148 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111428528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542554069 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199305704 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26941972 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29270810 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947933260 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 215 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857474146 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13497185 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283901059 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647116126 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1540592805 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.205688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150881 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 311024347 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 154 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111506310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542573483 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199309856 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26973622 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29535518 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948030100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857442950 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13480165 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997895 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647563158 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1535854471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209387 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150580 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 587702275 38.15% 38.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325996808 21.16% 59.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378232244 24.55% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219639231 14.26% 98.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29016078 1.88% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6169 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582872858 37.95% 37.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326140941 21.24% 59.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378202799 24.62% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219661262 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28970430 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6181 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1540592805 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535854471 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166081126 41.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1996 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191505284 47.27% 88.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47530605 11.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166043738 41.02% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1958 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191460391 47.30% 88.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47270881 11.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138242397 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801060 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138255914 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800916 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -567,90 +576,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 32 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532116023 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186314612 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532080715 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186305355 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857474146 # Type of FU issued -system.cpu.iq.rate 1.205625 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405119011 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218102 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5674157044 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2231847189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805703414 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 266 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262593018 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 139 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17811740 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857442950 # Type of FU issued +system.cpu.iq.rate 1.209327 # Inst issue rate +system.cpu.iq.fu_busy_cnt 404776968 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.217922 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5668997271 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232041055 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805706922 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 233 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 216 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262219787 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 131 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17802666 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84247735 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66708 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13149 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24458659 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84267149 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66494 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13286 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24462811 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4504401 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4884981 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4478194 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4870766 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25329983 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1325123 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947933556 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14641784 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25370881 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1332488 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030384 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542554069 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199305704 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 153 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159005 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1165002 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13149 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699177 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8705456 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16404633 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827812064 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516937908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29662082 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542573483 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199309856 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159276 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1171811 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13286 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7699902 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8704078 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16403980 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827785519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516901938 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29657431 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 698690935 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542500 # Number of branches executed -system.cpu.iew.exec_stores 181753027 # Number of stores executed -system.cpu.iew.exec_rate 1.186373 # Inst execution rate -system.cpu.iew.wb_sent 1808734068 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805703486 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169239698 # num instructions producing a value -system.cpu.iew.wb_consumers 1689624086 # num instructions consuming a value +system.cpu.iew.exec_nop 73 # number of nop insts executed +system.cpu.iew.exec_refs 698651224 # number of memory reference insts executed +system.cpu.iew.exec_branches 229542579 # Number of branches executed +system.cpu.iew.exec_stores 181749286 # Number of stores executed +system.cpu.iew.exec_rate 1.190018 # Inst execution rate +system.cpu.iew.wb_sent 1808742163 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805706990 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169201528 # num instructions producing a value +system.cpu.iew.wb_consumers 1689618558 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.172023 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692012 # average fanout of values written-back +system.cpu.iew.wb_rate 1.175643 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691991 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 258007667 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 258099025 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1501111622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.108533 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.025633 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14629375 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496362804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.027734 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 920819202 61.34% 61.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250634053 16.70% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110061016 7.33% 85.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55281373 3.68% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29321487 1.95% 91.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34081425 2.27% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24716781 1.65% 94.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18131809 1.21% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58064476 3.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 916038990 61.22% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250656359 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110050903 7.35% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55261193 3.69% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29363802 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34102831 2.28% 93.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24718362 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18151757 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58018607 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1501111622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496362804 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -696,76 +705,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58064476 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3365086648 # The number of ROB reads -system.cpu.rob.rob_writes 3883566462 # The number of ROB writes -system.cpu.timesIdled 859 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79817 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58018607 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360475057 # The number of ROB reads +system.cpu.rob.rob_writes 3883759706 # The number of ROB writes +system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76614 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.997481 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.997481 # CPI: Total CPI of All Threads -system.cpu.ipc 1.002525 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.002525 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175803949 # number of integer regfile reads -system.cpu.int_regfile_writes 1261568723 # number of integer regfile writes +system.cpu.cpi 0.994411 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994411 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005620 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005620 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175771978 # number of integer regfile reads +system.cpu.int_regfile_writes 1261585669 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 54 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965710140 # number of cc regfile reads -system.cpu.cc_regfile_writes 551865181 # number of cc regfile writes -system.cpu.misc_regfile_reads 675846539 # number of misc regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965626191 # number of cc regfile reads +system.cpu.cc_regfile_writes 551852831 # number of cc regfile writes +system.cpu.misc_regfile_reads 675841321 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004606 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964973 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638063275 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17005118 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.521838 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77839500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964973 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17004065 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964813 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638072070 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004577 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.523549 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964813 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 420 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 416 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335698850 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335698850 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469343498 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469343498 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168719659 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168719659 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335720557 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335720557 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469353506 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469353506 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718419 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718419 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638063157 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638063157 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638063157 # number of overall hits -system.cpu.dcache.overall_hits::total 638063157 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417197 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417197 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3866388 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3866388 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638071925 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638071925 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638071925 # number of overall hits +system.cpu.dcache.overall_hits::total 638071925 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17418313 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17418313 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867628 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867628 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21283585 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21283585 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21283587 # number of overall misses -system.cpu.dcache.overall_misses::total 21283587 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 415522893500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 415522893500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149855935942 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149855935942 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 565378829442 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 565378829442 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 565378829442 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 565378829442 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486760695 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486760695 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21285941 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21285941 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21285943 # number of overall misses +system.cpu.dcache.overall_misses::total 21285943 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412331077000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 561293636255 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 561293636255 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 561293636255 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 561293636255 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486771819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486771819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -774,440 +783,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659346742 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659346742 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659346744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659346744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022403 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022403 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659357866 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659357866 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659357868 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659357868 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23857.047348 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23857.047348 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38758.638797 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38758.638797 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26564.078817 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26564.078817 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26564.076320 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26564.076320 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20755892 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3446894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946527 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67143 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.928473 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51.336610 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032283 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032283 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032283 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032283 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26369.218831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26369.216353 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20544187 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3409553 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942936 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67231 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.787467 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.714001 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4835415 # number of writebacks -system.cpu.dcache.writebacks::total 4835415 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149636 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3149636 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1128832 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1128832 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17004065 # number of writebacks +system.cpu.dcache.writebacks::total 17004065 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151291 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3151291 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130068 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1130068 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4278468 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4278468 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4278468 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4278468 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267561 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14267561 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737556 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737556 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281359 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17005118 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335383172000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 335383172000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116381847286 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 116381847286 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004582 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004582 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004583 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17004583 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451765019286 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 451765019286 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451765087286 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 451765087286 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447653216597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447653216597 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23506.692700 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23506.692700 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42513.047144 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42513.047144 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025790 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025790 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26566.416408 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26566.416408 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26566.418844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26566.418844 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 592 # number of replacements -system.cpu.icache.tags.tagsinuse 446.127099 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656939322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1080 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 608277.150000 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 587 # number of replacements +system.cpu.icache.tags.tagsinuse 444.617750 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656962266 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 612266.790308 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 446.127099 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.871342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.871342 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 444.617750 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313883006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313883006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656939322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656939322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656939322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656939322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656939322 # number of overall hits -system.cpu.icache.overall_hits::total 656939322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1641 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1641 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1641 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1641 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1641 # number of overall misses -system.cpu.icache.overall_misses::total 1641 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107375484 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107375484 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107375484 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107375484 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107375484 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107375484 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656940963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656940963 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656940963 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656940963 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656940963 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656940963 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313928777 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313928777 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656962266 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656962266 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656962266 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656962266 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656962266 # number of overall hits +system.cpu.icache.overall_hits::total 656962266 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1586 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1586 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1586 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1586 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1586 # number of overall misses +system.cpu.icache.overall_misses::total 1586 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98890487 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98890487 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98890487 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98890487 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98890487 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98890487 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656963852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656963852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656963852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656963852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656963852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656963852 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65432.957952 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 65432.957952 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 65432.957952 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 65432.957952 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 65432.957952 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18112 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1654 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 94.333333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 165.400000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62352.135561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62352.135561 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17132 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.309278 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 561 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 561 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 561 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 561 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 561 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 561 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1080 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1080 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1080 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1080 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1080 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1080 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76771987 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 76771987 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76771987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 76771987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76771987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 76771987 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 587 # number of writebacks +system.cpu.icache.writebacks::total 587 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73172990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 73172990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73172990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 73172990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73172990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 73172990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71085.173148 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71085.173148 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71085.173148 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71085.173148 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68067.897674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68067.897674 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11620529 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11640215 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 14721 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11609988 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11638125 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19145 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4656609 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4712362 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16129.977996 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27367770 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4728288 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.788093 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29479829000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5227.936161 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.488571 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7534.908085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3348.645178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.319088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001128 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.459894 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.204385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 817 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 215 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2347 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1263 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9167 # 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number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45559 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45559 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144921 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1144921 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 976534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2701329 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2701329 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3677863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3678880 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3677863 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144921 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4823801 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72325395404 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72325395404 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 101500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 101500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92841040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92841040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65516000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65516000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215255322500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215255322500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65516000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 308096362500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308161878500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65516000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 308096362500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72325395404 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380487273904 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358163 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.962037 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.191935 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.191935 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.218743 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962037 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.218695 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356711 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216333 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277660 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72781.087835 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95408.043397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95408.043397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66550.529355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66550.529355 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79942.612843 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79942.612843 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84015.224275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66550.529355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84020.103572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72781.087835 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81631.427256 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283659 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34011398 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17005208 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21592 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 111772 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 111653 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14268599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 6472980 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 15222988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1281199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267519 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2748 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50996002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397794112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1397863232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 5993561 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 40004959 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003877 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062190 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34010311 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004668 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2921208 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2902417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18791 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14268046 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6464245 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12155140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5774511 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1435676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266973 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2731 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50991946 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50994677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 105984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2175190848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2175296832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8846223 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25851874 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320751 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 39849994 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 154846 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 119 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22909361 88.62% 88.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2923722 11.31% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18791 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 40004959 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21841114998 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1620000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25851874 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34009808017 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 10525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1610997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25507681990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506872492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3739654 # Transaction distribution -system.membus.trans_dist::Writeback 1637565 # Transaction distribution -system.membus.trans_dist::CleanEvict 3065415 # Transaction distribution -system.membus.trans_dist::ReadExReq 980644 # Transaction distribution -system.membus.trans_dist::ReadExResp 980644 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3739654 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14143576 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14143576 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406903232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406903232 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3698381 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1636029 # Transaction distribution +system.membus.trans_dist::CleanEvict 3003353 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 976674 # Transaction distribution +system.membus.trans_dist::ReadExResp 976674 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3698382 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13989505 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13989505 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403909376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403909376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9423278 # Request fanout histogram +system.membus.snoop_fanout::samples 9314444 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9423278 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9314444 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9423278 # Request fanout histogram -system.membus.reqLayer0.occupancy 17318873513 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25673835894 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9314444 # Request fanout histogram +system.membus.reqLayer0.occupancy 17663480706 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 25423271236 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 3fad64f8d..02c08f292 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363368 # Number of seconds simulated -sim_ticks 2363368369500 # Number of ticks simulated -final_tick 2363368369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.377030 # Number of seconds simulated +sim_ticks 2377029670500 # Number of ticks simulated +final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1008024 # Simulator instruction rate (inst/s) -host_op_rate 1086287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1548215415 # Simulator tick rate (ticks/s) -host_mem_usage 315828 # Number of bytes of host memory used -host_seconds 1526.51 # Real time elapsed on the host +host_inst_rate 970948 # Simulator instruction rate (inst/s) +host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1499891883 # Simulator tick rate (ticks/s) +host_mem_usage 316204 # Number of bytes of host memory used +host_seconds 1584.80 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124870144 # Number of bytes read from this memory -system.physmem.bytes_read::total 124909568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory +system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951096 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 16681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52835667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52852348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 16681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27652112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27652112 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27652112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 16681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52835667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80504461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4726736739 # number of cpu cycles simulated +system.cpu.numCycles 4754059341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759602 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4726736738.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4754059340.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462427 # Number of branches fetched @@ -215,19 +215,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032481 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.732103 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.741120 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164683500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.732103 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 25224281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.741120 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997007 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997007 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143052931500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143052931500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57408921000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200461852500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200461852500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200461852500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200461852500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151235084500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62883763000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214118847500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214118847500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214118847500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.738027 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.738027 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.773464 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.773464 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21991.956598 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21991.956598 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21991.954185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21991.954185 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20929.045752 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20929.045752 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33286.820150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33286.820150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23490.216928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23490.216928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23490.214351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23490.214351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135826845500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135826845500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55519772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55519772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191346617500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191346617500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191346671500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191346671500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144008998500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 60994614000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 205003612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 205003673500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 205003673500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,26 +334,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.738027 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.738027 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.773464 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.773464 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20991.956598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20991.956598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20991.960219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20991.960219 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19929.045752 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32286.820150 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22490.216928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22490.216928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22490.221153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22490.221153 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.003151 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.144337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.003151 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.251466 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.251466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 515.144337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.251535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.251535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34234000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34234000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34234000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34234000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34234000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34234000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38540000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38540000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38540000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38540000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38540000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53658.307210 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53658.307210 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53658.307210 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53658.307210 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53658.307210 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60407.523511 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 60407.523511 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 60407.523511 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 60407.523511 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,93 +405,99 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 7 # number of writebacks +system.cpu.icache.writebacks::total 7 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52658.307210 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52658.307210 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59407.523511 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59407.523511 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59407.523511 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26842 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149644895 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149644895 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3681379 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3681379 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107017 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107017 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 149644904 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149644904 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3681379 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 7 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116106326500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116143015500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3681379 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 638 # number of ReadCleanReq accesses(hits+misses) @@ -504,30 +510,30 @@ system.cpu.l2cache.demand_accesses::total 9115874 # n system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414013 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.414013 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414014 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.414014 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.965517 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161770 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161770 # 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average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52513.964074 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52513.964074 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52508.611158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52569.805195 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.591838 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52508.611158 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.214101 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.332424 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.332424 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,58 +544,58 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1021127 # number of writebacks system.cpu.l2cache.writebacks::total 1021127 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 226 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 226 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782132 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782132 # number of ReadExReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 219 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782134 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782134 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 616 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168964 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168964 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951096 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951098 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951714 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951096 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951712 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33241050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33241050000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26223000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49697293500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49697293500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26223000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82938343500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82964566500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26223000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82938343500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82964566500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951098 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951714 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38715893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 30529000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57879453500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30529000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96595346500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96625875500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30529000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96595346500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96625875500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414013 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414013 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414014 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161770 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214101 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214100 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.562565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.562565 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42569.805195 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42513.964074 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42513.964074 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42569.805195 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42508.591838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42508.611158 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214101 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.332424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49560.064935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49513.461065 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49560.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49508.198204 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.214574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18227021 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9111154 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -598,8 +604,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1063 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1063 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4702506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6326508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution @@ -607,51 +614,51 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819024192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919018 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20146039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919027 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11034901 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000201 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.014186 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20142667 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3372 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11032680 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2221 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20146039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12794889500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11034901 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12794896500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.trans_dist::ReadResp 1169580 # Transaction distribution -system.membus.trans_dist::Writeback 1021127 # Transaction distribution -system.membus.trans_dist::CleanEvict 897054 # Transaction distribution -system.membus.trans_dist::ReadExReq 782132 # Transaction distribution -system.membus.trans_dist::ReadExResp 782132 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1021127 # Transaction distribution +system.membus.trans_dist::CleanEvict 897056 # Transaction distribution +system.membus.trans_dist::ReadExReq 782134 # Transaction distribution +system.membus.trans_dist::ReadExResp 782134 # Transaction distribution system.membus.trans_dist::ReadSharedReq 1169580 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5821605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190261696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5821611 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190261824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190261824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3870264 # Request fanout histogram +system.membus.snoop_fanout::samples 3869897 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869897 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870264 # Request fanout histogram -system.membus.reqLayer0.occupancy 7969342268 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869897 # Request fanout histogram +system.membus.reqLayer0.occupancy 7968854000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9772290268 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9758570000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index c34bcec93..d16f022eb 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.882285 # Number of seconds simulated -sim_ticks 5882284743500 # Number of ticks simulated -final_tick 5882284743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.895948 # Number of seconds simulated +sim_ticks 5895947852500 # Number of ticks simulated +final_tick 5895947852500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 704974 # Simulator instruction rate (inst/s) -host_op_rate 1098413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1378571885 # Simulator tick rate (ticks/s) -host_mem_usage 317252 # Number of bytes of host memory used -host_seconds 4266.94 # Real time elapsed on the host +host_inst_rate 730138 # Simulator instruction rate (inst/s) +host_op_rate 1137621 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1431096811 # Simulator tick rate (ticks/s) +host_mem_usage 317400 # Number of bytes of host memory used +host_seconds 4119.88 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124876416 # Number of bytes read from this memory -system.physmem.bytes_read::total 124919616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124876480 # Number of bytes read from this memory +system.physmem.bytes_read::total 124919680 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65426432 # Number of bytes written to this memory -system.physmem.bytes_written::total 65426432 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65426496 # Number of bytes written to this memory +system.physmem.bytes_written::total 65426496 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1951194 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1951869 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022288 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022288 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 21229237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21236581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11122622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11122622 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11122622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 21229237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32359203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 1951195 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1951870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022289 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022289 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 21180052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21187379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11096858 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11096858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 21180052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 32284237 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11764569487 # number of cpu cycles simulated +system.cpu.numCycles 11791895705 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11764569486.998001 # Number of busy cycles +system.cpu.num_busy_cycles 11791895704.997999 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -100,19 +100,19 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.586459 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4084.587762 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58853917500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.586459 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997213 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997213 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 58914110500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587762 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 901 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2764 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses @@ -133,14 +133,14 @@ system.cpu.dcache.demand_misses::cpu.data 9112677 # n system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 142985038000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 142985038000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57429949000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57429949000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200414987000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200414987000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200414987000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200414987000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151166404000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62906975000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 214073379000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 214073379000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 214073379000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) @@ -157,14 +157,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19796.207591 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19796.207591 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30388.998041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30388.998041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21992.987022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21992.987022 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21992.987022 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20928.913656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20928.913656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33287.160677 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33287.160677 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23491.821229 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23491.821229 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,8 +173,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3682721 # number of writebacks -system.cpu.dcache.writebacks::total 3682721 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3682716 # number of writebacks +system.cpu.dcache.writebacks::total 3682716 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses @@ -183,14 +183,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 135762188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 135762188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 55540122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 55540122000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191302310000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 191302310000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 191302310000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 191302310000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 143943554000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 61017148000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 204960702000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204960702000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 204960702000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses @@ -199,24 +199,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18796.207591 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18796.207591 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29388.998041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29388.998041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20992.987022 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20992.987022 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19928.913656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32287.160677 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22491.821229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22491.821229 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements -system.cpu.icache.tags.tagsinuse 555.701425 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 555.751337 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 675 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5945529.195556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 555.701425 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.271339 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.271339 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 555.751337 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271363 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271363 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id @@ -235,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37142500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37142500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37142500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37142500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37142500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37142500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41859500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41859500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41859500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41859500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41859500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -253,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55025.925926 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55025.925926 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55025.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55025.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55025.925926 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62014.074074 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62014.074074 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62014.074074 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62014.074074 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -267,89 +267,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 10 # number of writebacks +system.cpu.icache.writebacks::total 10 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36467500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36467500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36467500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36467500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 41184500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 41184500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41184500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 41184500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54025.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54025.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54025.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54025.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61014.074074 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61014.074074 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61014.074074 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1919162 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.006197 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 14382006 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1948945 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.379380 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768623000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15266.348436 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.605704 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15844.052057 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.465892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000781 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.483522 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.950196 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1919169 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31137.283983 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 14382005 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1948952 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.379353 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 341160385000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15261.679989 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.568616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15850.035379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.465750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.483705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.950234 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 997 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 995 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27925 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149614316 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149614316 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 3682721 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3682721 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 149614323 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614323 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3682716 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 1107394 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 1107394 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054089 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6054089 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7161483 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7161483 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7161483 # number of overall hits -system.cpu.l2cache.overall_hits::total 7161483 # number of overall hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6054088 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.data 7161482 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7161482 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7161482 # number of overall hits +system.cpu.l2cache.overall_hits::total 7161482 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 782433 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 782433 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 675 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 675 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168761 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1168761 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1168762 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1168762 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 675 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1951194 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1951869 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1951195 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1951870 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1951194 # number of overall misses -system.cpu.l2cache.overall_misses::total 1951869 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41077744500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 41077744500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 35453500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 35453500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 61359978500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 61359978500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35453500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102437723000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 102473176500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35453500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102437723000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 102473176500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 3682721 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3682721 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1951195 # number of overall misses +system.cpu.l2cache.overall_misses::total 1951870 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46554770500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 40170500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 69541354000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 40170500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 116096124500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 116136295000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 40170500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 116096124500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 116136295000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 3682716 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889827 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 675 # number of ReadCleanReq accesses(hits+misses) @@ -366,26 +372,26 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.414024 system.cpu.l2cache.ReadExReq_miss_rate::total 0.414024 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161814 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161814 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.161815 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.161815 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.214119 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.214177 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214119 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214177 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.015337 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.015337 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52523.703704 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52523.703704 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.022246 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.022246 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.027666 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52523.703704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.019475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.027666 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.008946 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.851852 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.012834 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.015370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.851852 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.011275 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.015370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,60 +400,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1022288 # number of writebacks -system.cpu.l2cache.writebacks::total 1022288 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 218 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 218 # number of CleanEvict MSHR misses +system.cpu.l2cache.writebacks::writebacks 1022289 # number of writebacks +system.cpu.l2cache.writebacks::total 1022289 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 212 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 212 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782433 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 782433 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 675 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 675 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168761 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168761 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1168762 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1168762 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1951194 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1951869 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1951195 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1951870 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1951194 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1951869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33253414500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33253414500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28703500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28703500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49672368500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49672368500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28703500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82925783000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 82954486500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28703500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82925783000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 82954486500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1951195 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1951870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38730440500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 33420500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 57853734000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 33420500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96584174500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 96617595000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 33420500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96584174500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 96617595000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.414024 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.414024 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161814 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161814 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161815 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161815 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214177 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214119 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214177 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.015337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.015337 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42523.703704 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42523.703704 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.022246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.022246 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42523.703704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.019475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.027666 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.008946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.851852 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.012834 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.851852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.011275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.015370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 18221943 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9108591 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -456,8 +462,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 1002 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4705009 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6322744 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4705005 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6322745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 675 # Transaction distribution @@ -465,53 +472,53 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222850 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1360 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27333935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 27335295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43200 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 818948672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1919162 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20141105 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000050 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.007053 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 43840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818905152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 818948992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1919169 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 11032521 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000091 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.009530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 20140103 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1002 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11031519 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1002 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20141105 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12793692500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11032521 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12793697500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1169436 # Transaction distribution -system.membus.trans_dist::Writeback 1022288 # Transaction distribution +system.membus.trans_dist::ReadResp 1169437 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1022289 # Transaction distribution system.membus.trans_dist::CleanEvict 896090 # Transaction distribution system.membus.trans_dist::ReadExReq 782433 # Transaction distribution system.membus.trans_dist::ReadExResp 782433 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1169436 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5822116 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190346048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1169437 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5822119 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190346176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190346176 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3870262 # Request fanout histogram +system.membus.snoop_fanout::samples 3870249 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870262 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3870249 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870262 # Request fanout histogram -system.membus.reqLayer0.occupancy 7959418124 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3870249 # Request fanout histogram +system.membus.reqLayer0.occupancy 7959407000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9759348624 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 9759350000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 11356e644..8b18f9604 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.051911 # Nu sim_ticks 51910606500 # Number of ticks simulated final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339215 # Simulator instruction rate (inst/s) -host_op_rate 339215 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191602600 # Simulator tick rate (ticks/s) -host_mem_usage 303192 # Number of bytes of host memory used -host_seconds 270.93 # Real time elapsed on the host +host_inst_rate 362776 # Simulator instruction rate (inst/s) +host_op_rate 362776 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 204910533 # Simulator tick rate (ticks/s) +host_mem_usage 303308 # Number of bytes of host memory used +host_seconds 253.33 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # By system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation -system.physmem.totQLat 35331250 # Total ticks spent queuing -system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 35329750 # Total ticks spent queuing +system.physmem.totMemAccLat 135061000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6642.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25392.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s @@ -227,28 +227,28 @@ system.physmem_0.preEnergy 1914000 # En system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.907929 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.actBackEnergy 1735573905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619608250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500355 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907919 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271583750 # Time in different power states system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898672500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.156857 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.actBackEnergy 1825260840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540935500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783420965 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156855 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142724000 # Time in different power states system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030067000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 11441088 # Number of BP lookups system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted @@ -305,12 +305,12 @@ system.cpu.ipc 0.885205 # IP system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1447.424803 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id @@ -340,12 +340,12 @@ system.cpu.dcache.overall_misses::cpu.data 3431 # system.cpu.dcache.overall_misses::total 3431 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214034000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214034000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254246500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254246500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254246500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -364,12 +364,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74102.739726 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,12 +398,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 2230 system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168813500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168813500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168813500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -414,20 +414,20 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13850 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1640.456655 # Cycle average of tags in use system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456655 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id @@ -483,6 +483,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 13850 # number of writebacks +system.cpu.icache.writebacks::total 13850 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15816 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 15816 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 15816 # number of demand (read+write) MSHR misses @@ -509,13 +511,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890 system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2477.794194 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2477.794192 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 26614 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3666 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 7.259684 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 17.781001 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046720 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.046719 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 359.966473 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064088 # Average percentage of cache occupancy @@ -530,8 +532,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2505 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111877 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 261827 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 261827 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13850 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13850 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12647 # number of ReadCleanReq hits @@ -556,20 +560,22 @@ system.cpu.l2cache.demand_misses::total 5319 # nu system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5319 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 128817000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236600000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 236600000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236598500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 236598500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 35817000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 35817000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 236600000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 401234000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 236600000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 401234000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 236598500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164633000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 401231500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 236598500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164633000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 401231500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13850 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13850 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15815 # number of ReadCleanReq accesses(hits+misses) @@ -594,18 +600,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.294763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200316 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74937.172775 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74684.343434 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74684.343434 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75434.104155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74684.343434 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76538.354254 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75434.104155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -626,18 +632,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5319 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111626000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204918500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204918500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143123000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348041500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143123000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348041500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses @@ -650,18 +656,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 32052 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 14007 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -670,8 +676,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution @@ -679,23 +686,23 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1898560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2048128 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 18045 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 32052 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18045 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 18045 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 29983000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) @@ -719,9 +726,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5319 # Request fanout histogram -system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6412500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index cc5b93144..fdd161331 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021919 # Number of seconds simulated -sim_ticks 21919473500 # Number of ticks simulated -final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021917 # Number of seconds simulated +sim_ticks 21916940500 # Number of ticks simulated +final_tick 21916940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199769 # Simulator instruction rate (inst/s) -host_op_rate 199769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52017673 # Simulator tick rate (ticks/s) -host_mem_usage 302932 # Number of bytes of host memory used -host_seconds 421.39 # Real time elapsed on the host +host_inst_rate 209109 # Simulator instruction rate (inst/s) +host_op_rate 209109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54443336 # Simulator tick rate (ticks/s) +host_mem_usage 303052 # Number of bytes of host memory used +host_seconds 402.56 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 195776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory -system.physmem.bytes_read::total 334272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3059 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 334208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5223 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8931601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6318400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15250001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8931601 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8931601 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6318400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15250001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5223 # Number of read requests accepted +system.physmem.num_reads::total 5222 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8929714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6319130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15248844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8929714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8929714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6319130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15248844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5222 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5223 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5222 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334272 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334208 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334272 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334208 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -50,7 +50,7 @@ system.physmem.perBankRdBursts::5 223 # Pe system.physmem.perBankRdBursts::6 218 # Per bank write bursts system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts +system.physmem.perBankRdBursts::9 277 # Per bank write bursts system.physmem.perBankRdBursts::10 249 # Per bank write bursts system.physmem.perBankRdBursts::11 251 # Per bank write bursts system.physmem.perBankRdBursts::12 396 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21919378500 # Total gap between requests +system.physmem.totGap 21916845500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5223 # Read request sizes (log2) +system.physmem.readPktSize::6 5222 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 509 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 387.497674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 231.928894 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.454487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 187 21.74% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 83 9.65% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 6.74% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 4.19% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 34 3.95% 75.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 40 4.65% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.81% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 118 13.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 860 # Bytes accessed per row activation -system.physmem.totQLat 44538500 # Total ticks spent queuing -system.physmem.totMemAccLat 142469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8527.38 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 386.235157 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.364931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.000658 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253 29.45% 29.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 21.77% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 82 9.55% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 62 7.22% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 35 4.07% 72.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 38 4.42% 76.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 35 4.07% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 43 5.01% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 14.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 859 # Bytes accessed per row activation +system.physmem.totQLat 43137250 # Total ticks spent queuing +system.physmem.totMemAccLat 141049750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8260.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27277.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27010.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4358 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4196702.76 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19741800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 4197021.35 # Average gap between requests +system.physmem.pageHitRate 83.36 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3122280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1703625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19461000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 935708580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12330335250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14722266360 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.680556 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20510216250 # Time in different power states -system.physmem_0.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_0.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 912284145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12346211250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14713870140 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.536045 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20536521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 731640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 676644750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 642620250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20872800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20748000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 913464900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12349847250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14720946120 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.620322 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20542312250 # Time in different power states -system.physmem_1.memoryStateTime::REF 731900000 # Time in different power states +system.physmem_1.refreshEnergy 1431087840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 917766405 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12341402250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14716122525 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.638843 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20529652250 # Time in different power states +system.physmem_1.memoryStateTime::REF 731640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 644355250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 650829750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16112018 # Number of BP lookups -system.cpu.branchPred.condPredicted 11701868 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 926184 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8628002 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7529875 # Number of BTB hits +system.cpu.branchPred.lookups 16111441 # Number of BP lookups +system.cpu.branchPred.condPredicted 11701383 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8627871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7529688 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.272523 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1595504 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 407 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.271680 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1595490 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 408 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24062707 # DTB read hits -system.cpu.dtb.read_misses 205786 # DTB read misses +system.cpu.dtb.read_hits 24061115 # DTB read hits +system.cpu.dtb.read_misses 205797 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24268493 # DTB read accesses -system.cpu.dtb.write_hits 7162407 # DTB write hits -system.cpu.dtb.write_misses 1203 # DTB write misses +system.cpu.dtb.read_accesses 24266912 # DTB read accesses +system.cpu.dtb.write_hits 7162299 # DTB write hits +system.cpu.dtb.write_misses 1202 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7163610 # DTB write accesses -system.cpu.dtb.data_hits 31225114 # DTB hits -system.cpu.dtb.data_misses 206989 # DTB misses +system.cpu.dtb.write_accesses 7163501 # DTB write accesses +system.cpu.dtb.data_hits 31223414 # DTB hits +system.cpu.dtb.data_misses 206999 # DTB misses system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 31432103 # DTB accesses -system.cpu.itb.fetch_hits 15925407 # ITB hits +system.cpu.dtb.data_accesses 31430413 # DTB accesses +system.cpu.itb.fetch_hits 15924997 # ITB hits system.cpu.itb.fetch_misses 77 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15925484 # ITB accesses +system.cpu.itb.fetch_accesses 15925074 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 43838948 # number of cpu cycles simulated +system.cpu.numCycles 43833882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16632320 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137954260 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16112018 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9125379 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 25989721 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1930958 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 16631894 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137948476 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16111441 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9125178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25988337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1931044 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15925407 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 365179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.164819 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433135 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 15924997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 365277 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.164813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433150 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19407451 44.52% 44.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2621129 6.01% 50.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1337584 3.07% 53.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1925835 4.42% 58.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3007413 6.90% 64.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1288266 2.96% 67.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1362128 3.12% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 884292 2.03% 73.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11755833 26.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19406935 44.52% 44.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2620914 6.01% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1337526 3.07% 53.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1925752 4.42% 58.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3007087 6.90% 64.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1288201 2.96% 67.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1362015 3.12% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 884285 2.03% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11755477 26.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43589931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367527 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.146842 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12848398 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8248987 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19437203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2101434 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 953909 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2651089 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11974 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132128383 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 953909 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13970899 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4649700 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10898 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20300581 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3703944 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128750721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69632 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2039237 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1388591 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55010 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94550726 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167277672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159796203 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7481468 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43588192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367557 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.147074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12849243 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8247037 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19437084 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2100878 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953950 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2651003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11975 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132120831 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49966 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 953950 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13971462 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4650933 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10896 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20300187 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3700764 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128743195 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69669 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2038779 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1385854 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 54667 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94545107 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167268798 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159787749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7481048 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26123365 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 949 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8314647 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26912240 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8709829 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3514186 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1623457 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111857121 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99743085 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 115820 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27678694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21106490 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 894 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43589931 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.288214 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099779 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26117746 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 950 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 948 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8310352 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26910154 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8709135 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3511293 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1618997 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111850389 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1284 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99739394 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116060 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27671963 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21101257 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 895 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43588192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.288220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099837 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11253194 25.82% 25.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7641118 17.53% 43.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7479948 17.16% 60.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5719610 13.12% 73.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4459621 10.23% 83.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2975044 6.83% 90.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2026173 4.65% 95.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1169285 2.68% 98.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 865938 1.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11252596 25.82% 25.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7641941 17.53% 43.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7479961 17.16% 60.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5717065 13.12% 73.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4459781 10.23% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2974994 6.83% 90.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2026656 4.65% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169278 2.68% 98.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 865920 1.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43589931 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43588192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 482162 20.24% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482625 20.24% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 537 0.02% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 536 0.02% 20.26% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34275 1.44% 21.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12320 0.52% 22.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1010506 42.41% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 685066 28.75% 93.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 157661 6.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34267 1.44% 21.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12315 0.52% 22.21% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1010469 42.37% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 686537 28.79% 93.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 158059 6.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60678292 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 490564 0.49% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60676588 60.84% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 490565 0.49% 61.33% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2838989 2.85% 64.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115355 0.12% 64.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2438911 2.45% 66.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313691 0.31% 67.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 766049 0.77% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2839004 2.85% 64.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115354 0.12% 64.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2438838 2.45% 66.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313701 0.31% 67.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766055 0.77% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued @@ -447,84 +447,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24838081 24.90% 92.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7262827 7.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24836317 24.90% 92.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7262646 7.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99743085 # Type of FU issued -system.cpu.iq.rate 2.275216 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2382527 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229948900 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 130065304 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89786778 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15625548 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9512793 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7169302 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93776538 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8349067 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1917366 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99739394 # Type of FU issued +system.cpu.iq.rate 2.275395 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2384808 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023910 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229942315 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130052988 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89783673 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15625533 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9511643 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7169331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93775141 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8349054 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1917494 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6916042 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11056 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41363 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2208726 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6913956 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11070 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41356 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2208032 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42784 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42783 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 953909 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3616734 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 464700 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122788755 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 239982 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26912240 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8709829 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1283 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38454 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 420547 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41363 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 525246 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028202 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98432500 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24268972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1310585 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953950 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3617044 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 465078 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122781228 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 240022 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26910154 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8709135 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1284 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38486 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420890 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41356 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525280 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502970 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028250 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98428862 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24267391 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1310532 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10930351 # number of nop insts executed -system.cpu.iew.exec_refs 31432616 # number of memory reference insts executed -system.cpu.iew.exec_branches 12487704 # Number of branches executed -system.cpu.iew.exec_stores 7163644 # Number of stores executed -system.cpu.iew.exec_rate 2.245321 # Inst execution rate -system.cpu.iew.wb_sent 97645732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96956080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66985594 # num instructions producing a value -system.cpu.iew.wb_consumers 95002941 # num instructions consuming a value +system.cpu.iew.exec_nop 10929555 # number of nop insts executed +system.cpu.iew.exec_refs 31430926 # number of memory reference insts executed +system.cpu.iew.exec_branches 12487406 # Number of branches executed +system.cpu.iew.exec_stores 7163535 # Number of stores executed +system.cpu.iew.exec_rate 2.245497 # Inst execution rate +system.cpu.iew.wb_sent 97642114 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96953004 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66984387 # num instructions producing a value +system.cpu.iew.wb_consumers 95000699 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.211642 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705090 # average fanout of values written-back +system.cpu.iew.wb_rate 2.211828 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705094 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 30887581 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 30880053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914614 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39095972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.350704 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921132 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914663 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39095166 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.350752 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14698430 37.60% 37.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8547015 21.86% 59.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3864183 9.88% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1929221 4.93% 74.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1372371 3.51% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1004316 2.57% 80.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 690404 1.77% 82.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 733733 1.88% 84.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6256299 16.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14698751 37.60% 37.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8546224 21.86% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3864207 9.88% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1928510 4.93% 74.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1372257 3.51% 77.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1004424 2.57% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690640 1.77% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 733325 1.88% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6256828 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39095972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39095166 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,118 +570,118 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6256299 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155629269 # The number of ROB reads -system.cpu.rob.rob_writes 250130763 # The number of ROB writes -system.cpu.timesIdled 4629 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 249017 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6256828 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155620406 # The number of ROB reads +system.cpu.rob.rob_writes 250114778 # The number of ROB writes +system.cpu.timesIdled 4635 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.520778 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.520778 # CPI: Total CPI of All Threads -system.cpu.ipc 1.920204 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.920204 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 132982273 # number of integer regfile reads -system.cpu.int_regfile_writes 72919705 # number of integer regfile writes -system.cpu.fp_regfile_reads 6252521 # number of floating regfile reads -system.cpu.fp_regfile_writes 6155462 # number of floating regfile writes -system.cpu.misc_regfile_reads 719143 # number of misc regfile reads +system.cpu.cpi 0.520718 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520718 # CPI: Total CPI of All Threads +system.cpu.ipc 1.920426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.920426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132978272 # number of integer regfile reads +system.cpu.int_regfile_writes 72916434 # number of integer regfile writes +system.cpu.fp_regfile_reads 6252591 # number of floating regfile reads +system.cpu.fp_regfile_writes 6155476 # number of floating regfile writes +system.cpu.misc_regfile_reads 719142 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.350779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28592916 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1457.328310 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28591208 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12741.941176 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12741.180036 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.350779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355799 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.328310 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355793 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57207152 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57207152 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22099846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22099846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492613 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492613 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 57203742 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57203742 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22098137 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22098137 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492614 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28592459 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28592459 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28592459 # number of overall hits -system.cpu.dcache.overall_hits::total 28592459 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1047 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1047 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8490 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8490 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28590751 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28590751 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28590751 # number of overall hits +system.cpu.dcache.overall_hits::total 28590751 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1051 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1051 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8489 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9537 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9537 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9537 # number of overall misses -system.cpu.dcache.overall_misses::total 9537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69532500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69532500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 543709251 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 543709251 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9540 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9540 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9540 # number of overall misses +system.cpu.dcache.overall_misses::total 9540 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 72374000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 72374000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 544060252 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 544060252 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 613241751 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 613241751 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 613241751 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22100893 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22100893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 616434252 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 616434252 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 616434252 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22099188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22099188 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28601996 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28601996 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28601996 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28601996 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28600291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28600291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28600291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28600291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000048 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000333 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000333 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000333 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64301.326518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32746 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64615.749686 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32998 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 389 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 378 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.179949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.296296 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108 # number of writebacks system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 540 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6754 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6754 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7294 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7294 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7294 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 544 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6753 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6753 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7297 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7297 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7297 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 507 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1736 # number of WriteReq MSHR misses @@ -692,16 +692,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2243 system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39700000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135151495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 135151495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135653495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135653495 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 174851495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 174851495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 174851495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 176215495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176215495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 176215495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses @@ -712,134 +712,138 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9477 # number of replacements -system.cpu.icache.tags.tagsinuse 1601.339074 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15910864 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11414 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1393.977922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9476 # number of replacements +system.cpu.icache.tags.tagsinuse 1601.325936 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15910465 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11413 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1394.065101 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1601.339074 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781904 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781904 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1601.325936 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781897 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781897 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31862226 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31862226 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 15910864 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15910864 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15910864 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15910864 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15910864 # number of overall hits -system.cpu.icache.overall_hits::total 15910864 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14542 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14542 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14542 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14542 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14542 # number of overall misses -system.cpu.icache.overall_misses::total 14542 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447928500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447928500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447928500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447928500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447928500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15925406 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15925406 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15925406 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15925406 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15925406 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000913 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000913 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000913 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000913 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000913 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30802.399945 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31861405 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31861405 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15910465 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15910465 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15910465 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15910465 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15910465 # number of overall hits +system.cpu.icache.overall_hits::total 15910465 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14531 # number of overall misses +system.cpu.icache.overall_misses::total 14531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 444593500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 444593500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 444593500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 444593500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 444593500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444593500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15924996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15924996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15924996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15924996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15924996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000912 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000912 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000912 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000912 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000912 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30596.208107 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30596.208107 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30596.208107 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30596.208107 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30596.208107 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30596.208107 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 865 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 209.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 216.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3128 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3128 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3128 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3128 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3128 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3128 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11414 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11414 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11414 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11414 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11414 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 338490500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 338490500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338490500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 338490500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 9476 # number of writebacks +system.cpu.icache.writebacks::total 9476 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3118 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3118 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3118 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3118 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3118 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11413 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11413 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11413 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11413 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11413 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 335979500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 335979500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335979500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 335979500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000717 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000717 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000717 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29655.729806 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29655.729806 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29655.729806 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2397.609271 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 17951 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3579 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.015647 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2397.525400 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 17950 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3578 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.016769 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.690606 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2004.677718 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 375.240947 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.688826 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2004.597838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 375.238736 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061175 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011451 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073169 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3579 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 908 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.073167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3578 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 907 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2421 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109222 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 191659 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 191659 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 108 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108 # number of Writeback hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109192 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 191642 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 191642 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 9476 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 9476 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8355 # number of ReadCleanReq hits @@ -854,66 +858,68 @@ system.cpu.l2cache.overall_hits::cpu.data 80 # n system.cpu.l2cache.overall_hits::total 8435 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 1710 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1710 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3059 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3059 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3058 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3058 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 454 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 454 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3059 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3058 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 2164 # 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number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 233633500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 170571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 404204500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 233633500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 170571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 404204500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 108 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 108 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 5222 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 132634500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 132634500 # 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number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 9476 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 9476 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1736 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1736 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11414 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11414 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11413 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 11413 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 508 # 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number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985023 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985023 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.268004 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.268004 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267940 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267940 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.893701 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.893701 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.268004 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267940 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.382413 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.268004 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.382368 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267940 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.382413 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77270.467836 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76375.776398 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84666.299559 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77389.335631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76375.776398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78822.088725 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77389.335631 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.382368 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77564.035088 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75490.680183 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86564.977974 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77132.420529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75490.680183 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77132.420529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -924,112 +930,113 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3059 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3058 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3058 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3058 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5223 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3059 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5222 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3058 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5223 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115032500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 203043500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33898500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 203043500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 351974500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 203043500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 351974500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5222 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115534500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 200270500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34760500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 200270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 150295000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350565500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 200270500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 150295000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350565500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267940 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.382413 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.382368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267940 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.382413 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.382368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 23293 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9635 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 23291 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9634 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 11921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11413 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32302 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 36951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1336896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1487424 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13657 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 23293 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13657 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13657 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 21229500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17121000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17119500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3513 # Transaction distribution +system.membus.trans_dist::ReadResp 3512 # Transaction distribution system.membus.trans_dist::ReadExReq 1710 # Transaction distribution system.membus.trans_dist::ReadExResp 1710 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3513 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10446 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334272 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3512 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10444 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334208 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5223 # Request fanout histogram +system.membus.snoop_fanout::samples 5222 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5223 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5222 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5223 # Request fanout histogram -system.membus.reqLayer0.occupancy 6235500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5222 # Request fanout histogram +system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27428750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27427000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 13ae4452a..717d8e764 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu sim_ticks 130772642500 # Number of ticks simulated final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233615 # Simulator instruction rate (inst/s) -host_op_rate 246267 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 177290947 # Simulator tick rate (ticks/s) -host_mem_usage 321196 # Number of bytes of host memory used -host_seconds 737.62 # Real time elapsed on the host +host_inst_rate 246902 # Simulator instruction rate (inst/s) +host_op_rate 260275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187375043 # Simulator tick rate (ticks/s) +host_mem_usage 321308 # Number of bytes of host memory used +host_seconds 697.92 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -591,6 +591,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks::writebacks 2888 # number of writebacks +system.cpu.icache.writebacks::total 2888 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4685 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 4685 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 4685 # number of demand (read+write) MSHR misses @@ -638,8 +640,10 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2004 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084961 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 76658 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 76658 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 2566 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 2566 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2524 # number of ReadCleanReq hits @@ -676,8 +680,10 @@ system.cpu.l2cache.demand_miss_latency::total 294557500 system.cpu.l2cache.overall_miss_latency::cpu.inst 161329500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 133228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 294557500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 2566 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 2566 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4685 # number of ReadCleanReq accesses(hits+misses) @@ -788,8 +794,9 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution @@ -797,22 +804,22 @@ system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.083820 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.257064 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8635 91.62% 91.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 790 8.38% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6033 92.89% 92.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 462 7.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6495 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7616500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 7a60aaca0..ce097fad9 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085039 # Number of seconds simulated -sim_ticks 85038866000 # Number of ticks simulated -final_tick 85038866000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085490 # Number of seconds simulated +sim_ticks 85490431000 # Number of ticks simulated +final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124768 # Simulator instruction rate (inst/s) -host_op_rate 131526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61578459 # Simulator tick rate (ticks/s) -host_mem_usage 316956 # Number of bytes of host memory used -host_seconds 1380.98 # Real time elapsed on the host +host_inst_rate 129805 # Simulator instruction rate (inst/s) +host_op_rate 136836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64404554 # Simulator tick rate (ticks/s) +host_mem_usage 317332 # Number of bytes of host memory used +host_seconds 1327.40 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71424 # Number of bytes read from this memory -system.physmem.bytes_read::total 246336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 748 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3849 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1493905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 562943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2896746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1493905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1493905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1493905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 562943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2896746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3849 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 587136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 70784 # Number of bytes read from this memory +system.physmem.bytes_read::total 789952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 587136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 587136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 9174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1106 # Number of read requests responded to by this memory +system.physmem.num_reads::total 12343 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6867856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1544407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 827976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9240239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6867856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6867856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6867856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1544407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 827976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9240239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12344 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3849 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 12344 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246336 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 790016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246336 # Total read bytes from the system interface side +system.physmem.bytesReadSys 790016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts -system.physmem.perBankRdBursts::2 134 # Per bank write bursts -system.physmem.perBankRdBursts::3 318 # Per bank write bursts -system.physmem.perBankRdBursts::4 300 # Per bank write bursts -system.physmem.perBankRdBursts::5 302 # Per bank write bursts -system.physmem.perBankRdBursts::6 262 # Per bank write bursts -system.physmem.perBankRdBursts::7 237 # Per bank write bursts -system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 219 # Per bank write bursts -system.physmem.perBankRdBursts::10 292 # Per bank write bursts -system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 191 # Per bank write bursts -system.physmem.perBankRdBursts::13 211 # Per bank write bursts -system.physmem.perBankRdBursts::14 211 # Per bank write bursts -system.physmem.perBankRdBursts::15 194 # Per bank write bursts +system.physmem.perBankRdBursts::0 1112 # Per bank write bursts +system.physmem.perBankRdBursts::1 371 # Per bank write bursts +system.physmem.perBankRdBursts::2 5091 # Per bank write bursts +system.physmem.perBankRdBursts::3 435 # Per bank write bursts +system.physmem.perBankRdBursts::4 1954 # Per bank write bursts +system.physmem.perBankRdBursts::5 426 # Per bank write bursts +system.physmem.perBankRdBursts::6 266 # Per bank write bursts +system.physmem.perBankRdBursts::7 369 # Per bank write bursts +system.physmem.perBankRdBursts::8 265 # Per bank write bursts +system.physmem.perBankRdBursts::9 221 # Per bank write bursts +system.physmem.perBankRdBursts::10 295 # Per bank write bursts +system.physmem.perBankRdBursts::11 323 # Per bank write bursts +system.physmem.perBankRdBursts::12 197 # Per bank write bursts +system.physmem.perBankRdBursts::13 249 # Per bank write bursts +system.physmem.perBankRdBursts::14 227 # Per bank write bursts +system.physmem.perBankRdBursts::15 543 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85038722500 # Total gap between requests +system.physmem.totGap 85490422000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3849 # Read request sizes (log2) +system.physmem.readPktSize::6 12344 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,15 +94,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 10928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.357050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 198.451466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.377497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 239 30.92% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 25.10% 56.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 84 10.87% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 11.25% 78.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 29 3.75% 81.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 4.79% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 16 2.07% 88.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13 1.68% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 74 9.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 773 # Bytes accessed per row activation -system.physmem.totQLat 41463141 # Total ticks spent queuing -system.physmem.totMemAccLat 113631891 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10772.45 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 7242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 108.822977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 85.142878 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 132.567115 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5271 72.78% 72.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1523 21.03% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 185 2.55% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 87 1.20% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 0.52% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 0.36% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 0.23% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 0.25% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 77 1.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 7242 # Bytes accessed per row activation +system.physmem.totQLat 167084529 # Total ticks spent queuing +system.physmem.totMemAccLat 398534529 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 61720000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13535.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29522.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32285.69 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 9.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 9.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.83 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3069 # Number of row buffer hits during reads +system.physmem.readRowHits 5095 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.73 # Row buffer hit rate for reads +system.physmem.readRowHitRate 41.28 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22093718.50 # Average gap between requests -system.physmem.pageHitRate 79.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2789640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1522125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6925666.07 # Average gap between requests +system.physmem.pageHitRate 41.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 48527640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 26478375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 78156000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338576335 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48968955000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56882066460 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.934025 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81466129254 # Time in different power states -system.physmem_0.memoryStateTime::REF 2839460000 # Time in different power states +system.physmem_0.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17009559810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36370632750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 59116834815 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.542258 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 60400646468 # Time in different power states +system.physmem_0.memoryStateTime::REF 2854540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 731738246 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22233687032 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3031560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1654125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13525200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6199200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3382500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 17869800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5553983760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2304071955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48999213750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56875480350 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.856680 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81513506905 # Time in different power states -system.physmem_1.memoryStateTime::REF 2839460000 # Time in different power states +system.physmem_1.refreshEnergy 5583480240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3325437855 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 48374248500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 57310618095 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.413332 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 80466021414 # Time in different power states +system.physmem_1.memoryStateTime::REF 2854540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 681039595 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2165082586 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929659 # Number of BP lookups -system.cpu.branchPred.condPredicted 68408036 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6017804 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40110757 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39021888 # Number of BTB hits +system.cpu.branchPred.lookups 85927149 # Number of BP lookups +system.cpu.branchPred.condPredicted 68408695 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6018080 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40104766 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39018080 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.285344 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3703815 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81895 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.290382 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3702096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81897 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170077733 # number of cpu cycles simulated +system.cpu.numCycles 170980863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5627528 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349301730 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929659 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42725703 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158283885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12049307 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5755157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349305240 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85927149 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42720176 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158448180 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12049937 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2618 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2380 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78962015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18924 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169940212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.047263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3916 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78960236 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 19348 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 170234862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.146650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.050166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17375065 10.22% 10.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30210489 17.78% 28.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838895 18.74% 46.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90515763 53.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17669518 10.38% 10.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30211265 17.75% 28.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31838913 18.70% 46.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90515166 53.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169940212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505238 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.053777 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17579546 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17112098 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122676977 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6721861 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5849730 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11135516 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190121 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306633664 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27649172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5849730 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37767470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8469466 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 579515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108936835 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8337196 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278676031 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13415385 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3051308 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 841767 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187025 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 37328 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26465 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483141060 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1197017326 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297598208 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3006154 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 170234862 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.502554 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.042949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17700032 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17289472 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122672401 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6722857 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5850100 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135652 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 190021 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306632940 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27644957 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5850100 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37887834 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8551246 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 582035 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108933106 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8430541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278671233 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13418761 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3051568 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 841704 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2280860 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 35921 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 27095 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483139430 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196998780 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297599206 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3005965 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190164131 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23437 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13334158 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34140467 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476937 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2547302 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1809047 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264833552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45866 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214914716 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5193890 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 83243464 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219964835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169940212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264649 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017441 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190162501 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23526 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23429 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338905 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34139598 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14476816 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2548575 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1784456 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264827834 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214914585 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5192491 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 83237736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219939522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 640 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 170234862 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262459 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017804 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52857789 31.10% 31.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36101949 21.24% 52.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65794996 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13566772 7.98% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571259 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47259 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 188 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53140673 31.22% 31.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36118420 21.22% 52.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65796647 38.65% 91.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13561298 7.97% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1570362 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47243 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 219 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169940212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 170234862 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35605031 66.12% 66.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152953 0.28% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35603971 66.12% 66.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152944 0.28% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.40% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.40% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1062 0.00% 66.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1066 0.00% 66.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35733 0.07% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 238 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35746 0.07% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 240 0.00% 66.47% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 1040 0.00% 66.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34389 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14077055 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3945216 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 952 0.00% 66.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34296 0.06% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14072260 26.13% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3948482 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167357469 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918949 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167357330 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918980 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33022 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165195 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245712 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245699 0.11% 78.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460561 0.21% 78.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206706 0.10% 78.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460522 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206694 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32005826 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373316 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005177 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374016 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214914716 # Type of FU issued -system.cpu.iq.rate 1.263626 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53852922 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250578 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654863168 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 346117768 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204606131 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3953288 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2011882 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806358 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266633604 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2134034 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600995 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214914585 # Type of FU issued +system.cpu.iq.rate 1.256951 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53850162 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250565 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 655153476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 346106935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204606292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3953209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011310 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806290 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266630626 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2134121 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600828 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6244323 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7621 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6899 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832303 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6243454 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7546 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6949 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832182 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25728 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 844 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25935 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 794 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5849730 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5682254 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37001 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264895393 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5850100 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5682962 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 61282 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264889651 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34140467 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476937 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23458 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3889 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29998 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6899 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3234969 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247770 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6482739 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207531016 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721231 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7383700 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34139598 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14476816 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23448 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3916 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 54251 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6949 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3234598 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3248118 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6482716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207529725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30719767 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7384860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15975 # number of nop insts executed -system.cpu.iew.exec_refs 43860800 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937472 # Number of branches executed -system.cpu.iew.exec_stores 13139569 # Number of stores executed -system.cpu.iew.exec_rate 1.220213 # Inst execution rate -system.cpu.iew.wb_sent 206747617 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206412489 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129477272 # num instructions producing a value -system.cpu.iew.wb_consumers 221702085 # num instructions consuming a value +system.cpu.iew.exec_nop 15961 # number of nop insts executed +system.cpu.iew.exec_refs 43859608 # number of memory reference insts executed +system.cpu.iew.exec_branches 44936158 # Number of branches executed +system.cpu.iew.exec_stores 13139841 # Number of stores executed +system.cpu.iew.exec_rate 1.213760 # Inst execution rate +system.cpu.iew.wb_sent 206746993 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206412582 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129474820 # num instructions producing a value +system.cpu.iew.wb_consumers 221691878 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.213636 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584015 # average fanout of values written-back +system.cpu.iew.wb_rate 1.207226 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584031 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69549191 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69543013 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5842881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158496522 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646497 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5843212 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158791205 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.143957 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.645227 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73710350 46.51% 46.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41283484 26.05% 72.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22554549 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9626760 6.07% 92.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3551822 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2145509 1.35% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280291 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 989155 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3354602 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73988497 46.59% 46.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41295308 26.01% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22556711 14.21% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9630949 6.07% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3552216 2.24% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2148211 1.35% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1284578 0.81% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986502 0.62% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3348233 2.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158496522 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158791205 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,380 +655,382 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3354602 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 406336252 # The number of ROB reads -system.cpu.rob.rob_writes 513856795 # The number of ROB writes -system.cpu.timesIdled 3529 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 137521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3348233 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 406631126 # The number of ROB reads +system.cpu.rob.rob_writes 513844376 # The number of ROB writes +system.cpu.timesIdled 8957 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 746001 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.987085 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.987085 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013084 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013084 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218963852 # number of integer regfile reads -system.cpu.int_regfile_writes 114515225 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904259 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441612 # number of floating regfile writes -system.cpu.cc_regfile_reads 709595430 # number of cc regfile reads -system.cpu.cc_regfile_writes 229551730 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313283 # number of misc regfile reads +system.cpu.cpi 0.992327 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.992327 # CPI: Total CPI of All Threads +system.cpu.ipc 1.007733 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.007733 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218966975 # number of integer regfile reads +system.cpu.int_regfile_writes 114516229 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904204 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441504 # number of floating regfile writes +system.cpu.cc_regfile_reads 709589080 # number of cc regfile reads +system.cpu.cc_regfile_writes 229556340 # number of cc regfile writes +system.cpu.misc_regfile_reads 59312089 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72876 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.418230 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41115950 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73388 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.254401 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 506092500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.418230 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998864 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998864 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72854 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.416253 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41114439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73366 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.401807 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 507537500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.416253 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998860 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 225 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82530918 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82530918 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28729730 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28729730 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341303 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341303 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82527906 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82527906 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28728233 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28728233 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341290 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341290 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22149 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22149 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22148 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22148 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41071033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41071033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41071394 # number of overall hits -system.cpu.dcache.overall_hits::total 41071394 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89456 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89456 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22984 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22984 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 41069523 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41069523 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41069884 # number of overall hits +system.cpu.dcache.overall_hits::total 41069884 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89457 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89457 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22997 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22997 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 259 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 259 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112440 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112440 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112556 # number of overall misses -system.cpu.dcache.overall_misses::total 112556 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 857049000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 857049000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 246637999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 246637999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2309500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1103686999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1103686999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1103686999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1103686999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 112454 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112454 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112572 # number of overall misses +system.cpu.dcache.overall_misses::total 112572 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1065753500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1065753500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 241354499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 241354499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2315500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2315500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1307107999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1307107999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1307107999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1307107999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28817690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28817690 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22408 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22408 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41183473 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41183473 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41183950 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41183950 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 41181977 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41181977 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41182456 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41182456 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001859 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011558 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001860 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002731 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002731 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9580.676534 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9580.676534 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10730.856204 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10730.856204 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8916.988417 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9815.786188 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9815.786188 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9805.670058 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9805.670058 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8940.154440 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8940.154440 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11623.490485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11611.306533 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11592 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10450 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 859 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 866 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 83 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 13.494761 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.066975 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64866 # number of writebacks -system.cpu.dcache.writebacks::total 64866 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24759 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24759 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14406 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14406 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 72854 # number of writebacks +system.cpu.dcache.writebacks::total 72854 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24777 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24777 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14426 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14426 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 259 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 259 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39165 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39165 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39165 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39165 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64697 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64697 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8578 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73275 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73275 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73388 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73388 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 560382500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 560382500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86241499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86241499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 962000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 962000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 646623999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 646623999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 647585999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 647585999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000694 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000694 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 39203 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39203 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39203 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39203 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8571 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8571 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73251 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73251 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73366 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73366 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 654439000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 654439000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86279999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 86279999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 978000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 978000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 740718999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 740718999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 741696999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 741696999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001779 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001779 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8661.645826 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8661.645826 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10053.800303 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10053.800303 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8513.274336 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8824.619570 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8824.619570 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8824.140173 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8824.140173 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001781 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8504.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8504.347826 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54478 # number of replacements -system.cpu.icache.tags.tagsinuse 510.603674 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78903878 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54990 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1434.876850 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84285313500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.603674 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997273 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997273 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54401 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602972 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78901806 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54913 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1436.851128 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84733597500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602972 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157978976 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157978976 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78903878 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78903878 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78903878 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78903878 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78903878 # number of overall hits -system.cpu.icache.overall_hits::total 78903878 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 58115 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 58115 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 58115 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 58115 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 58115 # number of overall misses -system.cpu.icache.overall_misses::total 58115 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 612004953 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 612004953 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 612004953 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 612004953 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 612004953 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 612004953 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78961993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78961993 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78961993 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78961993 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78961993 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78961993 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10530.929244 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10530.929244 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10530.929244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10530.929244 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10530.929244 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 59295 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 157975329 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157975329 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78901806 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78901806 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78901806 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78901806 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78901806 # number of overall hits +system.cpu.icache.overall_hits::total 78901806 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 58402 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 58402 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 58402 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 58402 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 58402 # number of overall misses +system.cpu.icache.overall_misses::total 58402 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1157058425 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1157058425 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1157058425 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1157058425 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1157058425 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1157058425 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78960208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78960208 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78960208 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78960208 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78960208 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78960208 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000740 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000740 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000740 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000740 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000740 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000740 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19811.965772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19811.965772 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 72401 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2885 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3397 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.552860 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.313218 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 13.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3125 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3125 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3125 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3125 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3125 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3125 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54990 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54990 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54990 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54990 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54990 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54990 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 544384465 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 544384465 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 544384465 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 544384465 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 544384465 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 544384465 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9899.699309 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9899.699309 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9899.699309 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9899.699309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9899.699309 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9899.699309 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 54401 # number of writebacks +system.cpu.icache.writebacks::total 54401 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3488 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3488 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3488 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3488 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3488 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3488 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1043630451 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1043630451 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1043630451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1043630451 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1043630451 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1043630451 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000695 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000695 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000695 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000695 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9181 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9181 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9281 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9281 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1371 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1359 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2666.904370 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 230419 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3586 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 64.255159 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2148.551192 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159756 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3199 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.939356 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 701.956928 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.038958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 419.067836 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 169.840648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162775 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 265 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2293 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.016174 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202698 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3935898 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 748 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2733 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 748 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1765 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4498 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70524171 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70524171 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17163500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17163500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 124005500 # 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number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 2046 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 2046 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 236 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 236 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9175 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9175 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1827 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 11238 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 2046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 13284 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 66908651 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 17421000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 17421000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 632417000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 632417000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 129587000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 129587000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 632417000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147008000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 779425000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 632417000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147008000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 66908651 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 846333651 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027405 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027405 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.036097 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.007893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.007893 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021289 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036097 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010192 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167079 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.028227 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.028227 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.087605 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028119 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035037 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 39957.037394 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72419.831224 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72419.831224 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62471.284635 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62471.284635 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67488.258317 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67488.258317 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64272.045371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62471.284635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69050.802139 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 39957.037394 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54730.918408 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103555 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 255732 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 127373 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 649 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 649 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 119730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64866 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 51985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54990 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64740 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 156105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217502 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3519360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8848256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2111 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 257843 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.084059 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277477 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 255535 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 127274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 11941 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 51941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155926 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 373340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6464768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9219072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 15683840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 13384 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.539520 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 236169 91.59% 91.59% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 21674 8.41% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 119230 84.16% 84.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13912 9.82% 93.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 8522 6.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 257843 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192732000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82511447 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 141664 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 255022500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 82377983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110086990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110053990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3612 # Transaction distribution -system.membus.trans_dist::ReadExReq 237 # Transaction distribution -system.membus.trans_dist::ReadExResp 237 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3612 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7698 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7698 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246336 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 12107 # Transaction distribution +system.membus.trans_dist::ReadExReq 236 # Transaction distribution +system.membus.trans_dist::ReadExResp 236 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 12108 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 24687 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 24687 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 789952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 789952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3849 # Request fanout histogram +system.membus.snoop_fanout::samples 12344 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3849 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 12344 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3849 # Request fanout histogram -system.membus.reqLayer0.occupancy 5019167 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 12344 # Request fanout histogram +system.membus.reqLayer0.occupancy 15598659 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20293808 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 66476550 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index fda8a8b37..5cd25481d 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079190 # Number of seconds simulated -sim_ticks 79190347500 # Number of ticks simulated -final_tick 79190347500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079230 # Number of seconds simulated +sim_ticks 79229645000 # Number of ticks simulated +final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91850 # Simulator instruction rate (inst/s) -host_op_rate 153949 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55073733 # Simulator tick rate (ticks/s) -host_mem_usage 350132 # Number of bytes of host memory used -host_seconds 1437.90 # Real time elapsed on the host +host_inst_rate 90742 # Simulator instruction rate (inst/s) +host_op_rate 152092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54436376 # Simulator tick rate (ticks/s) +host_mem_usage 350016 # Number of bytes of host memory used +host_seconds 1455.45 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory system.physmem.bytes_read::total 345920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1955 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2788219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1579991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4368209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2788219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2788219 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2788219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1579991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4368209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5405 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue @@ -40,23 +40,23 @@ system.physmem.bytesReadSys 345920 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 296 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 299 # Per bank write bursts -system.physmem.perBankRdBursts::1 345 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 295 # Per bank write bursts +system.physmem.perBankRdBursts::1 347 # Per bank write bursts +system.physmem.perBankRdBursts::2 460 # Per bank write bursts system.physmem.perBankRdBursts::3 350 # Per bank write bursts -system.physmem.perBankRdBursts::4 340 # Per bank write bursts -system.physmem.perBankRdBursts::5 325 # Per bank write bursts -system.physmem.perBankRdBursts::6 403 # Per bank write bursts -system.physmem.perBankRdBursts::7 384 # Per bank write bursts -system.physmem.perBankRdBursts::8 342 # Per bank write bursts +system.physmem.perBankRdBursts::4 341 # Per bank write bursts +system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.perBankRdBursts::6 402 # Per bank write bursts +system.physmem.perBankRdBursts::7 383 # Per bank write bursts +system.physmem.perBankRdBursts::8 339 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::10 240 # Per bank write bursts system.physmem.perBankRdBursts::11 284 # Per bank write bursts system.physmem.perBankRdBursts::12 217 # Per bank write bursts -system.physmem.perBankRdBursts::13 467 # Per bank write bursts -system.physmem.perBankRdBursts::14 385 # Per bank write bursts -system.physmem.perBankRdBursts::15 283 # Per bank write bursts +system.physmem.perBankRdBursts::13 468 # Per bank write bursts +system.physmem.perBankRdBursts::14 388 # Per bank write bursts +system.physmem.perBankRdBursts::15 282 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79190259000 # Total gap between requests +system.physmem.totGap 79229612500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.107566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.474477 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.278271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 419 38.20% 38.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 241 21.97% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97 8.84% 69.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 5.74% 74.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 5.74% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 54 4.92% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.01% 87.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17 1.55% 88.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 121 11.03% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1097 # Bytes accessed per row activation -system.physmem.totQLat 39419500 # Total ticks spent queuing -system.physmem.totMemAccLat 140763250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation +system.physmem.totQLat 41940250 # Total ticks spent queuing +system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s @@ -214,285 +214,285 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4299 # Number of row buffer hits during reads +system.physmem.readRowHits 4297 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14651296.76 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22565400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14658577.71 # Average gap between requests +system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2473079805 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45342485250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 53017734165 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.530615 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75427842500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2644200000 # Time in different power states +system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.484152 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1114667500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3402000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1856250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19305000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5172055200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2272318965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45518583000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 52987520415 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.149179 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75723788000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2644200000 # Time in different power states +system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.185395 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 820354000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20589195 # Number of BP lookups -system.cpu.branchPred.condPredicted 20589195 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327817 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12690862 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013274 # Number of BTB hits +system.cpu.branchPred.lookups 20592907 # Number of BP lookups +system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.660820 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1440361 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16897 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158380696 # number of cpu cycles simulated +system.cpu.numCycles 158459291 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25245702 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227408017 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20589195 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13453635 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131309354 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3192879 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 16 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 1952 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 21042 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24254364 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 267325 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158174565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.377629 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95855369 60.60% 60.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4772394 3.02% 63.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3794325 2.40% 66.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4370382 2.76% 68.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4226374 2.67% 71.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4818979 3.05% 74.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4692035 2.97% 77.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3702011 2.34% 79.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31942696 20.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158174565 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129998 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435832 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15399565 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96291119 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23261573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21625869 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1596439 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336537122 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1596439 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23302832 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31798352 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30486 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35975056 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65471400 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328175182 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1530 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57810134 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7763747 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 166308 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380366291 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909731361 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600445935 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4186121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120936841 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1921 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1898 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121141633 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82738842 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29779777 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59550134 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20391789 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317761802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259358612 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 72184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96402487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 196983368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158174565 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.639699 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.523293 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40029224 25.31% 25.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47620381 30.11% 55.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33114320 20.94% 76.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17999452 11.38% 87.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10926984 6.91% 94.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4757371 3.01% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2459469 1.55% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 879282 0.56% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 388082 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158174565 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 231613 7.32% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2544922 80.40% 87.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 388680 12.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1213055 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161788642 62.38% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789415 0.30% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038152 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1187589 0.46% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64884960 25.02% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22456799 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259358612 # Type of FU issued -system.cpu.iq.rate 1.637565 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3165215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012204 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675270057 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410763185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253622616 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4859131 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3700913 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2341090 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258863930 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2446842 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18717155 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued +system.cpu.iq.rate 1.636632 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26089255 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12841 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 302099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9264060 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50731 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1596439 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12482349 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 492760 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317765871 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 91851 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82738842 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29779777 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1874 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 386744 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63788 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 302099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551455 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825732 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377187 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257295592 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64068122 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2063020 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86346654 # number of memory reference insts executed -system.cpu.iew.exec_branches 14327856 # Number of branches executed -system.cpu.iew.exec_stores 22278532 # Number of stores executed -system.cpu.iew.exec_rate 1.624539 # Inst execution rate -system.cpu.iew.wb_sent 256649039 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255963706 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204348842 # num instructions producing a value -system.cpu.iew.wb_consumers 369627181 # num instructions consuming a value +system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed +system.cpu.iew.exec_branches 14326229 # Number of branches executed +system.cpu.iew.exec_stores 22275629 # Number of stores executed +system.cpu.iew.exec_rate 1.623652 # Inst execution rate +system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204333247 # num instructions producing a value +system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616129 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552851 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 96410316 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329636 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145035845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.526267 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.955883 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45546155 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57399506 39.58% 70.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14176238 9.77% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11993202 8.27% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4061532 2.80% 91.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2861406 1.97% 93.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 912773 0.63% 94.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1078264 0.74% 95.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7006769 4.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145035845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,339 +538,345 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 7006769 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455802776 # The number of ROB reads -system.cpu.rob.rob_writes 648723400 # The number of ROB writes -system.cpu.timesIdled 2658 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 206131 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455921349 # The number of ROB reads +system.cpu.rob.rob_writes 648768029 # The number of ROB writes +system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.199207 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.199207 # CPI: Total CPI of All Threads -system.cpu.ipc 0.833884 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.833884 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448507967 # number of integer regfile reads -system.cpu.int_regfile_writes 232568909 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215393 # number of floating regfile reads -system.cpu.fp_regfile_writes 1999198 # number of floating regfile writes -system.cpu.cc_regfile_reads 102530516 # number of cc regfile reads -system.cpu.cc_regfile_writes 59523273 # number of cc regfile writes -system.cpu.misc_regfile_reads 132435302 # number of misc regfile reads +system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448461429 # number of integer regfile reads +system.cpu.int_regfile_writes 232562681 # number of integer regfile writes +system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads +system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes +system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads +system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes +system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1432.092422 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65736813 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2001 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32851.980510 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 51 # number of replacements +system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1432.092422 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 500 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131480483 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131480483 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45222500 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45222500 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513893 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513893 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65736393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65736393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65736393 # number of overall hits -system.cpu.dcache.overall_hits::total 65736393 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1010 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1010 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2848 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2848 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2848 # number of overall misses -system.cpu.dcache.overall_misses::total 2848 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129164500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129164500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 194560500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 194560500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 194560500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 194560500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45223510 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45223510 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits +system.cpu.dcache.overall_hits::total 65754783 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses +system.cpu.dcache.overall_misses::total 2767 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65739241 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65739241 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65739241 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65739241 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64748.514851 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64748.514851 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70274.483134 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70274.483134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68314.782303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68314.782303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68314.782303 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 697 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.125000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # 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number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1836 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1836 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2297 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2297 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2297 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2297 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36137000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 127182500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163319500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163319500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163319500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163319500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78388.286334 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78388.286334 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69271.514161 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69271.514161 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71101.218981 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71101.218981 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # 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Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1639.175035 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.800378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.800378 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 793 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48515969 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48515969 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24244955 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24244955 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24244955 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24244955 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24244955 # number of overall hits -system.cpu.icache.overall_hits::total 24244955 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9408 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9408 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9408 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9408 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9408 # number of overall misses -system.cpu.icache.overall_misses::total 9408 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43295.599384 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43295.599384 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 788 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2164 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7244 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7244 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7244 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7244 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7244 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7244 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 309481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 309481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 309481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 309481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 309481499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 309481499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000299 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000299 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000299 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # 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Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3873 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.172218 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2583.684571 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.256976 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2282.894376 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 304.777736 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000038 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.079008 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 989 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2616 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118195 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118429 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118429 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2610 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118164 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 118500 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 118500 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 4883 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 4883 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3494 # 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number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 35 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 35 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3495 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3536 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3495 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits +system.cpu.l2cache.overall_hits::total 3536 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 261 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 261 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1534 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1534 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3451 # 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number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6949 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1993 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8942 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6949 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1993 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8942 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996104 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996104 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.496904 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.496904 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.913232 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.913232 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.496904 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.977011 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.604292 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.496904 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.977011 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.604292 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74960.234681 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74960.234681 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75730.078238 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75730.078238 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83089.073634 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83089.073634 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76084.720681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75730.078238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76710.741688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76084.720681 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76543.470218 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -879,128 +885,129 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 296 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 296 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 261 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 261 # 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number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3454 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 5406 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3451 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1955 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3454 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5406 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6416500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6416500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99649000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99649000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226844500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226844500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226844500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130419500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 357264000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226844500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130419500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 357264000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5671500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5671500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99529500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99529500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229284000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30940500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30940500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229284000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 130470000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 359754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229284000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 130470000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 359754000 # number of overall MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996104 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996104 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.496904 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.913232 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.913232 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.604292 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.496904 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977011 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.604292 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21677.364865 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21677.364865 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64960.234681 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64960.234681 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65732.975949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65732.975949 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73089.073634 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73089.073634 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65732.975949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66710.741688 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66086.570477 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.497050 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922737 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.604563 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.497050 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.604563 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21729.885057 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21729.885057 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64882.333768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64882.333768 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66382.165605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66382.165605 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74020.334928 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74020.334928 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66382.165605 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66839.139344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66547.169811 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14563 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5344 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7704 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 4875 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 296 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 461 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19022 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4645 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 444416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 299 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 14563 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.061251 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.239799 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 263 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13671 93.87% 93.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 892 6.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 14563 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7291500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10864500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3149999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3871 # Transaction distribution -system.membus.trans_dist::UpgradeReq 296 # Transaction distribution -system.membus.trans_dist::UpgradeResp 296 # Transaction distribution +system.membus.trans_dist::ReadResp 3870 # Transaction distribution +system.membus.trans_dist::UpgradeReq 261 # Transaction distribution +system.membus.trans_dist::UpgradeResp 261 # Transaction distribution system.membus.trans_dist::ReadExReq 1534 # Transaction distribution system.membus.trans_dist::ReadExResp 1534 # Transaction distribution system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11402 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 345920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5701 # Request fanout histogram +system.membus.snoop_fanout::samples 5666 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5701 # Request fanout histogram -system.membus.reqLayer0.occupancy 6922500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5666 # Request fanout histogram +system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29231454 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |