diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/long/se | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/long/se')
21 files changed, 1384 insertions, 1388 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 011acdd4e..182ad7ea2 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.271545 # Nu sim_ticks 271544682500 # Number of ticks simulated final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105483 # Simulator instruction rate (inst/s) -host_op_rate 105483 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47591638 # Simulator tick rate (ticks/s) -host_mem_usage 219440 # Number of bytes of host memory used -host_seconds 5705.72 # Real time elapsed on the host +host_inst_rate 142205 # Simulator instruction rate (inst/s) +host_op_rate 142205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64159611 # Simulator tick rate (ticks/s) +host_mem_usage 212920 # Number of bytes of host memory used +host_seconds 4232.33 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 55134.540117 system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits @@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 14281.915545 system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks @@ -410,11 +410,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 56646.117674 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 73ec0cee6..66988a872 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133202 # Nu sim_ticks 133202081500 # Number of ticks simulated final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189557 # Simulator instruction rate (inst/s) -host_op_rate 189557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44645563 # Simulator tick rate (ticks/s) -host_mem_usage 220464 # Number of bytes of host memory used -host_seconds 2983.55 # Real time elapsed on the host +host_inst_rate 258977 # Simulator instruction rate (inst/s) +host_op_rate 258977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60995759 # Simulator tick rate (ticks/s) +host_mem_usage 213944 # Number of bytes of host memory used +host_seconds 2183.79 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory @@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7340.245420 system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 963 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 413 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.441176 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 37.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks @@ -571,14 +571,14 @@ system.cpu.l2cache.overall_misses::total 26388 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34437000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 148748500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 183185500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844656996 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 844656996 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844655000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 844655000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 34437000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 993405496 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1027842496 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 993403500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1027840500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 34437000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 993405496 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1027842496 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 993403500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1027840500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 210276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 211255 # number of ReadReq accesses(hits+misses) @@ -606,19 +606,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.056655 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35946.764092 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34892.476190 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.172864 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.172864 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39959.078437 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39959.078437 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38951.132939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38951.057299 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35946.764092 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.313645 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38951.132939 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 100996 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39064.235155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38951.057299 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 198 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1246.864198 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2.444444 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -638,14 +638,14 @@ system.cpu.l2cache.overall_mshr_misses::total 26388 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31379500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 167175000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778051996 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778051996 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 778050000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 778050000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913847496 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 945226996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 913845500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 945225000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31379500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913847496 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 945226996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 913845500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 945225000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses @@ -660,14 +660,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.056655 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.212508 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36808.118081 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.118081 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.334849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35935.725521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35820.259209 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 20eccd335..c6b30ffc7 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.163008 # Nu sim_ticks 163008222000 # Number of ticks simulated final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104701 # Simulator instruction rate (inst/s) -host_op_rate 110635 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29939476 # Simulator tick rate (ticks/s) -host_mem_usage 234836 # Number of bytes of host memory used -host_seconds 5444.59 # Real time elapsed on the host +host_inst_rate 178133 # Simulator instruction rate (inst/s) +host_op_rate 188229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50937760 # Simulator tick rate (ticks/s) +host_mem_usage 228580 # Number of bytes of host memory used +host_seconds 3200.15 # Real time elapsed on the host sim_insts 570052710 # Number of instructions simulated sim_ops 602360916 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory @@ -502,12 +502,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 8537.033204 system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28514592 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 54626 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3014 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9460.714001 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 1000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.124088 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks @@ -595,14 +595,14 @@ system.cpu.l2cache.overall_misses::total 28446 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27249500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 189324500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 216574000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974455801 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 974455801 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 974356500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 974356500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 27249500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1163780301 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1191029801 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1163681000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1190930500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 27249500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1163780301 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1191029801 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1163681000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1190930500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 197352 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 198170 # number of ReadReq accesses(hits+misses) @@ -630,19 +630,19 @@ system.cpu.l2cache.overall_miss_rate::total 0.063881 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 34607.542346 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43918.144988 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43918.144988 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43913.669551 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43913.669551 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 41869.851684 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 41866.360824 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36092.052980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42027.384385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 41869.851684 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 13672801 # number of cycles access was blocked +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 42023.798346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 41866.360824 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 27147 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 2920 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4682.466096 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 9.296918 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed @@ -671,14 +671,14 @@ system.cpu.l2cache.overall_mshr_misses::total 28433 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 197057000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 900047801 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 900047801 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 899948500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 899948500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24797500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072307301 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1097104801 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1072208000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1097005500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24797500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072307301 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1097104801 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1072208000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1097005500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses @@ -693,14 +693,14 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.063852 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40564.620561 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40564.620561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40560.145123 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40560.145123 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38736.626725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38585.615341 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38733.039520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38582.122885 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index b8b444d29..293c634b6 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.386987 # Nu sim_ticks 386986985000 # Number of ticks simulated final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135169 # Simulator instruction rate (inst/s) -host_op_rate 135595 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37331500 # Simulator tick rate (ticks/s) -host_mem_usage 223688 # Number of bytes of host memory used -host_seconds 10366.23 # Real time elapsed on the host +host_inst_rate 190632 # Simulator instruction rate (inst/s) +host_op_rate 191233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52649747 # Simulator tick rate (ticks/s) +host_mem_usage 217240 # Number of bytes of host memory used +host_seconds 7350.22 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory @@ -453,11 +453,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 6577.376711 system.cpu.dcache.demand_avg_miss_latency::total 6577.376711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 6577.376711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b0555a54b..0c2881972 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025432 # Nu sim_ticks 25432499000 # Number of ticks simulated final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141358 # Simulator instruction rate (inst/s) -host_op_rate 142373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39681246 # Simulator tick rate (ticks/s) -host_mem_usage 367916 # Number of bytes of host memory used -host_seconds 640.92 # Real time elapsed on the host +host_inst_rate 191631 # Simulator instruction rate (inst/s) +host_op_rate 193007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53793580 # Simulator tick rate (ticks/s) +host_mem_usage 361656 # Number of bytes of host memory used +host_seconds 472.78 # Real time elapsed on the host sim_insts 90599358 # Number of instructions simulated sim_ops 91249911 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory @@ -494,11 +494,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 7044.800890 system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 12648 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 1374.477220 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.940175 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 5a3a68b8e..b5e0cf470 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201852 # Nu sim_ticks 201852280500 # Number of ticks simulated final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114620 # Simulator instruction rate (inst/s) -host_op_rate 129121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45458575 # Simulator tick rate (ticks/s) -host_mem_usage 239092 # Number of bytes of host memory used -host_seconds 4440.36 # Real time elapsed on the host +host_inst_rate 135871 # Simulator instruction rate (inst/s) +host_op_rate 153059 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53886430 # Simulator tick rate (ticks/s) +host_mem_usage 232836 # Number of bytes of host memory used +host_seconds 3745.88 # Real time elapsed on the host sim_insts 508955133 # Number of instructions simulated sim_ops 573341693 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory @@ -162,9 +162,9 @@ system.cpu.iq.issued_per_cycle::samples 402291353 # Nu system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle @@ -503,11 +503,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 12757.829762 system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index eb9886f3f..8ceb40825 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.427481 # Number of seconds simulated -sim_ticks 427481057500 # Number of ticks simulated -final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 427481054500 # Number of ticks simulated +final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54913 # Simulator instruction rate (inst/s) -host_op_rate 101540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28388930 # Simulator tick rate (ticks/s) -host_mem_usage 267916 # Number of bytes of host memory used -host_seconds 15058.02 # Real time elapsed on the host +host_inst_rate 86006 # Simulator instruction rate (inst/s) +host_op_rate 159036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44463827 # Simulator tick rate (ticks/s) +host_mem_usage 261156 # Number of bytes of host memory used +host_seconds 9614.13 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988699 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory @@ -24,18 +24,18 @@ system.physmem.num_reads::total 434860 # Nu system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 854962116 # number of cpu cycles simulated +system.cpu.numCycles 854962110 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups @@ -52,16 +52,16 @@ system.cpu.fetch.Branches 221542687 # Nu system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total) @@ -73,11 +73,11 @@ system.cpu.fetch.rateDist::8 188811034 22.28% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing @@ -85,7 +85,7 @@ system.cpu.decode.DecodedInsts 2233248714 # Nu system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking @@ -114,11 +114,11 @@ system.cpu.iq.iqSquashedInstsIssued 951947 # Nu system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle @@ -130,7 +130,7 @@ system.cpu.iq.issued_per_cycle::8 1920111 0.23% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available @@ -203,7 +203,7 @@ system.cpu.iq.FU_type_0::total 1834774344 # Ty system.cpu.iq.rate 2.146030 # Inst issue rate system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads @@ -223,7 +223,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 10593 # system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch @@ -256,11 +256,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle @@ -272,7 +272,7 @@ system.cpu.commit.committed_per_cycle::8 68515952 8.89% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 770294258 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -285,7 +285,7 @@ system.cpu.commit.int_insts 1528317557 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2788262369 # The number of ROB reads +system.cpu.rob.rob_reads 2788262363 # The number of ROB reads system.cpu.rob.rob_writes 4250388650 # The number of ROB writes system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling @@ -302,12 +302,12 @@ system.cpu.fp_regfile_reads 9183 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads system.cpu.icache.replacements 5688 # number of replacements -system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1035.102624 # Cycle average of tags in use system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1035.102624 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits @@ -322,12 +322,12 @@ system.cpu.icache.demand_misses::cpu.inst 199745 # n system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses system.cpu.icache.overall_misses::total 199745 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1237681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1237681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1237681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1237681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1237681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses @@ -340,12 +340,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001113 system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.305289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6196.305289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6196.305289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6196.305289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,24 +366,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 198172 system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804804500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804804500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804804500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804804500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804804500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804804500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804803500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804803500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804803500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804803500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804803500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804803500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.136286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.136286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2529003 # number of replacements system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use @@ -410,14 +410,14 @@ system.cpu.dcache.demand_misses::cpu.data 3725145 # n system.cpu.dcache.demand_misses::total 3725145 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3725145 # number of overall misses system.cpu.dcache.overall_misses::total 3725145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892922500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29892922500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960185000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16960185000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46853107500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46853107500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46853107500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46853107500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892904500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29892904500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960182000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16960182000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46853086500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46853086500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46853086500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46853086500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses) @@ -434,14 +434,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009000 system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12577.525841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12577.525841 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.047567 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.047567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.936922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.936922 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12577.520204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12577.520204 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -468,14 +468,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2723946 system.cpu.dcache.demand_mshr_misses::total 2723946 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2723946 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2723946 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993049600 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993049600 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994697002 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994697002 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987746602 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25987746602 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987746602 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25987746602 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993099500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994695000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994695000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987794500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25987794500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987794500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25987794500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006658 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006658 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006445 # mshr miss rate for WriteReq accesses @@ -484,24 +484,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006581 system.cpu.dcache.demand_mshr_miss_rate::total 0.006581 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006581 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.759555 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.759555 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.963852 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.963852 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.787865 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.787865 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.961769 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.961769 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 408687 # number of replacements -system.cpu.l2cache.tagsinuse 29306.187052 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 29306.187032 # Cycle average of tags in use system.cpu.l2cache.total_refs 3611934 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 21100.579684 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 8058.630755 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy @@ -612,18 +612,18 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 3470 system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068613966 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957207430 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7068631930 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5878812896 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5878812896 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445527430 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556951930 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445527430 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556951930 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses @@ -638,18 +638,18 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.478885 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.282671 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.591770 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31036.516957 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31036.516957 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 63bbc9ea5..c1850cccb 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.141181 # Nu sim_ticks 141180939500 # Number of ticks simulated final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88431 # Simulator instruction rate (inst/s) -host_op_rate 88431 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31316360 # Simulator tick rate (ticks/s) -host_mem_usage 225476 # Number of bytes of host memory used -host_seconds 4508.22 # Real time elapsed on the host +host_inst_rate 139974 # Simulator instruction rate (inst/s) +host_op_rate 139974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49569488 # Simulator tick rate (ticks/s) +host_mem_usage 218836 # Number of bytes of host memory used +host_seconds 2848.14 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory @@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 49040.669856 system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 90 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 52755.480984 system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 90.156266 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 9ec4bfca0..f5e3faa91 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.080354 # Nu sim_ticks 80354154000 # Number of ticks simulated final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172564 # Simulator instruction rate (inst/s) -host_op_rate 172564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36920064 # Simulator tick rate (ticks/s) -host_mem_usage 226504 # Number of bytes of host memory used -host_seconds 2176.44 # Real time elapsed on the host +host_inst_rate 221188 # Simulator instruction rate (inst/s) +host_op_rate 221188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47323038 # Simulator tick rate (ticks/s) +host_mem_usage 219864 # Number of bytes of host memory used +host_seconds 1697.99 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory @@ -473,11 +473,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 31189.659864 system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -607,11 +607,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 38052.307692 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 3500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 8292ba84e..908860e43 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.070882 # Nu sim_ticks 70882487500 # Number of ticks simulated final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119635 # Simulator instruction rate (inst/s) -host_op_rate 152946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31056895 # Simulator tick rate (ticks/s) -host_mem_usage 243232 # Number of bytes of host memory used -host_seconds 2282.34 # Real time elapsed on the host +host_inst_rate 146290 # Simulator instruction rate (inst/s) +host_op_rate 187023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37976354 # Simulator tick rate (ticks/s) +host_mem_usage 236976 # Number of bytes of host memory used +host_seconds 1866.49 # Real time elapsed on the host sim_insts 273048441 # Number of instructions simulated sim_ops 349076165 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory @@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 32843.594242 system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 626 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.125000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 1c7f4cd18..76fb7aa81 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.644314 # Nu sim_ticks 644314104000 # Number of ticks simulated final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127860 # Simulator instruction rate (inst/s) -host_op_rate 127860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45189117 # Simulator tick rate (ticks/s) -host_mem_usage 230524 # Number of bytes of host memory used -host_seconds 14258.17 # Real time elapsed on the host +host_inst_rate 164548 # Simulator instruction rate (inst/s) +host_op_rate 164548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58155841 # Simulator tick rate (ticks/s) +host_mem_usage 223896 # Number of bytes of host memory used +host_seconds 11079.10 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory @@ -488,12 +488,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 33793.696324 system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.904762 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 43 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks @@ -624,11 +624,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 35105.146381 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 35105.146381 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 105500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 211 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5275 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.550000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 70391a345..c008b73ab 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.659244 # Nu sim_ticks 659244465000 # Number of ticks simulated final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88407 # Simulator instruction rate (inst/s) -host_op_rate 120399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42099861 # Simulator tick rate (ticks/s) -host_mem_usage 243836 # Number of bytes of host memory used -host_seconds 15659.07 # Real time elapsed on the host +host_inst_rate 153116 # Simulator instruction rate (inst/s) +host_op_rate 208523 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72914339 # Simulator tick rate (ticks/s) +host_mem_usage 237584 # Number of bytes of host memory used +host_seconds 9041.36 # Real time elapsed on the host sim_insts 1384375635 # Number of instructions simulated sim_ops 1885330387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory @@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 1f592bc6b..7d4bfa05d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.046793 # Nu sim_ticks 46793182500 # Number of ticks simulated final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59681 # Simulator instruction rate (inst/s) -host_op_rate 59681 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31612654 # Simulator tick rate (ticks/s) -host_mem_usage 227600 # Number of bytes of host memory used -host_seconds 1480.20 # Real time elapsed on the host +host_inst_rate 131801 # Simulator instruction rate (inst/s) +host_op_rate 131801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69813482 # Simulator tick rate (ticks/s) +host_mem_usage 220956 # Number of bytes of host memory used +host_seconds 670.26 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 15833.265655 system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits @@ -277,11 +277,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index dcb5671a4..9eadbf92f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.021083 # Nu sim_ticks 21083079000 # Number of ticks simulated final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162660 # Simulator instruction rate (inst/s) -host_op_rate 162660 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43087037 # Simulator tick rate (ticks/s) -host_mem_usage 228624 # Number of bytes of host memory used -host_seconds 489.31 # Real time elapsed on the host +host_inst_rate 198104 # Simulator instruction rate (inst/s) +host_op_rate 198104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52475767 # Simulator tick rate (ticks/s) +host_mem_usage 221996 # Number of bytes of host memory used +host_seconds 401.77 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory @@ -480,12 +480,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170 system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 181 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 51 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.066667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks @@ -614,11 +614,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 39898.128604 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 75 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3409.090909 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6.818182 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3a7d388e3..fe9fd6111 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023747 # Nu sim_ticks 23747395500 # Number of ticks simulated final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107822 # Simulator instruction rate (inst/s) -host_op_rate 153002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36101670 # Simulator tick rate (ticks/s) -host_mem_usage 242616 # Number of bytes of host memory used -host_seconds 657.79 # Real time elapsed on the host +host_inst_rate 142184 # Simulator instruction rate (inst/s) +host_op_rate 201762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47606944 # Simulator tick rate (ticks/s) +host_mem_usage 237384 # Number of bytes of host memory used +host_seconds 498.82 # Real time elapsed on the host sim_insts 70924309 # Number of instructions simulated sim_ops 100643556 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory @@ -504,11 +504,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9df6e0f0a..0c8fe7df6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.983203 # Nu sim_ticks 983202553500 # Number of ticks simulated final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94547 # Simulator instruction rate (inst/s) -host_op_rate 94547 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51082649 # Simulator tick rate (ticks/s) -host_mem_usage 219392 # Number of bytes of host memory used -host_seconds 19247.29 # Real time elapsed on the host +host_inst_rate 119503 # Simulator instruction rate (inst/s) +host_op_rate 119503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64565869 # Simulator tick rate (ticks/s) +host_mem_usage 212872 # Number of bytes of host memory used +host_seconds 15227.90 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -181,11 +181,11 @@ system.cpu.icache.demand_avg_miss_latency::total 54537.140204 system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits @@ -276,12 +276,12 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 25004.469885 system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks @@ -407,11 +407,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 52782.351713 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index b5afab091..d7e4bc3be 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.601884 # Number of seconds simulated -sim_ticks 601884201500 # Number of ticks simulated -final_tick 601884201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.601742 # Number of seconds simulated +sim_ticks 601741522500 # Number of ticks simulated +final_tick 601741522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130981 # Simulator instruction rate (inst/s) -host_op_rate 130981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45411041 # Simulator tick rate (ticks/s) -host_mem_usage 220420 # Number of bytes of host memory used -host_seconds 13254.14 # Real time elapsed on the host +host_inst_rate 165987 # Simulator instruction rate (inst/s) +host_op_rate 165987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57533745 # Simulator tick rate (ticks/s) +host_mem_usage 213900 # Number of bytes of host memory used +host_seconds 10458.93 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138169152 # Number of bytes read from this memory -system.physmem.bytes_read::total 138230976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67208000 # Number of bytes written to this memory -system.physmem.bytes_written::total 67208000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2158893 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2159859 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050125 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050125 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 102717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 229561021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 229663739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 102717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 102717 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 111662675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 111662675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 111662675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 102717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 229561021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 341326414 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138172352 # Number of bytes read from this memory +system.physmem.bytes_read::total 138234112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67207424 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2158943 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2159908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050116 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050116 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 102635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 229620770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 229723406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 102635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 102635 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 111688194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 111688194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 111688194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 102635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 229620770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 341411600 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 610881152 # DTB read hits -system.cpu.dtb.read_misses 10794363 # DTB read misses +system.cpu.dtb.read_hits 610863506 # DTB read hits +system.cpu.dtb.read_misses 10801691 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 621675515 # DTB read accesses -system.cpu.dtb.write_hits 207421516 # DTB write hits -system.cpu.dtb.write_misses 6613595 # DTB write misses +system.cpu.dtb.read_accesses 621665197 # DTB read accesses +system.cpu.dtb.write_hits 207455295 # DTB write hits +system.cpu.dtb.write_misses 6623437 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 214035111 # DTB write accesses -system.cpu.dtb.data_hits 818302668 # DTB hits -system.cpu.dtb.data_misses 17407958 # DTB misses +system.cpu.dtb.write_accesses 214078732 # DTB write accesses +system.cpu.dtb.data_hits 818318801 # DTB hits +system.cpu.dtb.data_misses 17425128 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 835710626 # DTB accesses -system.cpu.itb.fetch_hits 399285601 # ITB hits -system.cpu.itb.fetch_misses 63 # ITB misses +system.cpu.dtb.data_accesses 835743929 # DTB accesses +system.cpu.itb.fetch_hits 399244233 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 399285664 # ITB accesses +system.cpu.itb.fetch_accesses 399244290 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +67,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1203768404 # number of cpu cycles simulated +system.cpu.numCycles 1203483046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 378661928 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 290874773 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 18850616 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 264881962 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 260540807 # Number of BTB hits +system.cpu.BPredUnit.lookups 378630674 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 290853975 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 18842896 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 264245889 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 260518236 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 25136701 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6159 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 410735894 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3138932224 # Number of instructions fetch has processed -system.cpu.fetch.Branches 378661928 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 285677508 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 572729793 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 132567804 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 108566970 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 399285601 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10259418 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1199047347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.617855 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.169243 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 25134989 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6201 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 410689836 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3138690905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 378630674 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 285653225 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 572677806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 132533954 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 108403122 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 399244233 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10255002 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1198760050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.618281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.169328 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 626317554 52.23% 52.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42572057 3.55% 55.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22209930 1.85% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 40806426 3.40% 61.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 126340363 10.54% 71.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 63640386 5.31% 76.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40565082 3.38% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30197237 2.52% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 206398312 17.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 626082244 52.23% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42560367 3.55% 55.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22212227 1.85% 57.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 40796625 3.40% 61.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126320083 10.54% 71.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 63645436 5.31% 76.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 40565089 3.38% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30205669 2.52% 82.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 206372310 17.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1199047347 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.314564 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.607588 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 438876145 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95310008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542739947 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15108786 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 107012461 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 60159953 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 978 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3060008107 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 1198760050 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.314612 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.608006 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 438814843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95153182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542714056 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15090918 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 106987051 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 60150241 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1010 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3059802509 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 107012461 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 459450274 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50562010 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 5044 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 536182540 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 45835018 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2978218339 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 422353 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1724352 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 41499068 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2227532255 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3846059420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3844664884 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1394536 # Number of floating rename lookups +system.cpu.rename.SquashCycles 106987051 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 459387866 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50448288 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5147 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 536142849 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 45788849 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2978016816 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 421943 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1715322 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41464029 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2227365150 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3845813324 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3844419965 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1393359 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 851329292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 212 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 95534350 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 674543157 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 250165929 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60031674 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34641501 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2674307937 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2477606155 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3178446 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 927538702 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 394492556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1199047347 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.066312 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.969260 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 851162187 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 215 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 95471202 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 674494217 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 250159031 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59771171 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34263403 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2674166611 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 189 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2477607357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3173205 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 927397839 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 394299937 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 160 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1198760050 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.969624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 374590988 31.24% 31.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 190702947 15.90% 47.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 181537142 15.14% 62.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153695699 12.82% 75.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 136730734 11.40% 86.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 80190081 6.69% 93.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 61698536 5.15% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14532490 1.21% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5368730 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 374466356 31.24% 31.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 190640446 15.90% 47.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 181417957 15.13% 62.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153622544 12.82% 75.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 136730069 11.41% 86.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80254846 6.69% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 61695164 5.15% 98.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14563469 1.21% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5369199 0.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1199047347 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1198760050 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2248592 11.88% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12188219 64.39% 76.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4492341 23.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2251857 11.87% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12201284 64.32% 76.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4515049 23.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1617099394 65.27% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1617068630 65.27% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 297 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 41 0.00% 65.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued @@ -228,84 +228,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 639262195 25.80% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 221243949 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 639258763 25.80% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 221279320 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2477606155 # Type of FU issued -system.cpu.iq.rate 2.058208 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18929152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007640 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6174384179 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3600600502 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2375948293 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1983076 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1349305 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 869249 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2495560681 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 974626 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 56273066 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2477607357 # Type of FU issued +system.cpu.iq.rate 2.058697 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18968190 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6174132781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3600319262 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2375945234 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1983378 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1347629 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 869060 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2495600765 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 974782 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 56278777 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 229947494 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 250240 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 104617 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 89437427 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 229898554 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 250139 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 103830 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 89430529 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 223 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 81293 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 234 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 81236 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 107012461 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18493719 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 964338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2816222496 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17539215 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 674543157 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 250165929 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 222443 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13054 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 104617 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 13266110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8853005 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 22119115 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2426782897 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 621677051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 50823258 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 106987051 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18488263 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 963433 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2816062244 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17529415 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 674494217 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 250159031 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 189 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 221508 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12923 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 103830 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 13260228 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8848776 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 22109004 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2426798028 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 621666775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 50809329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 141914378 # number of nop insts executed -system.cpu.iew.exec_refs 835712197 # number of memory reference insts executed -system.cpu.iew.exec_branches 297017404 # Number of branches executed -system.cpu.iew.exec_stores 214035146 # Number of stores executed -system.cpu.iew.exec_rate 2.015988 # Inst execution rate -system.cpu.iew.wb_sent 2405357276 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2376817542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1361466858 # num instructions producing a value -system.cpu.iew.wb_consumers 1724557006 # num instructions consuming a value +system.cpu.iew.exec_nop 141895444 # number of nop insts executed +system.cpu.iew.exec_refs 835745555 # number of memory reference insts executed +system.cpu.iew.exec_branches 297016780 # Number of branches executed +system.cpu.iew.exec_stores 214078780 # Number of stores executed +system.cpu.iew.exec_rate 2.016479 # Inst execution rate +system.cpu.iew.wb_sent 2405369179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2376814294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1361493757 # num instructions producing a value +system.cpu.iew.wb_consumers 1724612513 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.974481 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.789459 # average fanout of values written-back +system.cpu.iew.wb_rate 1.974946 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.789449 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 756599351 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 756436478 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 18849719 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1092034886 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.666412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.514594 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 18841975 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1091772999 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.666812 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.514787 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 565812226 51.81% 51.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 181963708 16.66% 68.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 91431923 8.37% 76.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53287438 4.88% 81.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36685843 3.36% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 28834990 2.64% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 22491649 2.06% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22994830 2.11% 91.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 88532279 8.11% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 565636558 51.81% 51.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 181878211 16.66% 68.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 91372107 8.37% 76.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53285897 4.88% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 36714852 3.36% 85.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 28908245 2.65% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22459323 2.06% 89.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22999009 2.11% 91.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 88518797 8.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1092034886 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1091772999 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +316,70 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 88532279 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 88518797 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3494102884 # The number of ROB reads -system.cpu.rob.rob_writes 5259875951 # The number of ROB writes -system.cpu.timesIdled 272602 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4721057 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3493691606 # The number of ROB reads +system.cpu.rob.rob_writes 5259524652 # The number of ROB writes +system.cpu.timesIdled 273067 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4722996 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.693397 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.693397 # CPI: Total CPI of All Threads -system.cpu.ipc 1.442174 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.442174 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3262431101 # number of integer regfile reads -system.cpu.int_regfile_writes 1906790236 # number of integer regfile writes -system.cpu.fp_regfile_reads 51143 # number of floating regfile reads -system.cpu.fp_regfile_writes 554 # number of floating regfile writes +system.cpu.cpi 0.693233 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.693233 # CPI: Total CPI of All Threads +system.cpu.ipc 1.442516 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.442516 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3262496367 # number of integer regfile reads +system.cpu.int_regfile_writes 1906751993 # number of integer regfile writes +system.cpu.fp_regfile_reads 51073 # number of floating regfile reads +system.cpu.fp_regfile_writes 575 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 770.355491 # Cycle average of tags in use -system.cpu.icache.total_refs 399284112 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 413337.590062 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 769.815211 # Cycle average of tags in use +system.cpu.icache.total_refs 399242763 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 413723.070466 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 770.355491 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.376150 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.376150 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 399284112 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 399284112 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 399284112 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 399284112 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 399284112 # number of overall hits -system.cpu.icache.overall_hits::total 399284112 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses -system.cpu.icache.overall_misses::total 1489 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 51254000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 51254000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 51254000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 51254000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 51254000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 51254000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 399285601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 399285601 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 399285601 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 399285601 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 399285601 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 399285601 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 769.815211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375886 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375886 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 399242763 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 399242763 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 399242763 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 399242763 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 399242763 # number of overall hits +system.cpu.icache.overall_hits::total 399242763 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1470 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1470 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1470 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1470 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1470 # number of overall misses +system.cpu.icache.overall_misses::total 1470 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 50742000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 50742000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 50742000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 50742000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 50742000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 50742000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 399244233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 399244233 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 399244233 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 399244233 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 399244233 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 399244233 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34421.759570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34421.759570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34421.759570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34421.759570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34518.367347 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34518.367347 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34518.367347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34518.367347 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,299 +388,299 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 523 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 523 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 523 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 523 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 523 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36312000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 36312000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36312000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 36312000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36312000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 36312000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 505 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 505 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 505 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36236500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36236500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36236500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36236500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36236500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36236500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37590.062112 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37590.062112 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37590.062112 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37590.062112 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37550.777202 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37550.777202 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37550.777202 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 37550.777202 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176158 # number of replacements -system.cpu.dcache.tagsinuse 4085.718246 # Cycle average of tags in use -system.cpu.dcache.total_refs 700542179 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180254 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 76.309673 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9176269 # number of replacements +system.cpu.dcache.tagsinuse 4085.715808 # Cycle average of tags in use +system.cpu.dcache.total_refs 700520059 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180365 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 76.306341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 5701764000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4085.718246 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997490 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997490 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 544702732 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 544702732 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155839442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155839442 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 700542174 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 700542174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 700542174 # number of overall hits -system.cpu.dcache.overall_hits::total 700542174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9892344 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9892344 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4889060 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4889060 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 4085.715808 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997489 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997489 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 544680569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 544680569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155839486 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155839486 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 700520055 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 700520055 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 700520055 # number of overall hits +system.cpu.dcache.overall_hits::total 700520055 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9891173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9891173 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4889016 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4889016 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 14781404 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 14781404 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 14781404 # number of overall misses -system.cpu.dcache.overall_misses::total 14781404 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 135375372000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 135375372000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128493017298 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128493017298 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 14780189 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 14780189 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 14780189 # number of overall misses +system.cpu.dcache.overall_misses::total 14780189 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 135366568000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 135366568000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128487056395 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128487056395 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 42500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 42500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 263868389298 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 263868389298 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 263868389298 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 263868389298 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 554595076 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 554595076 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 263853624395 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 263853624395 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 263853624395 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 263853624395 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 554571742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 554571742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 715323578 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 715323578 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 715323578 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 715323578 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017837 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017837 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 715300244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 715300244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 715300244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 715300244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017836 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017836 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030418 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.030418 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.020664 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.020664 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.020664 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.020664 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13684.862961 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13684.862961 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26281.742768 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26281.742768 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.020663 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.020663 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.020663 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.020663 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13685.593003 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13685.593003 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26280.760054 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26280.760054 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 42500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 42500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17851.375235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.375235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17851.375235 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 54186258 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2148410500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 10025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65117 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5405.113017 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 32993.081684 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17851.843735 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17851.843735 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17851.843735 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17851.843735 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105233 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4296872 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9989 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65119 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.534888 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 65.984920 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3416507 # number of writebacks -system.cpu.dcache.writebacks::total 3416507 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2595838 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2595838 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005313 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3005313 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5601151 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5601151 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5601151 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5601151 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883747 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883747 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3416489 # number of writebacks +system.cpu.dcache.writebacks::total 3416489 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2594561 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2594561 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3005264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3005264 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5599825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5599825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5599825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5599825 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296612 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296612 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883752 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1883752 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9180253 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9180253 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9180253 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9180253 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63651885000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63651885000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32596175026 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 32596175026 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9180364 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180364 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180364 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180364 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63655163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 63655163500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 32590773423 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 32590773423 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 40500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 40500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96248060026 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96248060026 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96248060026 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96248060026 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013156 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96245936923 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 96245936923 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96245936923 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 96245936923 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013157 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011720 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011720 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.012834 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012834 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012834 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.611685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.611685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17303.902820 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17303.902820 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8723.934273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8723.934273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17300.989421 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17300.989421 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 40500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 40500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10484.249184 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10484.249184 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10483.891153 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10483.891153 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2143403 # number of replacements -system.cpu.l2cache.tagsinuse 30886.044156 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8540338 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2173098 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.930029 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 106236291500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14425.723577 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 30.926005 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16429.394573 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440238 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000944 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.501385 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.942567 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5920206 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5920206 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3416507 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3416507 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1101155 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1101155 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7021361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7021361 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7021361 # number of overall hits -system.cpu.l2cache.overall_hits::total 7021361 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1376292 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1377258 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 782601 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 782601 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2158893 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2159859 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2158893 # number of overall misses -system.cpu.l2cache.overall_misses::total 2159859 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35332000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49455599500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 49490931500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28985235156 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 28985235156 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35332000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 78440834656 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 78476166656 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35332000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 78440834656 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 78476166656 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7296498 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7297464 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3416507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3416507 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883756 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1883756 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9180254 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9181220 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9180254 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9181220 # number of overall (read+write) accesses +system.cpu.l2cache.replacements 2143480 # number of replacements +system.cpu.l2cache.tagsinuse 30885.644548 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8540352 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2173177 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.929893 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106255777500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14426.759191 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 30.810977 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16428.074381 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000940 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.501345 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942555 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5920172 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5920172 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3416489 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3416489 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1101250 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1101250 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7021422 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7021422 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7021422 # number of overall hits +system.cpu.l2cache.overall_hits::total 7021422 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1376432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1377397 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 782511 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 782511 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2158943 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2159908 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2158943 # number of overall misses +system.cpu.l2cache.overall_misses::total 2159908 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35260500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49459767000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 49495027500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 28979186500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 28979186500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35260500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 78438953500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 78474214000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35260500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 78438953500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 78474214000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 965 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7296604 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7297569 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3416489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3416489 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1883761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1883761 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9180365 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9181330 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9180365 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9181330 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.188731 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415447 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.415447 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188640 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.188747 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.415398 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.415398 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235167 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.235247 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235170 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.235250 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235167 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.235247 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36575.569358 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.943887 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35934.393919 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37037.053564 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37037.053564 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36333.930435 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36575.569358 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36333.822314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36333.930435 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 23861689 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235170 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.235250 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36539.378238 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35933.316720 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35933.741325 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37033.583553 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37033.583553 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36539.378238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36332.109509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 36332.202112 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36539.378238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36332.109509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 36332.202112 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 47300 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3922 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3906 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6084.061448 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12.109575 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1050125 # number of writebacks -system.cpu.l2cache.writebacks::total 1050125 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376292 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1377258 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782601 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 782601 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2158893 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2159859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2158893 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2159859 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32266500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45051953000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45084219500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26472928656 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26472928656 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32266500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71524881656 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 71557148156 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32266500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71524881656 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 71557148156 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1050116 # number of writebacks +system.cpu.l2cache.writebacks::total 1050116 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1376432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1377397 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 782511 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 782511 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2158943 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2159908 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2158943 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2159908 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32204000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 45055642500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 45087846500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 26467073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 26467073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 71522715500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71554919500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32204000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 71522715500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71554919500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188731 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415447 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415447 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188640 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188747 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.415398 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.415398 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.235247 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.235250 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235167 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.235247 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33402.173913 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32734.298390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.766834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33826.852580 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33826.852580 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.235250 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33372.020725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32733.649392 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.096633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33823.259993 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33823.259993 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 620901a70..2519af40e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.454220 # Number of seconds simulated -sim_ticks 454219906500 # Number of ticks simulated -final_tick 454219906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.454149 # Number of seconds simulated +sim_ticks 454149445000 # Number of ticks simulated +final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138720 # Simulator instruction rate (inst/s) -host_op_rate 154753 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40794382 # Simulator tick rate (ticks/s) -host_mem_usage 234840 # Number of bytes of host memory used -host_seconds 11134.37 # Real time elapsed on the host +host_inst_rate 251011 # Simulator instruction rate (inst/s) +host_op_rate 280022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73805166 # Simulator tick rate (ticks/s) +host_mem_usage 228580 # Number of bytes of host memory used +host_seconds 6153.36 # Real time elapsed on the host sim_insts 1544563043 # Number of instructions simulated sim_ops 1723073855 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156313408 # Number of bytes read from this memory -system.physmem.bytes_read::total 156361216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71943232 # Number of bytes written to this memory -system.physmem.bytes_written::total 71943232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 747 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443144 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124113 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124113 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 105253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 344135970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 344241223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 105253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105253 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158388549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158388549 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158388549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 105253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 344135970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 502629772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory +system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory +system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,140 +77,140 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 908439814 # number of cpu cycles simulated +system.cpu.numCycles 908298891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 299293350 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 245165786 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16042294 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 167415927 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 155291115 # Number of BTB hits +system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18349808 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 291155231 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2147464853 # Number of instructions fetch has processed -system.cpu.fetch.Branches 299293350 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 173640923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 427083963 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 82022952 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 117971766 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 282205512 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5329978 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 901954385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.649183 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.246512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 474870538 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 22740626 2.52% 55.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38702218 4.29% 59.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47644255 5.28% 64.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 40322718 4.47% 69.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46782649 5.19% 74.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38980366 4.32% 78.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18009770 2.00% 80.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 173901245 19.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 901954385 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.329459 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.363904 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 319244517 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 99044104 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402843645 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15079439 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 65742680 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46017167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 685 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2336575701 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2448 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 65742680 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 340277658 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 45082178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13877 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 395714637 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55123355 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2280505483 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18602 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4635517 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42073464 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2255238182 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10526656383 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10526652098 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4285 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 548918220 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1694 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1690 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 127506095 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 622196847 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 217942695 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 85227601 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 65382931 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2181344295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1719 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2010119502 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4796816 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454085036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1056260113 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1545 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 901954385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.228627 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.927984 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 241738453 26.80% 26.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 133353594 14.78% 41.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 156367006 17.34% 58.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 115954647 12.86% 71.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 125581942 13.92% 85.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 75899476 8.42% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39722592 4.40% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10686145 1.18% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2650530 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 901954385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 695241 2.77% 2.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4797 0.02% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19085015 76.16% 78.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5273410 21.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1230459115 61.21% 61.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 930103 0.05% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued @@ -234,88 +234,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 33 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 585119298 29.11% 90.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193610861 9.63% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2010119502 # Type of FU issued -system.cpu.iq.rate 2.212716 # Inst issue rate -system.cpu.iq.fu_busy_cnt 25058463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012466 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4952048213 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2635615257 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1952750313 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 782 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2035177734 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63595770 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued +system.cpu.iq.rate 2.213059 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 136270074 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 285522 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187812 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 43095646 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 118212 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 65742680 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 20161039 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1080033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2181346094 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5536242 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 622196847 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 217942695 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1653 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 42353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187812 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8595145 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10187661 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18782806 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1980860321 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 570725685 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29259181 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 761335906 # number of memory reference insts executed -system.cpu.iew.exec_branches 237528825 # Number of branches executed -system.cpu.iew.exec_stores 190610221 # Number of stores executed -system.cpu.iew.exec_rate 2.180508 # Inst execution rate -system.cpu.iew.wb_sent 1961779173 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1952750482 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1293463699 # num instructions producing a value -system.cpu.iew.wb_consumers 2065510739 # num instructions consuming a value +system.cpu.iew.exec_nop 81 # number of nop insts executed +system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed +system.cpu.iew.exec_branches 237537296 # Number of branches executed +system.cpu.iew.exec_stores 190660380 # Number of stores executed +system.cpu.iew.exec_rate 2.180837 # Inst execution rate +system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1293399468 # num instructions producing a value +system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.149565 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626220 # average fanout of values written-back +system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 458335863 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16041632 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 836211706 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.060571 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763665 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 346444317 41.43% 41.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193987468 23.20% 64.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73877669 8.83% 73.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35342489 4.23% 77.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18524109 2.22% 79.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30984795 3.71% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19692342 2.35% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10738999 1.28% 87.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106619518 12.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 836211706 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563061 # Number of instructions committed system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -326,70 +326,70 @@ system.cpu.commit.branches 213462430 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106619518 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2911001325 # The number of ROB reads -system.cpu.rob.rob_writes 4428720797 # The number of ROB writes -system.cpu.timesIdled 678798 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6485429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2910643265 # The number of ROB reads +system.cpu.rob.rob_writes 4428322151 # The number of ROB writes +system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563043 # Number of Instructions Simulated system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated -system.cpu.cpi 0.588153 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.588153 # CPI: Total CPI of All Threads -system.cpu.ipc 1.700237 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.700237 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9924440864 # number of integer regfile reads -system.cpu.int_regfile_writes 1932829114 # number of integer regfile writes -system.cpu.fp_regfile_reads 176 # number of floating regfile reads -system.cpu.fp_regfile_writes 197 # number of floating regfile writes -system.cpu.misc_regfile_reads 2885564305 # number of misc regfile reads +system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads +system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads +system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes +system.cpu.fp_regfile_reads 180 # number of floating regfile reads +system.cpu.fp_regfile_writes 196 # number of floating regfile writes +system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads system.cpu.misc_regfile_writes 132 # number of misc regfile writes -system.cpu.icache.replacements 18 # number of replacements -system.cpu.icache.tagsinuse 627.769502 # Cycle average of tags in use -system.cpu.icache.total_refs 282204371 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 363197.388674 # Average number of references to valid blocks. +system.cpu.icache.replacements 25 # number of replacements +system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use +system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 627.769502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.306528 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.306528 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 282204371 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 282204371 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 282204371 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 282204371 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 282204371 # number of overall hits -system.cpu.icache.overall_hits::total 282204371 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses -system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38891500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38891500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38891500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38891500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38891500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38891500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 282205512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 282205512 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 282205512 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 282205512 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 282205512 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 282205512 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits +system.cpu.icache.overall_hits::total 282187157 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34085.451358 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34085.451358 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34085.451358 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34085.451358 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34085.451358 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,313 +398,309 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 363 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 363 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 363 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 363 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 363 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 778 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 778 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 778 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 778 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 778 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 778 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36341.902314 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36341.902314 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36341.902314 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36341.902314 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9617276 # number of replacements -system.cpu.dcache.tagsinuse 4087.426616 # Cycle average of tags in use -system.cpu.dcache.total_refs 660019994 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9621372 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 68.599363 # Average number of references to valid blocks. +system.cpu.dcache.replacements 9616145 # number of replacements +system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use +system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.426616 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 492609527 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 492609527 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 167410308 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 167410308 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 660019835 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 660019835 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 660019835 # number of overall hits -system.cpu.dcache.overall_hits::total 660019835 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 10110221 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 10110221 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5175739 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5175739 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 659915355 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 659915355 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 659915355 # number of overall hits +system.cpu.dcache.overall_hits::total 659915355 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 10104493 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 10104493 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5175397 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5175397 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 15285960 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 15285960 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 15285960 # number of overall misses -system.cpu.dcache.overall_misses::total 15285960 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152096766000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152096766000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119863517075 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119863517075 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 78000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 271960283075 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 271960283075 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 271960283075 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 271960283075 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 502719748 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 502719748 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses +system.cpu.dcache.overall_misses::total 15279890 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 96 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 675305795 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 675305795 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 675305795 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 675305795 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020111 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020111 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029989 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.029989 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031250 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022636 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022636 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022636 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022636 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15043.861652 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15043.861652 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23158.725174 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23158.725174 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17791.508226 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17791.508226 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17791.508226 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 277962262 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 153500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 60300 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4609.656086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 17055.555556 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3473158 # number of writebacks -system.cpu.dcache.writebacks::total 3473158 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2383078 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2383078 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3281509 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks +system.cpu.dcache.writebacks::total 3473179 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5664587 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5664587 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5664587 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5664587 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727143 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7727143 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894230 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1894230 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9621373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9621373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9621373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9621373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75156431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75156431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39462683260 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 39462683260 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114619114760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114619114760 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114619114760 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114619114760 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015371 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015371 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010976 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010976 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014247 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014247 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014247 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9726.289717 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9726.289717 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20833.100130 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20833.100130 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11912.968633 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11912.968633 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2427555 # number of replacements -system.cpu.l2cache.tagsinuse 31133.152617 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8743299 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2457267 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.558140 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 77440728000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14066.626463 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 15.622946 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17050.903208 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.429279 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000477 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.520352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.950108 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6115762 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6115791 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3473158 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3473158 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1063205 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1063205 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7178967 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7178996 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7178967 # number of overall hits -system.cpu.l2cache.overall_hits::total 7178996 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 749 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1611381 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1612130 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 831024 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 831024 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 749 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2442405 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2443154 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 749 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2442405 # number of overall misses -system.cpu.l2cache.overall_misses::total 2443154 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27440500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59348934500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 59376375000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35714709005 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 35714709005 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27440500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 95063643505 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 95091084005 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27440500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 95063643505 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 95091084005 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7727143 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7727921 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3473158 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3473158 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894229 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1894229 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9621372 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9622150 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9621372 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9622150 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208535 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.208611 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438714 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.438714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962725 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.253852 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.253909 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962725 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.253852 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.253909 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36636.181575 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36831.099845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36831.009286 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42976.747970 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42976.747970 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 38921.444987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36636.181575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38922.145797 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 38921.444987 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 115700122 # number of cycles access was blocked +system.cpu.l2cache.replacements 2426778 # number of replacements +system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use +system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits +system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 830807 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2441663 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2442420 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2441663 # number of overall misses +system.cpu.l2cache.overall_misses::total 2442420 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27670500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59328864000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 59356534500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35694611500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 35694611500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27670500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 95023475500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 95051146000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27670500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 95023475500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 95051146000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7726108 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7726893 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3473179 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3473179 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894133 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1894133 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9620241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9621026 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9620241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9621026 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964331 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208495 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.208572 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438621 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964331 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.253805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.253863 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964331 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.253805 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.253863 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36552.840159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42963.782804 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 38916.789905 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 21086 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5487.058807 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1124113 # number of writebacks -system.cpu.l2cache.writebacks::total 1124113 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks +system.cpu.l2cache.writebacks::total 1123907 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 747 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612120 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831024 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 831024 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 747 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2443144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 747 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442397 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2443144 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25029000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54213758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54238787000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33085952005 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33085952005 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25029000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87299710005 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 87324739005 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25029000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87299710005 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 87324739005 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208534 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208610 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33506.024096 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33644.449795 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33644.385654 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39813.473504 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39813.473504 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1610849 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1611603 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830807 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830807 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2441656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2442410 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2441656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2442410 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54220265500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33065264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25220000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438621 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438621 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253862 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253862 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index aad21c6d0..feb13ce30 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.042001 # Nu sim_ticks 42001440000 # Number of ticks simulated final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75192 # Simulator instruction rate (inst/s) -host_op_rate 75192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34364250 # Simulator tick rate (ticks/s) -host_mem_usage 223172 # Number of bytes of host memory used -host_seconds 1222.24 # Real time elapsed on the host +host_inst_rate 134131 # Simulator instruction rate (inst/s) +host_op_rate 134131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61300636 # Simulator tick rate (ticks/s) +host_mem_usage 216520 # Number of bytes of host memory used +host_seconds 685.17 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -174,11 +174,11 @@ system.cpu.icache.demand_avg_miss_latency::total 24215.288412 system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits @@ -270,11 +270,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 54653.714005 system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 4339a22dc..c18f0c43e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023660 # Nu sim_ticks 23659827000 # Number of ticks simulated final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114539 # Simulator instruction rate (inst/s) -host_op_rate 114539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32192844 # Simulator tick rate (ticks/s) -host_mem_usage 224192 # Number of bytes of host memory used -host_seconds 734.94 # Real time elapsed on the host +host_inst_rate 188397 # Simulator instruction rate (inst/s) +host_op_rate 188397 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52951506 # Simulator tick rate (ticks/s) +host_mem_usage 217548 # Number of bytes of host memory used +host_seconds 446.82 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory @@ -481,11 +481,11 @@ system.cpu.dcache.demand_avg_miss_latency::cpu.data 35694.911504 system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -623,11 +623,11 @@ system.cpu.l2cache.demand_avg_miss_latency::total 36749.952390 system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index e11bd02ec..a5a9d98b7 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.075929 # Nu sim_ticks 75929256000 # Number of ticks simulated final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99785 # Simulator instruction rate (inst/s) -host_op_rate 109254 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43964821 # Simulator tick rate (ticks/s) -host_mem_usage 238132 # Number of bytes of host memory used -host_seconds 1727.05 # Real time elapsed on the host +host_inst_rate 126863 # Simulator instruction rate (inst/s) +host_op_rate 138901 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55895176 # Simulator tick rate (ticks/s) +host_mem_usage 231880 # Number of bytes of host memory used +host_seconds 1358.42 # Real time elapsed on the host sim_insts 172333091 # Number of instructions simulated sim_ops 188686573 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory @@ -497,11 +497,11 @@ system.cpu.dcache.demand_avg_miss_latency::total 31016.696141 system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 18 # number of writebacks |