diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-07-28 01:48:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-07-28 01:48:21 -0400 |
| commit | cbf417c71322de6aee0afd9ca11444f935c1cd80 (patch) | |
| tree | d33ad25edec0508ddaeb81a553064adfe0ebbdd0 /tests/long/se | |
| parent | 5d0b25ba3f82b6d563b3fabd3de71f3ceabb140d (diff) | |
| download | gem5-cbf417c71322de6aee0afd9ca11444f935c1cd80.tar.xz | |
stats: Bump stats for the regressions using the minor CPU
Updating the stats to match the current behaviour.
Diffstat (limited to 'tests/long/se')
7 files changed, 3864 insertions, 3863 deletions
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 3677da8b6..d97d6a9aa 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,529 +1,100 @@ ---------- Begin Simulation Statistics ---------- -final_tick 409828126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 259766 # Simulator instruction rate (inst/s) -host_mem_usage 250424 # Number of bytes of host memory used -host_op_rate 259766 # Simulator op (including micro ops) rate (op/s) -host_seconds 2355.59 # Real time elapsed on the host -host_tick_rate 173981398 # Simulator tick rate (ticks/s) +sim_seconds 0.409306 # Number of seconds simulated +sim_ticks 409306011500 # Number of ticks simulated +final_tick 409306011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 215743 # Simulator instruction rate (inst/s) +host_op_rate 215743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 144312578 # Simulator tick rate (ticks/s) +host_mem_usage 243356 # Number of bytes of host memory used +host_seconds 2836.25 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated -sim_seconds 0.409828 # Number of seconds simulated -sim_ticks 409828126500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.066276 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 67266528 # Number of BTB hits -system.cpu.branchPred.BTBLookups 71509717 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 1120898 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 6389580 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 87724444 # Number of conditional branches predicted -system.cpu.branchPred.lookups 123843348 # Number of BP lookups -system.cpu.branchPred.usedRAS 14941692 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 611901617 # Number of instructions committed -system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.cpi 1.339523 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 148791104 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148791104 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19067.269367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19067.269367 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17118.543589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17118.543589 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 146883081 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146883081 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36380788500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36380788500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012824 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012824 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1908023 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908023 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143343 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143343 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30208751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30208751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011860 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011860 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29178.748051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29178.748051 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27324.419197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27324.419197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 55666185 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666185 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45047581000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 45047581000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 1543849 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543849 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769059 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769059 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21170686750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21170686750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774790 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774790 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 206001138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206001138 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23589.626006 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23589.626006 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20232.347005 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20232.347005 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 202549266 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202549266 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 81428369500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81428369500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.016757 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 3451872 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3451872 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 912402 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912402 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51379438250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51379438250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012327 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012327 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2539470 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539470 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 206001138 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206001138 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23589.626006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23589.626006 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20232.347005 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20232.347005 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 202549266 # number of overall hits -system.cpu.dcache.overall_hits::total 202549266 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 81428369500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81428369500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.016757 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 3451872 # number of overall misses -system.cpu.dcache.overall_misses::total 3451872 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 912402 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912402 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51379438250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51379438250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012327 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012327 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2539470 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539470 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 79.760448 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 414541746 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.758169 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 2535374 # number of replacements -system.cpu.dcache.tags.sampled_refs 2539470 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 414541746 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4087.758169 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202549266 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608263250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 2340003 # number of writebacks -system.cpu.dcache.writebacks::total 2340003 # number of writebacks -system.cpu.discardedOps 13239611 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 207242011 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 206630168 # DTB hits -system.cpu.dtb.data_misses 611843 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 149856039 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 149313819 # DTB read hits -system.cpu.dtb.read_misses 542220 # DTB read misses -system.cpu.dtb.write_accesses 57385972 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 57316349 # DTB write hits -system.cpu.dtb.write_misses 69623 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 226025524 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226025524 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45550.859313 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45550.859313 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43330.035971 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43330.035971 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 226020520 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226020520 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 227936500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 227936500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 5004 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5004 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216823500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 216823500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5004 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 226025524 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226025524 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45550.859313 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45550.859313 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43330.035971 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43330.035971 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 226020520 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226020520 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 227936500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 227936500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 5004 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5004 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216823500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 216823500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 5004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5004 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 226025524 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226025524 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45550.859313 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45550.859313 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43330.035971 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43330.035971 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 226020520 # number of overall hits -system.cpu.icache.overall_hits::total 226020520 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 227936500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 227936500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 5004 # number of overall misses -system.cpu.icache.overall_misses::total 5004 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216823500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 216823500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 5004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5004 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 45167.969624 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 452056052 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.136811 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545477 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 3175 # number of replacements -system.cpu.icache.tags.sampled_refs 5004 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 452056052 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1117.136811 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226020520 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 81747250 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.746534 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 226025572 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 226025524 # ITB hits -system.cpu.itb.fetch_misses 48 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778160 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778160 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71244.326459 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71244.326459 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58557.851000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58557.851000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 571543 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571543 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14720289000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14720289000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265520 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265520 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 206617 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206617 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12099047500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12099047500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265520 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265520 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206617 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206617 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73023.954626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73023.954626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60269.606712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60269.606712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1592955 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1592955 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12659359750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12659359750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 173359 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 173359 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10448278750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10448278750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173359 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173359 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 2340003 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340003 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 2340003 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340003 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 2544474 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544474 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72056.258158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72056.258158 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59338.816794 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59338.816794 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 2164498 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164498 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 27379648750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27379648750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149334 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149334 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 379976 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 379976 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22547326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22547326250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149334 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149334 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 379976 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 379976 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 2544474 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544474 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72056.258158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72056.258158 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59338.816794 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59338.816794 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 2164498 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164498 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 27379648750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27379648750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149334 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149334 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 379976 # number of overall misses -system.cpu.l2cache.overall_misses::total 379976 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22547326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22547326250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149334 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149334 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 379976 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 379976 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18830 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 9.773812 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 40233665 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 21416.051201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8077.270621 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246499 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900065 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 347265 # number of replacements -system.cpu.l2cache.tags.sampled_refs 379689 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 40233665 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 29493.321822 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711009 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 188556996000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 292560 # number of writebacks -system.cpu.l2cache.writebacks::total 292560 # number of writebacks -system.cpu.numCycles 819656253 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 737909003 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 312606528 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10008 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7418943 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7428951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4782241500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8058500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891611750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 762774704 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 320256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312286272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 312606528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 1766314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340003 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution -system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 43042304 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052512 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052512 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 3207663500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3609435250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 105025256 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43042304 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43042304 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 173359 # Transaction distribution -system.membus.trans_dist::ReadResp 173359 # Transaction distribution -system.membus.trans_dist::Writeback 292560 # Transaction distribution -system.membus.trans_dist::ReadExReq 206617 # Transaction distribution -system.membus.trans_dist::ReadExResp 206617 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 609377.11 # Average gap between requests -system.physmem.avgMemAccLat 29335.98 # Average memory access latency per DRAM burst -system.physmem.avgQLat 10585.98 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 59.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.34 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 45.68 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.69 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 21.08 # Average write queue length when enqueuing -system.physmem.busUtil 0.82 # Data bus utilization in percentage -system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 416487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 416487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 59338202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59338202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45687055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 59338202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 105025256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 45687055 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45687055 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 141722 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.513414 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.917362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.228374 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50747 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38472 27.15% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12956 9.14% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8075 5.70% 77.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5903 4.17% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3858 2.72% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2996 2.11% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2531 1.79% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16184 11.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 141722 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 24294464 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 24318464 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue -system.physmem.bytesWritten 18722176 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 18723840 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 170688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 170688 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 24318464 # Number of bytes read from this memory -system.physmem.bytes_read::total 24318464 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 18723840 # Number of bytes written to this memory -system.physmem.bytes_written::total 18723840 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 275306446750 # Time in different power states -system.physmem.memoryStateTime::REF 13684840000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 120830469500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 24320640 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320640 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724096 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 380010 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380010 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292564 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 59419210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 59419210 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 417174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 417174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45745959 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45745959 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45745959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 59419210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 105165169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380010 # Number of read requests accepted +system.physmem.writeReqs 292564 # Number of write requests accepted +system.physmem.readBursts 380010 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292564 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24298688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21952 # Total number of bytes read from write queue +system.physmem.bytesWritten 18722368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24320640 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724096 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 343 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 379976 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379976 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292560 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292560 # Number of write requests responded to by this memory -system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 23726 # Per bank write bursts -system.physmem.perBankRdBursts::1 23205 # Per bank write bursts -system.physmem.perBankRdBursts::2 23510 # Per bank write bursts -system.physmem.perBankRdBursts::3 24533 # Per bank write bursts -system.physmem.perBankRdBursts::4 25455 # Per bank write bursts -system.physmem.perBankRdBursts::5 23583 # Per bank write bursts -system.physmem.perBankRdBursts::6 23677 # Per bank write bursts -system.physmem.perBankRdBursts::7 23976 # Per bank write bursts -system.physmem.perBankRdBursts::8 23173 # Per bank write bursts -system.physmem.perBankRdBursts::9 23944 # Per bank write bursts -system.physmem.perBankRdBursts::10 24673 # Per bank write bursts -system.physmem.perBankRdBursts::11 22745 # Per bank write bursts -system.physmem.perBankRdBursts::12 23724 # Per bank write bursts -system.physmem.perBankRdBursts::13 24416 # Per bank write bursts -system.physmem.perBankRdBursts::14 22797 # Per bank write bursts -system.physmem.perBankRdBursts::15 22464 # Per bank write bursts -system.physmem.perBankWrBursts::0 17752 # Per bank write bursts -system.physmem.perBankWrBursts::1 17432 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18769 # Per bank write bursts -system.physmem.perBankWrBursts::4 19443 # Per bank write bursts -system.physmem.perBankWrBursts::5 18535 # Per bank write bursts -system.physmem.perBankWrBursts::6 18682 # Per bank write bursts +system.physmem.perBankRdBursts::0 23736 # Per bank write bursts +system.physmem.perBankRdBursts::1 23211 # Per bank write bursts +system.physmem.perBankRdBursts::2 23514 # Per bank write bursts +system.physmem.perBankRdBursts::3 24536 # Per bank write bursts +system.physmem.perBankRdBursts::4 25475 # Per bank write bursts +system.physmem.perBankRdBursts::5 23585 # Per bank write bursts +system.physmem.perBankRdBursts::6 23685 # Per bank write bursts +system.physmem.perBankRdBursts::7 23974 # Per bank write bursts +system.physmem.perBankRdBursts::8 23182 # Per bank write bursts +system.physmem.perBankRdBursts::9 23951 # Per bank write bursts +system.physmem.perBankRdBursts::10 24679 # Per bank write bursts +system.physmem.perBankRdBursts::11 22748 # Per bank write bursts +system.physmem.perBankRdBursts::12 23716 # Per bank write bursts +system.physmem.perBankRdBursts::13 24414 # Per bank write bursts +system.physmem.perBankRdBursts::14 22802 # Per bank write bursts +system.physmem.perBankRdBursts::15 22459 # Per bank write bursts +system.physmem.perBankWrBursts::0 17754 # Per bank write bursts +system.physmem.perBankWrBursts::1 17435 # Per bank write bursts +system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::3 18771 # Per bank write bursts +system.physmem.perBankWrBursts::4 19442 # Per bank write bursts +system.physmem.perBankWrBursts::5 18539 # Per bank write bursts +system.physmem.perBankWrBursts::6 18677 # Per bank write bursts system.physmem.perBankWrBursts::7 18571 # Per bank write bursts -system.physmem.perBankWrBursts::8 18355 # Per bank write bursts +system.physmem.perBankWrBursts::8 18354 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19130 # Per bank write bursts +system.physmem.perBankWrBursts::10 19131 # Per bank write bursts system.physmem.perBankWrBursts::11 17964 # Per bank write bursts -system.physmem.perBankWrBursts::12 18225 # Per bank write bursts -system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::12 18221 # Per bank write bursts +system.physmem.perBankWrBursts::13 18695 # Per bank write bursts system.physmem.perBankWrBursts::14 17147 # Per bank write bursts system.physmem.perBankWrBursts::15 17101 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 17247 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.008465 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.376560 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17237 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17247 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 378215 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1371 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 409305930000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 380010 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 292564 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -554,42 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 379976 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379976 # Read request sizes (log2) -system.physmem.readReqs 379976 # Number of read requests accepted -system.physmem.readRowHitRate 82.98 # Row buffer hit rate for reads -system.physmem.readRowHits 314993 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 1898005000 # Total ticks spent in databus transfers -system.physmem.totGap 409828045500 # Total gap between requests -system.physmem.totMemAccLat 11135967500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 4018448750 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 17247 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.961443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.889231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.813189 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17030 98.74% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 169 0.98% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 4 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17247 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -605,42 +140,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17305 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -654,17 +189,482 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 292560 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292560 # Write request sizes (log2) -system.physmem.writeReqs 292560 # Number of write requests accepted -system.physmem.writeRowHitRate 73.63 # Row buffer hit rate for writes -system.physmem.writeRowHits 215411 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 141944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.070281 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.645979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.191162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50836 35.81% 35.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38595 27.19% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13069 9.21% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8075 5.69% 77.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5863 4.13% 82.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3755 2.65% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3005 2.12% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2490 1.75% 88.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16256 11.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 141944 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.005912 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.974837 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17241 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 7 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 17252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.956701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.885973 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.749936 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17057 98.87% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 150 0.87% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.14% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 7 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17252 # Writes before turning the bus around for reads +system.physmem.totQLat 4021715750 # Total ticks spent queuing +system.physmem.totMemAccLat 11140472000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10592.75 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29342.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 59.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.74 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 59.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.75 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.32 # Average write queue length when enqueuing +system.physmem.readRowHits 314877 # Number of row buffer hits during reads +system.physmem.writeRowHits 215374 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.94 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes +system.physmem.avgGap 608566.39 # Average gap between requests +system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 274823723500 # Time in different power states +system.physmem.memoryStateTime::REF 13667420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 120808954500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 105165169 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 173388 # Transaction distribution +system.membus.trans_dist::ReadResp 173388 # Transaction distribution +system.membus.trans_dist::Writeback 292564 # Transaction distribution +system.membus.trans_dist::ReadExReq 206622 # Transaction distribution +system.membus.trans_dist::ReadExResp 206622 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052584 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044736 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43044736 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43044736 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3204326000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3607344750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 123709142 # Number of BP lookups +system.cpu.branchPred.condPredicted 87625206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6390886 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71443290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67227338 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 94.098883 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 14930671 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1120494 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 149298589 # DTB read hits +system.cpu.dtb.read_misses 537604 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 149836193 # DTB read accesses +system.cpu.dtb.write_hits 57313863 # DTB write hits +system.cpu.dtb.write_misses 67044 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 57380907 # DTB write accesses +system.cpu.dtb.data_hits 206612452 # DTB hits +system.cpu.dtb.data_misses 604648 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 207217100 # DTB accesses +system.cpu.itb.fetch_hits 225745608 # ITB hits +system.cpu.itb.fetch_misses 48 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 225745656 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 485 # Number of system calls +system.cpu.numCycles 818612023 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 611901617 # Number of instructions committed +system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed +system.cpu.discardedOps 13147093 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.337816 # CPI: cycles per instruction +system.cpu.ipc 0.747487 # IPC: instructions per cycle +system.cpu.tickCycles 736852058 # Number of cycles that the object actually ticked +system.cpu.idleCycles 81759965 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3162 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.165991 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 225740617 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4991 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45229.536566 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1116.165991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545003 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 451496207 # Number of tag accesses +system.cpu.icache.tags.data_accesses 451496207 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 225740617 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 225740617 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 225740617 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 225740617 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 225740617 # number of overall hits +system.cpu.icache.overall_hits::total 225740617 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4991 # number of overall misses +system.cpu.icache.overall_misses::total 4991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 227498000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 227498000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 227498000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 227498000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 227498000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 227498000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 225745608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 225745608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 225745608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 225745608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 225745608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 225745608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45581.646965 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45581.646965 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45581.646965 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45581.646965 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45581.646965 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4991 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4991 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4991 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4991 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4991 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4991 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 216413000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 216413000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 216413000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 216413000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 216413000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 216413000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43360.649169 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43360.649169 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43360.649169 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43360.649169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43360.649169 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43360.649169 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 763750366 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1766329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778155 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7418996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7428978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312288192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 312607616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 312607616 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4782257000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8038000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3891565250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 347300 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29490.485605 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3710989 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379724 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.772859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 188606170000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21413.748537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8076.737069 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653496 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.246482 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.899978 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18828 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 40233831 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40233831 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1592941 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1592941 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2340010 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2340010 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 571533 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571533 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2164474 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164474 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2164474 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164474 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 173388 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 173388 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 206622 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206622 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 380010 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380010 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 380010 # number of overall misses +system.cpu.l2cache.overall_misses::total 380010 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12655083750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12655083750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 14728692500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14728692500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27383776250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27383776250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27383776250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27383776250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1766329 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1766329 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2340010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2340010 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 778155 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778155 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 2544484 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2544484 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.098163 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098163 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.265528 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265528 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149347 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149347 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149347 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149347 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72987.079556 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72987.079556 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 71283.273320 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71283.273320 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72060.672745 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72060.672745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72060.672745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72060.672745 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 292564 # number of writebacks +system.cpu.l2cache.writebacks::total 292564 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 173388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 206622 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206622 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 380010 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380010 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 380010 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380010 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10443247750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10443247750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 12110276500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12110276500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22553524250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22553524250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22553524250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22553524250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.098163 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098163 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.265528 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265528 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149347 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149347 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60230.510474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60230.510474 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 58610.779588 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58610.779588 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59349.817768 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 2535397 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.756934 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202541489 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539493 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.756664 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1608245250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4087.756934 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.997988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997988 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 414526387 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414526387 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 146875295 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146875295 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 55666194 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666194 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 202541489 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202541489 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 202541489 # number of overall hits +system.cpu.dcache.overall_hits::total 202541489 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1908118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 1543840 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543840 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3451958 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3451958 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3451958 # number of overall misses +system.cpu.dcache.overall_misses::total 3451958 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36372214750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36372214750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 45066771500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45066771500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 81438986250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 81438986250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 81438986250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 81438986250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 148783413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148783413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 205993447 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 205993447 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 205993447 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 205993447 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.016758 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016758 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.016758 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016758 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 19061.826758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19061.826758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 29191.348521 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29191.348521 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23592.113881 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 23592.113881 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23592.113881 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2340010 # number of writebacks +system.cpu.dcache.writebacks::total 2340010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 143436 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143436 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 769029 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769029 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 912465 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912465 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 912465 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912465 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1764682 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764682 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 774811 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774811 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2539493 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539493 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2539493 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539493 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 30204720750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30204720750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 21179013000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 21179013000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 51383733750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 51383733750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 51383733750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 51383733750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.011861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012328 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.012328 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012328 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 17116.240065 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17116.240065 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 27334.424782 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27334.424782 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 20233.855242 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20233.855242 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 12f448f86..0b41505d8 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,476 +1,42 @@ ---------- Begin Simulation Statistics ---------- -final_tick 220685053500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 266134 # Simulator instruction rate (inst/s) -host_mem_usage 254064 # Number of bytes of host memory used -host_op_rate 266134 # Simulator op (including micro ops) rate (op/s) -host_seconds 1497.99 # Real time elapsed on the host -host_tick_rate 147321061 # Simulator tick rate (ticks/s) +sim_seconds 0.219644 # Number of seconds simulated +sim_ticks 219644167500 # Number of ticks simulated +final_tick 219644167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 184210 # Simulator instruction rate (inst/s) +host_op_rate 184210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 101490439 # Simulator tick rate (ticks/s) +host_mem_usage 247040 # Number of bytes of host memory used +host_seconds 2164.19 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated -sim_seconds 0.220685 # Number of seconds simulated -sim_ticks 220685053500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.751650 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 21330181 # Number of BTB hits -system.cpu.branchPred.BTBLookups 25468371 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 1012944 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 26708480 # Number of conditional branches predicted -system.cpu.branchPred.lookups 46221019 # Number of BP lookups -system.cpu.branchPred.usedRAS 8327448 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 398664665 # Number of instructions committed -system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.cpi 1.107121 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 94494338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94494338 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68449.404762 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68449.404762 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66089.617769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66089.617769 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 94493162 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94493162 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80496500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80496500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 63974750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63974750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66549.865343 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66549.865343 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67934.000626 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67934.000626 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 73514789 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514789 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 395372750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 395372750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 5941 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5941 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 217185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 217185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 168015068 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168015068 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66863.741745 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 168007951 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168007951 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 475869250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 475869250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281159750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 281159750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 168015068 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168015068 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66863.741745 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66863.741745 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67505.342137 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67505.342137 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 168007951 # number of overall hits -system.cpu.dcache.overall_hits::total 168007951 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 475869250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 475869250 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses -system.cpu.dcache.overall_misses::total 7117 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281159750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 281159750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 40338.043457 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 336034301 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.724304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.803644 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803644 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 336034301 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 3291.724304 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168007951 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 654 # number of writebacks -system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.discardedOps 4407642 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 169201829 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 169200862 # DTB hits -system.cpu.dtb.data_misses 967 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 95596602 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 95596493 # DTB read hits -system.cpu.dtb.read_misses 109 # DTB read misses -system.cpu.dtb.write_accesses 73605227 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 73604369 # DTB write hits -system.cpu.dtb.write_misses 858 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 98039875 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98039875 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56706.988208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56706.988208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54392.373864 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54392.373864 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 98034702 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98034702 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293345250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293345250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281371750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281371750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5173 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5173 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 98039875 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98039875 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56706.988208 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56706.988208 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54392.373864 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54392.373864 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 98034702 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98034702 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 293345250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293345250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281371750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281371750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 5173 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 98039875 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98039875 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56706.988208 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56706.988208 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54392.373864 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54392.373864 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 98034702 # number of overall hits -system.cpu.icache.overall_hits::total 98034702 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 293345250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293345250 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses -system.cpu.icache.overall_misses::total 5173 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281371750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281371750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 18951.227914 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 196084923 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.700868 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937354 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937354 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 3195 # number of replacements -system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 196084923 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1919.700868 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98034702 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 3993538 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.903243 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 98041099 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 98039875 # ITB hits -system.cpu.itb.fetch_misses 1224 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68031.548757 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68031.548757 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55379.700446 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55379.700446 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 213483000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 213483000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980932 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.980932 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 3138 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3138 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173781500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173781500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68618.957146 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68618.957146 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56083.175005 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56083.175005 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1402 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325048000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 325048000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.771624 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 4737 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 265666000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265666000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 9338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9338 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68384.888889 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68384.888889 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55802.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55802.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1463 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 538531000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 538531000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439447500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 439447500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68384.888889 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68384.888889 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55802.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55802.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits -system.cpu.l2cache.overall_hits::total 1463 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 538531000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 538531000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses -system.cpu.l2cache.overall_misses::total 7875 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439447500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 439447500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 373.078063 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.561025 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135121 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 4427.639089 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 441370107 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 437376569 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8573250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6973250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 2897740 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 504000 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 9402000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73919000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 2283798 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 4737 # Transaction distribution -system.membus.trans_dist::ReadResp 4737 # Transaction distribution -system.membus.trans_dist::ReadExReq 3138 # Transaction distribution -system.membus.trans_dist::ReadExResp 3138 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 28023488.51 # Average gap between requests -system.physmem.avgMemAccLat 25444.19 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6694.19 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 1130154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1130154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 2283798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2283798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2283798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2283798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.859118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.497740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.655221 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 518 34.10% 34.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 348 22.91% 57.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 182 11.98% 68.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 6.32% 75.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 4.15% 79.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48 3.16% 82.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 42 2.76% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 38 2.50% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 184 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory +system.physmem.bytes_read::total 504000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2294620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2294620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1135509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1135509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2294620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2294620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7875 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 504000 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 504000 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 249408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 504000 # Number of bytes read from this memory -system.physmem.bytes_read::total 504000 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 211586881750 # Time in different power states -system.physmem.memoryStateTime::REF 7368920000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1722369500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory -system.physmem.pageHitRate 80.58 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 551 # Per bank write bursts system.physmem.perBankRdBursts::1 675 # Per bank write bursts system.physmem.perBankRdBursts::2 471 # Per bank write bursts @@ -503,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 6827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 81 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 219644086000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 7875 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 6822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -535,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7875 # Read request sizes (log2) -system.physmem.readReqs 7875 # Number of read requests accepted -system.physmem.readRowHitRate 80.58 # Row buffer hit rate for reads -system.physmem.readRowHits 6346 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers -system.physmem.totGap 220684972000 # Total gap between requests -system.physmem.totMemAccLat 200373000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 52716750 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -615,17 +182,450 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 1515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 331.828383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.155331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.926802 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 511 33.73% 33.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 341 22.51% 56.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 189 12.48% 68.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 107 7.06% 75.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 50 3.30% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 60 3.96% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 2.38% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.98% 87.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 191 12.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1515 # Bytes accessed per row activation +system.physmem.totQLat 51832750 # Total ticks spent queuing +system.physmem.totMemAccLat 199489000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6581.94 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25331.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 6354 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 27891312.51 # Average gap between requests +system.physmem.pageHitRate 80.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 210595847500 # Time in different power states +system.physmem.memoryStateTime::REF 7334340000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1712418250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 2294620 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4737 # Transaction distribution +system.membus.trans_dist::ReadExReq 3138 # Transaction distribution +system.membus.trans_dist::ReadExResp 3138 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15750 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 504000 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 9401500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 73916250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 46223200 # Number of BP lookups +system.cpu.branchPred.condPredicted 26710359 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1014875 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25598344 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21333887 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 83.340887 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8326899 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 95595217 # DTB read hits +system.cpu.dtb.read_misses 114 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 95595331 # DTB read accesses +system.cpu.dtb.write_hits 73605959 # DTB write hits +system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 73606817 # DTB write accesses +system.cpu.dtb.data_hits 169201176 # DTB hits +system.cpu.dtb.data_misses 972 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 169202148 # DTB accesses +system.cpu.itb.fetch_hits 98054052 # ITB hits +system.cpu.itb.fetch_misses 1240 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 98055292 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 215 # Number of system calls +system.cpu.numCycles 439288335 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 398664665 # Number of instructions committed +system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed +system.cpu.discardedOps 4458110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.101899 # CPI: cycles per instruction +system.cpu.ipc 0.907524 # IPC: instructions per cycle +system.cpu.tickCycles 435056382 # Number of cycles that the object actually ticked +system.cpu.idleCycles 4231953 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3195 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.689869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98048879 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18953.968490 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.689869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937349 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937349 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 196113277 # Number of tag accesses +system.cpu.icache.tags.data_accesses 196113277 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98048879 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98048879 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98048879 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98048879 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98048879 # number of overall hits +system.cpu.icache.overall_hits::total 98048879 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses +system.cpu.icache.overall_misses::total 5173 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 293884750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 293884750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 293884750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 293884750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 293884750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 293884750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98054052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98054052 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98054052 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98054052 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98054052 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98054052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56811.279722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56811.279722 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281914250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281914250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 2911473 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3199 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 639488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 639488 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 8571750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 4427.544414 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 373.069820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.474595 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123733 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 88409 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 88409 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1402 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1402 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 654 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 654 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 61 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1463 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1463 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1463 # number of overall hits +system.cpu.l2cache.overall_hits::total 1463 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4737 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4737 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 3138 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 3138 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7875 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses +system.cpu.l2cache.overall_misses::total 7875 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325631750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 325631750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212036500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 212036500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 537668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 537668250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 537668250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 537668250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 654 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3199 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 9338 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9338 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 9338 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9338 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.771624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.771624 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.980932 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.980932 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4737 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3138 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266250750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266250750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 172336000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 172336000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438586750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 438586750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438586750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 438586750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980932 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # 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Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336032209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336032209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 94492115 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94492115 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 73514790 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514790 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 168006905 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168006905 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 168006905 # number of overall hits +system.cpu.dcache.overall_hits::total 168006905 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1177 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1177 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 5940 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5940 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses +system.cpu.dcache.overall_misses::total 7117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80734750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80734750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 392862000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 392862000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 473596750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 473596750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 473596750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 473596750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 94493292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94493292 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 168014022 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168014022 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 168014022 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168014022 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66544.435858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66544.435858 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 654 # number of writebacks +system.cpu.dcache.writebacks::total 654 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64078250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 64078250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 215682250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 215682250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 279760500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 279760500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 279760500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 279760500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 9659640f2..ef1860117 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,502 +1,64 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1191522940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 293885 # Simulator instruction rate (inst/s) -host_mem_usage 258084 # Number of bytes of host memory used -host_op_rate 293885 # Simulator op (including micro ops) rate (op/s) -host_seconds 6837.45 # Real time elapsed on the host -host_tick_rate 174264280 # Simulator tick rate (ticks/s) +sim_seconds 1.190861 # Number of seconds simulated +sim_ticks 1190860634000 # Number of ticks simulated +final_tick 1190860634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 304682 # Simulator instruction rate (inst/s) +host_op_rate 304682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 180566626 # Simulator tick rate (ticks/s) +host_mem_usage 250024 # Number of bytes of host memory used +host_seconds 6595.13 # Real time elapsed on the host sim_insts 2009421070 # Number of instructions simulated sim_ops 2009421070 # Number of ops (including micro ops) simulated -sim_seconds 1.191523 # Number of seconds simulated -sim_ticks 1191522940000 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.283547 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 179637334 # Number of BTB hits -system.cpu.branchPred.BTBLookups 223753609 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 24504 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 26222048 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 174812836 # Number of conditional branches predicted -system.cpu.branchPred.lookups 271009171 # Number of BP lookups -system.cpu.branchPred.usedRAS 40320873 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 2009421070 # Number of instructions committed -system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed -system.cpu.cpi 1.185937 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 484973463 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 484973463 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 29869.727061 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 29869.727061 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 27793.909016 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27793.909016 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 483514457 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 483514457 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 43580111000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 43580111000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003008 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003008 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 1459006 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1459006 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 40534220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40534220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458385 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458385 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64653.542435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64653.542435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62992.275671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62992.275671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 210652621 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210652621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9198582750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9198582750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 142275 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 142275 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70327 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 70327 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4532168250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4532168250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 695768359 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 695768359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 32960.294758 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32960.294758 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29448.746286 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29448.746286 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 694167078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694167078 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 52778693750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 52778693750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.002301 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002301 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 1601281 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1601281 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 70948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 70948 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45066388250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45066388250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002199 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002199 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 1530333 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530333 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 695768359 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 695768359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 32960.294758 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32960.294758 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29448.746286 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29448.746286 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 694167078 # number of overall hits -system.cpu.dcache.overall_hits::total 694167078 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 52778693750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 52778693750 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.002301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002301 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 1601281 # number of overall misses -system.cpu.dcache.overall_misses::total 1601281 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 70948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 70948 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45066388250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45066388250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002199 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002199 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 1530333 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530333 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 948 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1258 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1618 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 453.605247 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1393067051 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.559536 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.999648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999648 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 1526237 # number of replacements -system.cpu.dcache.tags.sampled_refs 1530333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1393067051 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4094.559536 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 694167078 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 828837250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks -system.cpu.dcache.writebacks::total 95962 # number of writebacks -system.cpu.discardedOps 54230447 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 722376032 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 721933722 # DTB hits -system.cpu.dtb.data_misses 442310 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 511558478 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 511131393 # DTB read hits -system.cpu.dtb.read_misses 427085 # DTB read misses -system.cpu.dtb.write_accesses 210817554 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 210802329 # DTB write hits -system.cpu.dtb.write_misses 15225 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 683609242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 683609242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20652.120610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20652.120610 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18596.962668 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18596.962668 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 683586607 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 683586607 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 467460750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 467460750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 22635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 22635 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 420942250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 420942250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 22635 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 22635 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 683609242 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 683609242 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20652.120610 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20652.120610 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18596.962668 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18596.962668 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 683586607 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 683586607 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 467460750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 467460750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 22635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 22635 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 420942250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 420942250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 22635 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 22635 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 683609242 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 683609242 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20652.120610 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20652.120610 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18596.962668 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18596.962668 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 683586607 # number of overall hits -system.cpu.icache.overall_hits::total 683586607 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 467460750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 467460750 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 22635 # number of overall misses -system.cpu.icache.overall_misses::total 22635 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 420942250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 420942250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 22635 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 22635 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1573 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 30201.758726 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1367241118 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1688.672888 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.824547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.824547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 20893 # number of replacements -system.cpu.icache.tags.sampled_refs 22634 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1367241118 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1688.672888 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 683586607 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 103732278 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.843215 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 683609362 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 683609242 # ITB hits -system.cpu.itb.fetch_misses 120 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 71948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 71948 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65940.521766 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65940.521766 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53018.517549 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53018.517549 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 5079 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4409376750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4409376750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.929407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.929407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 66869 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66869 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3545295250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3545295250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.929407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66869 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1481020 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1481020 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70256.406419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70256.406419 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57611.646625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57611.646625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 1071704 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1071704 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 28757071250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28757071250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.276374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 409316 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 409316 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23581368750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23581368750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 409316 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409316 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 95962 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 95962 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 95962 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95962 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 1552968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1552968 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69650.341779 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69650.341779 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56966.649516 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56966.649516 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 1076783 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1076783 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 33166448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33166448000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.306629 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.306629 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 476185 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 476185 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27126664000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27126664000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.306629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.306629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 476185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 1552968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1552968 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69650.341779 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69650.341779 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56966.649516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56966.649516 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 1076783 # number of overall hits -system.cpu.l2cache.overall_hits::total 1076783 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 33166448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33166448000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.306629 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.306629 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 476185 # number of overall misses -system.cpu.l2cache.overall_misses::total 476185 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27126664000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27126664000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.306629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.306629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 476185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476185 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2674 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29455 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 2.311701 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 13739527 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 1349.197229 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.044596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.041174 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997352 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 443405 # number of replacements -system.cpu.l2cache.tags.sampled_refs 476139 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 13739527 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 32681.241826 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1100691 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks -system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.numCycles 2383045880 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2279313602 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 105531456 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45269 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3201897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 920427000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 34576250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2370536750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 88568547 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1448576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104082880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 105531456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 1481020 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1481019 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 95962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 71948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 71948 # Transaction distribution -system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 34757888 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019276 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1019276 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1283589500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4535569500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 29170977 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34757888 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34757888 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 409315 # Transaction distribution -system.membus.trans_dist::ReadResp 409315 # Transaction distribution -system.membus.trans_dist::Writeback 66908 # Transaction distribution -system.membus.trans_dist::ReadExReq 66869 # Transaction distribution -system.membus.trans_dist::ReadExResp 66869 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 2193961.36 # Average gap between requests -system.physmem.avgMemAccLat 26986.02 # Average memory access latency per DRAM burst -system.physmem.avgQLat 8236.02 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 25.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.58 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.59 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 24.44 # Average write queue length when enqueuing -system.physmem.busUtil 0.23 # Data bus utilization in percentage -system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 156519 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156519 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 25577163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25577163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3593814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25577163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29170977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 3593814 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3593814 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 196329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 176.935328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 127.479402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 206.642311 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 75423 38.42% 38.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 90953 46.33% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17208 8.76% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 945 0.48% 93.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 960 0.49% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 641 0.33% 94.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1086 0.55% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 966 0.49% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8147 4.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196329 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 30457664 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 30475776 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue -system.physmem.bytesWritten 4280512 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 186496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186496 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 30475776 # Number of bytes read from this memory -system.physmem.bytes_read::total 30475776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 30476096 # Number of bytes read from this memory +system.physmem.bytes_read::total 30476096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 593665055500 # Time in different power states -system.physmem.memoryStateTime::REF 39787540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 558069752500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 476184 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 476189 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476189 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.pageHitRate 63.83 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.bw_read::cpu.inst 25591656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25591656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 156875 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156875 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3595813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3595813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3595813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25591656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29187469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476189 # Number of read requests accepted +system.physmem.writeReqs 66908 # Number of write requests accepted +system.physmem.readBursts 476189 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 30458432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue +system.physmem.bytesWritten 4280448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 30476096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4282112 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 29463 # Per bank write bursts -system.physmem.perBankRdBursts::1 29813 # Per bank write bursts -system.physmem.perBankRdBursts::2 29826 # Per bank write bursts -system.physmem.perBankRdBursts::3 29780 # Per bank write bursts -system.physmem.perBankRdBursts::4 29692 # Per bank write bursts -system.physmem.perBankRdBursts::5 29773 # Per bank write bursts -system.physmem.perBankRdBursts::6 29849 # Per bank write bursts -system.physmem.perBankRdBursts::7 29830 # Per bank write bursts -system.physmem.perBankRdBursts::8 29753 # Per bank write bursts -system.physmem.perBankRdBursts::9 29878 # Per bank write bursts -system.physmem.perBankRdBursts::10 29844 # Per bank write bursts -system.physmem.perBankRdBursts::11 29908 # Per bank write bursts +system.physmem.perBankRdBursts::1 29817 # Per bank write bursts +system.physmem.perBankRdBursts::2 29839 # Per bank write bursts +system.physmem.perBankRdBursts::3 29779 # Per bank write bursts +system.physmem.perBankRdBursts::4 29691 # Per bank write bursts +system.physmem.perBankRdBursts::5 29776 # Per bank write bursts +system.physmem.perBankRdBursts::6 29845 # Per bank write bursts +system.physmem.perBankRdBursts::7 29824 # Per bank write bursts +system.physmem.perBankRdBursts::8 29755 # Per bank write bursts +system.physmem.perBankRdBursts::9 29877 # Per bank write bursts +system.physmem.perBankRdBursts::10 29842 # Per bank write bursts +system.physmem.perBankRdBursts::11 29915 # Per bank write bursts system.physmem.perBankRdBursts::12 29785 # Per bank write bursts -system.physmem.perBankRdBursts::13 29573 # Per bank write bursts -system.physmem.perBankRdBursts::14 29507 # Per bank write bursts +system.physmem.perBankRdBursts::13 29577 # Per bank write bursts +system.physmem.perBankRdBursts::14 29501 # Per bank write bursts system.physmem.perBankRdBursts::15 29627 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts @@ -508,23 +70,31 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4334 # Per bank write bursts -system.physmem.perBankWrBursts::10 4223 # Per bank write bursts +system.physmem.perBankWrBursts::10 4222 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 4057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 115.306631 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.801532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1128.564145 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.53% 99.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 6 0.15% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 12 0.30% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4057 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 475416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 459 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1190860558500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 476189 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 66908 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 475413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -555,30 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 476184 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 476184 # Read request sizes (log2) -system.physmem.readReqs 476184 # Number of read requests accepted -system.physmem.readRowHitRate 62.16 # Row buffer hit rate for reads -system.physmem.readRowHits 295815 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 2379505000 # Total ticks spent in databus transfers -system.physmem.totGap 1191522864500 # Total gap between requests -system.physmem.totMemAccLat 12842674500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 3919530750 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 4057 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.485827 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.464369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.858223 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3072 75.72% 75.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 984 24.25% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4057 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -594,24 +140,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4057 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4056 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -643,17 +189,471 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 66908 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66908 # Write request sizes (log2) -system.physmem.writeReqs 66908 # Number of write requests accepted -system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes -system.physmem.writeRowHits 50635 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 196024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 177.216831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 127.562877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 207.494740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 75216 38.37% 38.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 90843 46.34% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 17447 8.90% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 798 0.41% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 682 0.35% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 656 0.33% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1172 0.60% 95.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1008 0.51% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8202 4.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196024 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4056 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 115.321252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.815163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1129.679023 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-14335 7 0.17% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 9 0.22% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-18431 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4056 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.489645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.468091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.860070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3063 75.52% 75.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 993 24.48% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4056 # Writes before turning the bus around for reads +system.physmem.totQLat 4642842500 # Total ticks spent queuing +system.physmem.totMemAccLat 13566211250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2379565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9755.65 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28505.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.59 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.60 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 296141 # Number of row buffer hits during reads +system.physmem.writeRowHits 50629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 62.23 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 2192721.67 # Average gap between requests +system.physmem.pageHitRate 63.88 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 589509971750 # Time in different power states +system.physmem.memoryStateTime::REF 39765440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 561585082000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 29187469 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409320 # Transaction distribution +system.membus.trans_dist::ReadResp 409320 # Transaction distribution +system.membus.trans_dist::Writeback 66908 # Transaction distribution +system.membus.trans_dist::ReadExReq 66869 # Transaction distribution +system.membus.trans_dist::ReadExResp 66869 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1019286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1019286 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34758208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 34758208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34758208 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1283694000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 4536921750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 271010035 # Number of BP lookups +system.cpu.branchPred.condPredicted 174815111 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 26224729 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 223743631 # Number of BTB lookups +system.cpu.branchPred.BTBHits 179636452 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 80.286733 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 40316732 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 27614 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 511123125 # DTB read hits +system.cpu.dtb.read_misses 428196 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 511551321 # DTB read accesses +system.cpu.dtb.write_hits 210802220 # DTB write hits +system.cpu.dtb.write_misses 15121 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 210817341 # DTB write accesses +system.cpu.dtb.data_hits 721925345 # DTB hits +system.cpu.dtb.data_misses 443317 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 722368662 # DTB accesses +system.cpu.itb.fetch_hits 682230205 # ITB hits +system.cpu.itb.fetch_misses 120 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 682230325 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 39 # Number of system calls +system.cpu.numCycles 2381721268 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2009421070 # Number of instructions committed +system.cpu.committedOps 2009421070 # Number of ops (including micro ops) committed +system.cpu.discardedOps 51480727 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.185277 # CPI: cycles per instruction +system.cpu.ipc 0.843684 # IPC: instructions per cycle +system.cpu.tickCycles 2275163827 # Number of cycles that the object actually ticked +system.cpu.idleCycles 106557441 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 20821 # number of replacements +system.cpu.icache.tags.tagsinuse 1689.662119 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 682207641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 22563 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30235.679697 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1689.662119 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.825030 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.825030 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1364482973 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1364482973 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 682207641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 682207641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 682207641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 682207641 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 682207641 # number of overall hits +system.cpu.icache.overall_hits::total 682207641 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 22564 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 22564 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 22564 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 22564 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 22564 # number of overall misses +system.cpu.icache.overall_misses::total 22564 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 467220750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 467220750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 467220750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 467220750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 467220750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 467220750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 682230205 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 682230205 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 682230205 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 682230205 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 682230205 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 682230205 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20706.468268 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20706.468268 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20706.468268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20706.468268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20706.468268 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 22564 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 22564 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 22564 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 22564 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 22564 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 22564 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 420842250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 420842250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 420842250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 420842250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 420842250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 420842250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000033 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18651.048130 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18651.048130 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18651.048130 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18651.048130 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 88620923 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1481078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1481077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71948 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71948 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45127 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156886 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3202013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1444032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104091136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 105535168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 105535168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 920456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 34470750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2371437000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 443410 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32681.250734 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1100744 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 476144 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.311788 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 1349.100172 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 31332.150562 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.041171 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956181 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2678 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29451 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13739996 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13739996 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1071757 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1071757 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 95962 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95962 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 5079 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1076836 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1076836 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1076836 # number of overall hits +system.cpu.l2cache.overall_hits::total 1076836 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 409321 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 409321 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 66869 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66869 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 476190 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 476190 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 476190 # number of overall misses +system.cpu.l2cache.overall_misses::total 476190 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29485195750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29485195750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4407101000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4407101000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 33892296750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33892296750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 33892296750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33892296750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1481078 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1481078 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 95962 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 95962 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 71948 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 71948 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1553026 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1553026 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1553026 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1553026 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.276367 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.276367 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.929407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.929407 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.306621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.306621 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.306621 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.306621 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72034.407592 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72034.407592 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65906.488806 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65906.488806 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71173.894349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71173.894349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71173.894349 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks +system.cpu.l2cache.writebacks::total 66908 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 409321 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409321 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66869 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66869 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27850437750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27850437750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.276367 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.276367 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.929407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.306621 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.306621 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.306621 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.306621 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59384.709678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59384.709678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52984.626658 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52984.626658 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58485.977761 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58485.977761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58485.977761 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58485.977761 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 1526366 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.558807 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 694159033 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1530462 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 453.561757 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 828677250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.558807 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999648 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 948 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1393051346 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1393051346 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 483506411 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 483506411 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 210652622 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210652622 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 694159033 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694159033 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 694159033 # number of overall hits +system.cpu.dcache.overall_hits::total 694159033 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 1459135 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1459135 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 142274 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 142274 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 1601409 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1601409 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1601409 # number of overall misses +system.cpu.dcache.overall_misses::total 1601409 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44310462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44310462500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9194463750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9194463750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 53504926250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53504926250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 53504926250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53504926250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 484965546 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 484965546 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 695760442 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 695760442 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 695760442 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 695760442 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.003009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000675 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000675 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.002302 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002302 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.002302 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002302 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30367.623626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30367.623626 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64625.045686 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64625.045686 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33411.156207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33411.156207 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33411.156207 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 95962 # number of writebacks +system.cpu.dcache.writebacks::total 95962 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 621 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 621 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 70947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 70947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1458514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1458514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 71948 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71948 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1530462 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1530462 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1530462 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1530462 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41263033500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41263033500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4529893000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4529893000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 45792926500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45792926500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 45792926500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45792926500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003007 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002200 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002200 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002200 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28291.146674 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28291.146674 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62960.652138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62960.652138 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 29920.982357 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29920.982357 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 8796e7316..5d39af8d6 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,526 +1,101 @@ ---------- Begin Simulation Statistics ---------- -final_tick 58437370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 298644 # Simulator instruction rate (inst/s) -host_mem_usage 257212 # Number of bytes of host memory used -host_op_rate 298644 # Simulator op (including micro ops) rate (op/s) -host_seconds 296.13 # Real time elapsed on the host -host_tick_rate 197335322 # Simulator tick rate (ticks/s) +sim_seconds 0.058331 # Number of seconds simulated +sim_ticks 58330740000 # Number of ticks simulated +final_tick 58330740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 186275 # Simulator instruction rate (inst/s) +host_op_rate 186275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 122860334 # Simulator tick rate (ticks/s) +host_mem_usage 249156 # Number of bytes of host memory used +host_seconds 474.77 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated -sim_seconds 0.058437 # Number of seconds simulated -sim_ticks 58437370000 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.309910 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 6368851 # Number of BTB hits -system.cpu.branchPred.BTBLookups 10059801 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 72966 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 375118 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 9451361 # Number of conditional branches predicted -system.cpu.branchPred.lookups 14600308 # Number of BP lookups -system.cpu.branchPred.usedRAS 1701571 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 88438073 # Number of instructions committed -system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.cpi 1.321543 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 20357517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20357517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 49316.405682 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49316.405682 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39545.722557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39545.722557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 20268112 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20268112 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4409133250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4409133250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 89405 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89405 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28095 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28095 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2424548250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2424548250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 61310 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61310 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 70753.026587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70753.026587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69179.575454 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69179.575454 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 14333276 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333276 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 19817993500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19817993500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019167 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019167 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 280101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280101 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136536 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136536 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9931765750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931765750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 143565 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143565 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 34970894 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34970894 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 65566.260764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65566.260764 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60311.477730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60311.477730 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 34601388 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34601388 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 24227126750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24227126750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.010566 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010566 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 369506 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369506 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 164631 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164631 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12356314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12356314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005858 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005858 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 204875 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204875 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 34970894 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34970894 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 65566.260764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65566.260764 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60311.477730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60311.477730 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 34601388 # number of overall hits -system.cpu.dcache.overall_hits::total 34601388 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 24227126750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24227126750 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.010566 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010566 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 369506 # number of overall misses -system.cpu.dcache.overall_misses::total 369506 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 164631 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164631 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12356314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12356314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005858 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005858 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 204875 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204875 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 730 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3314 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 168.890240 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 70146663 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4071.465989 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.994010 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994010 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 200779 # number of replacements -system.cpu.dcache.tags.sampled_refs 204875 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 70146663 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4071.465989 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34601388 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 644810250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 168548 # number of writebacks -system.cpu.dcache.writebacks::total 168548 # number of writebacks -system.cpu.discardedOps 1195680 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 35330623 # DTB accesses -system.cpu.dtb.data_acv 9 # DTB access violations -system.cpu.dtb.data_hits 35224185 # DTB hits -system.cpu.dtb.data_misses 106438 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 20656247 # DTB read accesses -system.cpu.dtb.read_acv 9 # DTB read access violations -system.cpu.dtb.read_hits 20558934 # DTB read hits -system.cpu.dtb.read_misses 97313 # DTB read misses -system.cpu.dtb.write_accesses 14674376 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 14665251 # DTB write hits -system.cpu.dtb.write_misses 9125 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 25515682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25515682 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16238.011767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16238.011767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14217.821664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14217.821664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 25361176 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25361176 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2508870246 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2508870246 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006055 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006055 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 154506 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 154506 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2196738754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2196738754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006055 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154506 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 154506 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 25515682 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25515682 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16238.011767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16238.011767 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14217.821664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14217.821664 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 25361176 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25361176 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 2508870246 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2508870246 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.006055 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006055 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 154506 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 154506 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2196738754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2196738754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006055 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 154506 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 154506 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 25515682 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25515682 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16238.011767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16238.011767 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14217.821664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14217.821664 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 25361176 # number of overall hits -system.cpu.icache.overall_hits::total 25361176 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 2508870246 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2508870246 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.006055 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006055 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 154506 # number of overall misses -system.cpu.icache.overall_misses::total 154506 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2196738754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2196738754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006055 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006055 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 154506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 154506 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 164.144694 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 51185869 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1934.490309 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944575 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944575 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 152457 # number of replacements -system.cpu.icache.tags.sampled_refs 154505 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 51185869 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1934.490309 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25361176 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41486335250 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 25710116 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.756691 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 25520848 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 25515682 # ITB hits -system.cpu.itb.fetch_misses 5166 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 143566 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143566 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73817.546091 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73817.546091 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60944.031219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60944.031219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 12685 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12685 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9661314250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9661314250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.911643 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911643 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 130881 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7976415750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7976415750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.911643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911643 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 215815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 215815 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72877.172362 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72877.172362 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60213.094339 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60213.094339 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 180082 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180082 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 2604120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2604120000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.165572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.165572 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 35733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 2151594500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2151594500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.165572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.165572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 35733 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35733 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 168548 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168548 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 168548 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168548 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 359381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 359381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73615.868114 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 192767 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 192767 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 12265434250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12265434250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.463614 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 166614 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166614 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10128010250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10128010250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.463614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 166614 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166614 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 359381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 359381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73615.868114 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73615.868114 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60787.270277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60787.270277 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 192767 # number of overall hits -system.cpu.l2cache.overall_hits::total 192767 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 12265434250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12265434250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.463614 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 166614 # number of overall misses -system.cpu.l2cache.overall_misses::total 166614 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10128010250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10128010250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.463614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 166614 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166614 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 993 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12007 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18840 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 1.331233 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 4531761 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 26227.699402 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4243.729621 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800406 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129508 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.929914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 132687 # number of replacements -system.cpu.l2cache.tags.sampled_refs 164763 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 4531761 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 30471.429023 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 219338 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 114047 # number of writebacks -system.cpu.l2cache.writebacks::total 114047 # number of writebacks -system.cpu.numCycles 116874740 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 91164624 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 33787392 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309011 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887309 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 432512500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233318246 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 578181256 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9888320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 33787392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 215815 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 215814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168548 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 17962240 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447273 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 1301422000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1600112750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 307375914 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17962240 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 35732 # Transaction distribution -system.membus.trans_dist::ReadResp 35732 # Transaction distribution -system.membus.trans_dist::Writeback 114047 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 208214.01 # Average gap between requests -system.physmem.avgMemAccLat 30471.23 # Average memory access latency per DRAM burst -system.physmem.avgQLat 11721.23 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 182.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.47 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 124.87 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.90 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing -system.physmem.busUtil 2.40 # Data bus utilization in percentage -system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 8825038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8825038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 182472825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182472825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124903089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 182472825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 307375914 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 124903089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124903089 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 54430 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.948631 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.734417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.314792 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19369 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11718 21.53% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5622 10.33% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3646 6.70% 74.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2769 5.09% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2059 3.78% 83.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1651 3.03% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1489 2.74% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6107 11.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54430 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 10662720 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 10663232 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 10662976 # Number of bytes read from this memory +system.physmem.bytes_read::total 10662976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299200 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299200 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 166609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166609 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114050 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114050 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 182802001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 182802001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8833490 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8833490 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 125134706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 125134706 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 125134706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 182802001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 307936707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166609 # Number of read requests accepted +system.physmem.writeReqs 114050 # Number of write requests accepted +system.physmem.readBursts 166609 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114050 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10662464 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7296960 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 515712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515712 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 10663232 # Number of bytes read from this memory -system.physmem.bytes_read::total 10663232 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 31940805250 # Time in different power states -system.physmem.memoryStateTime::REF 1951300000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24543978500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytesWritten 7297728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10662976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299200 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 166613 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166613 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory -system.physmem.pageHitRate 80.59 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 10468 # Per bank write bursts -system.physmem.perBankRdBursts::1 10509 # Per bank write bursts +system.physmem.perBankRdBursts::0 10471 # Per bank write bursts +system.physmem.perBankRdBursts::1 10513 # Per bank write bursts system.physmem.perBankRdBursts::2 10311 # Per bank write bursts system.physmem.perBankRdBursts::3 10091 # Per bank write bursts -system.physmem.perBankRdBursts::4 10432 # Per bank write bursts -system.physmem.perBankRdBursts::5 10432 # Per bank write bursts -system.physmem.perBankRdBursts::6 9848 # Per bank write bursts -system.physmem.perBankRdBursts::7 10303 # Per bank write bursts -system.physmem.perBankRdBursts::8 10590 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10591 # Per bank write bursts -system.physmem.perBankRdBursts::11 10256 # Per bank write bursts -system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::4 10430 # Per bank write bursts +system.physmem.perBankRdBursts::5 10425 # Per bank write bursts +system.physmem.perBankRdBursts::6 9845 # Per bank write bursts +system.physmem.perBankRdBursts::7 10301 # Per bank write bursts +system.physmem.perBankRdBursts::8 10592 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10594 # Per bank write bursts +system.physmem.perBankRdBursts::11 10255 # Per bank write bursts +system.physmem.perBankRdBursts::12 10302 # Per bank write bursts system.physmem.perBankRdBursts::13 10654 # Per bank write bursts -system.physmem.perBankRdBursts::14 10527 # Per bank write bursts +system.physmem.perBankRdBursts::14 10528 # Per bank write bursts system.physmem.perBankRdBursts::15 10647 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::3 6999 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7096 # Per bank write bursts +system.physmem.perBankWrBursts::7 7089 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::10 7095 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts system.physmem.perBankWrBursts::12 6965 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 7018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.736820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.923098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7017 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7018 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 164979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 58330713500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166609 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114050 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -550,36 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 166613 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166613 # Read request sizes (log2) -system.physmem.readReqs 166613 # Number of read requests accepted -system.physmem.readRowHitRate 86.96 # Row buffer hit rate for reads -system.physmem.readRowHits 144887 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 833025000 # Total ticks spent in databus transfers -system.physmem.totGap 58437343500 # Total gap between requests -system.physmem.totMemAccLat 5076659000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 1952815250 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.246082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.230651 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.740530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 89.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 591 8.42% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 122 1.74% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.37% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -595,28 +140,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7033 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 7035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -644,17 +189,472 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114047 # Write request sizes (log2) -system.physmem.writeReqs 114047 # Number of write requests accepted -system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes -system.physmem.writeRowHits 81299 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 54540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 329.285515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.168705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.681094 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19405 35.58% 35.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11848 21.72% 57.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5629 10.32% 67.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3624 6.64% 74.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2728 5.00% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2044 3.75% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1598 2.93% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1491 2.73% 88.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6173 11.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54540 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7020 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.731339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.912038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7019 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7020 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7020 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.243162 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.227940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737137 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6260 89.17% 89.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.21% 89.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 596 8.49% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 118 1.68% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 21 0.30% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 7 0.10% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7020 # Writes before turning the bus around for reads +system.physmem.totQLat 1961331500 # Total ticks spent queuing +system.physmem.totMemAccLat 5085100250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11772.63 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30522.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 182.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 125.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 182.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 125.13 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.41 # Data bus utilization in percentage +system.physmem.busUtilRead 1.43 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.98 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.77 # Average write queue length when enqueuing +system.physmem.readRowHits 144790 # Number of row buffer hits during reads +system.physmem.writeRowHits 81289 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.27 # Row buffer hit rate for writes +system.physmem.avgGap 207834.82 # Average gap between requests +system.physmem.pageHitRate 80.56 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31870385750 # Time in different power states +system.physmem.memoryStateTime::REF 1947660000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24509026750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 307936707 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35729 # Transaction distribution +system.membus.trans_dist::ReadResp 35729 # Transaction distribution +system.membus.trans_dist::Writeback 114050 # Transaction distribution +system.membus.trans_dist::ReadExReq 130880 # Transaction distribution +system.membus.trans_dist::ReadExResp 130880 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447268 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447268 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17962176 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17962176 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1302300000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1600619750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 14594378 # Number of BP lookups +system.cpu.branchPred.condPredicted 9449120 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 378858 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10404778 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6369492 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 61.216991 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1700724 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 73182 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20554057 # DTB read hits +system.cpu.dtb.read_misses 96859 # DTB read misses +system.cpu.dtb.read_acv 9 # DTB read access violations +system.cpu.dtb.read_accesses 20650916 # DTB read accesses +system.cpu.dtb.write_hits 14665861 # DTB write hits +system.cpu.dtb.write_misses 9387 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 14675248 # DTB write accesses +system.cpu.dtb.data_hits 35219918 # DTB hits +system.cpu.dtb.data_misses 106246 # DTB misses +system.cpu.dtb.data_acv 9 # DTB access violations +system.cpu.dtb.data_accesses 35326164 # DTB accesses +system.cpu.itb.fetch_hits 25539378 # ITB hits +system.cpu.itb.fetch_misses 5182 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 25544560 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4583 # Number of system calls +system.cpu.numCycles 116661480 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 88438073 # Number of instructions committed +system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1184669 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.319132 # CPI: cycles per instruction +system.cpu.ipc 0.758074 # IPC: instructions per cycle +system.cpu.tickCycles 90786920 # Number of cycles that the object actually ticked +system.cpu.idleCycles 25874560 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 152636 # number of replacements +system.cpu.icache.tags.tagsinuse 1933.709390 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25384693 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 154684 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 164.106779 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 41485931250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1933.709390 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.944194 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.944194 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1042 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 799 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51233440 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51233440 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25384693 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25384693 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25384693 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25384693 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25384693 # number of overall hits +system.cpu.icache.overall_hits::total 25384693 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 154685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 154685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 154685 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 154685 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 154685 # number of overall misses +system.cpu.icache.overall_misses::total 154685 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2511936746 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2511936746 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2511936746 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2511936746 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2511936746 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2511936746 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25539378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25539378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25539378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25539378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25539378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25539378 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006057 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006057 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006057 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006057 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006057 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006057 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16239.045454 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16239.045454 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16239.045454 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16239.045454 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16239.045454 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154685 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154685 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154685 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154685 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154685 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154685 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2199492254 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2199492254 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2199492254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2199492254 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2199492254 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2199492254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006057 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006057 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006057 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006057 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14219.169629 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14219.169629 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14219.169629 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14219.169629 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 579413736 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 215991 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 215990 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143563 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 309369 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887642 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9899776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 33797632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 33797632 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 432579500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 233564246 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 34966953 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34966953 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 34966953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34966953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.004393 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004393 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.010568 # 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average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168535 # number of writebacks +system.cpu.dcache.writebacks::total 168535 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 28102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28102 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 136550 # 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number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2427134250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2427134250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 9937233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9937233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12364367750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12364367750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12364367750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12364367750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003012 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005859 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.005859 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005859 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 39589.838844 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39589.838844 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 69219.107424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69219.107424 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60352.555780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60352.555780 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index ce74a2918..a19ba8014 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,551 +1,49 @@ ---------- Begin Simulation Statistics ---------- +sim_seconds 0.064367 # Number of seconds simulated +sim_ticks 64366581500 # Number of ticks simulated final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 178791 # Simulator instruction rate (inst/s) -host_mem_usage 302756 # Number of bytes of host memory used -host_op_rate 253719 # Simulator op (including micro ops) rate (op/s) -host_seconds 396.64 # Real time elapsed on the host -host_tick_rate 162280857 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 99170 # Simulator instruction rate (inst/s) +host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90012135 # Simulator tick rate (ticks/s) +host_mem_usage 295432 # Number of bytes of host memory used +host_seconds 715.09 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 100634375 # Number of ops (including micro ops) simulated -sim_seconds 0.064367 # Number of seconds simulated -sim_ticks 64366581500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits -system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted -system.cpu.branchPred.lookups 16883830 # Number of BP lookups -system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 70915127 # Number of instructions committed -system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed -system.cpu.cpi 1.815313 # CPI: cycles per instruction -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38199.338598 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38199.338598 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.609683 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.609683 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169340439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2169340439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001786311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001786311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73771.399808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73771.399808 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.202050 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.202050 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315459000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15315459000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591658250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591658250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66130.854128 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 17484799439 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17484799439 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593444561 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9593444561 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.854128 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66130.854128 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59601.049701 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59601.049701 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits -system.cpu.dcache.overall_hits::total 47220249 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 17484799439 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17484799439 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses -system.cpu.dcache.overall_misses::total 264397 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593444561 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9593444561 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 156865 # number of replacements -system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks -system.cpu.dcache.writebacks::total 128565 # number of writebacks -system.cpu.discardedOps 2952330 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19971.672117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19971.672117 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17929.897070 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17929.897070 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 910009240 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 910009240 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816975760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 816975760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19971.672117 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 910009240 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 910009240 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816975760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 816975760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19971.672117 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19971.672117 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17929.897070 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17929.897070 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits -system.cpu.icache.overall_hits::total 27427302 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 910009240 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 910009240 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses -system.cpu.icache.overall_misses::total 45565 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816975760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 816975760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297147 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 43522 # number of replacements -system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1864.297147 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 19565206 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.550869 # IPC: instructions per cycle -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.821477 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.821477 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.466837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.466837 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436940250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7436940250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118068750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118068750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74187.493019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74187.493019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61477.049578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61477.049578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992453500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1992453500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646724250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646724250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73025.880162 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 9429393750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9429393750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764793000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7764793000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73025.880162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73025.880162 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60167.473829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60167.473829 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits -system.cpu.l2cache.overall_hits::total 77402 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 9429393750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9429393750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses -system.cpu.l2cache.overall_misses::total 129124 # number of overall misses -system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764793000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7764793000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 26739.141291 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.835051 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 95911 # number of replacements -system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 30027.976342 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks -system.cpu.l2cache.writebacks::total 83957 # number of writebacks -system.cpu.numCycles 128733163 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 109167957 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 269478939 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 13632576 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 975516000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1243562500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 211795868 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 26785 # Transaction distribution -system.membus.trans_dist::ReadResp 26785 # Transaction distribution -system.membus.trans_dist::Writeback 83957 # Transaction distribution -system.membus.trans_dist::ReadExReq 102267 # Transaction distribution -system.membus.trans_dist::ReadExResp 102267 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 302177.61 # Average gap between requests -system.physmem.avgMemAccLat 30050.93 # Average memory access latency per DRAM burst -system.physmem.avgQLat 11300.93 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing -system.physmem.busUtil 1.65 # Data bus utilization in percentage -system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory +system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory +system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.915649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.657943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2766 7.13% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 6.62% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1673 4.31% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1314 3.38% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1198 3.09% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4478 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation +system.physmem.readReqs 129052 # Number of read requests accepted +system.physmem.writeReqs 83957 # Number of write requests accepted +system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory -system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 37439884750 # Time in different power states -system.physmem.memoryStateTime::REF 2149160000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24772371500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory -system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.perBankRdBursts::0 8196 # Per bank write bursts system.physmem.perBankRdBursts::1 8381 # Per bank write bursts system.physmem.perBankRdBursts::2 8249 # Per bank write bursts @@ -578,14 +76,23 @@ system.physmem.perBankWrBursts::12 5344 # Pe system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts system.physmem.perBankWrBursts::15 5227 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 83957 # Write request sizes (log2) system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see @@ -618,37 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 129052 # Read request sizes (log2) -system.physmem.readReqs 129052 # Number of read requests accepted -system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads -system.physmem.readRowHits 112129 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers -system.physmem.totGap 64366550000 # Total gap between requests -system.physmem.totMemAccLat 3877921750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 1458328000 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -713,17 +189,541 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83957 # Write request sizes (log2) -system.physmem.writeReqs 83957 # Number of write requests accepted -system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads +system.physmem.totQLat 1458157250 # Total ticks spent queuing +system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.65 # Data bus utilization in percentage +system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing +system.physmem.readRowHits 112129 # Number of row buffer hits during reads system.physmem.writeRowHits 62016 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes +system.physmem.avgGap 302177.61 # Average gap between requests +system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states +system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 211795868 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26785 # Transaction distribution +system.membus.trans_dist::ReadResp 26785 # Transaction distribution +system.membus.trans_dist::Writeback 83957 # Transaction distribution +system.membus.trans_dist::ReadExReq 102267 # Transaction distribution +system.membus.trans_dist::ReadExResp 102267 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 16883830 # Number of BP lookups +system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 1946 # Number of system calls +system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 70915127 # Number of instructions committed +system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.815313 # CPI: cycles per instruction +system.cpu.ipc 0.550869 # IPC: instructions per cycle +system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 43522 # number of replacements +system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses +system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits +system.cpu.icache.overall_hits::total 27427302 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses +system.cpu.icache.overall_misses::total 45565 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 95911 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128565 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses +system.cpu.l2cache.overall_misses::total 129124 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992283500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1992283500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436939000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7436939000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9429222500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9429222500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9429222500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9429222500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks::writebacks 83957 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7764622250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 156865 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits +system.cpu.dcache.overall_hits::total 47220249 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses +system.cpu.dcache.overall_misses::total 264397 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks +system.cpu.dcache.writebacks::total 128565 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 8b5bdef98..fd5fa200e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,533 +1,100 @@ ---------- Begin Simulation Statistics ---------- -final_tick 1183291184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 268503 # Simulator instruction rate (inst/s) -host_mem_usage 248104 # Number of bytes of host memory used -host_op_rate 268503 # Simulator op (including micro ops) rate (op/s) -host_seconds 6802.08 # Real time elapsed on the host -host_tick_rate 173960186 # Simulator tick rate (ticks/s) +sim_seconds 1.181828 # Number of seconds simulated +sim_ticks 1181828044500 # Number of ticks simulated +final_tick 1181828044500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 296156 # Simulator instruction rate (inst/s) +host_op_rate 296156 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191639126 # Simulator tick rate (ticks/s) +host_mem_usage 241048 # Number of bytes of host memory used +host_seconds 6166.95 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated -sim_seconds 1.183291 # Number of seconds simulated -sim_ticks 1183291184500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.726550 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 164028132 # Number of BTB hits -system.cpu.branchPred.BTBLookups 166143892 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 101063 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 15659000 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 184956948 # Number of conditional branches predicted -system.cpu.branchPred.lookups 244507485 # Number of BP lookups -system.cpu.branchPred.usedRAS 18318035 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 1826378509 # Number of instructions committed -system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.cpi 1.295779 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 448787942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 448787942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24412.387640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24412.387640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22378.762178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22378.762178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 441498317 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441498317 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 177957151250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177957151250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.016243 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016243 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 7289625 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289625 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 161995965500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 161995965500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016130 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016130 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7238826 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238826 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45036.490101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45036.490101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40206.712752 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40206.712752 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 158490258 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158490258 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 100802653750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100802653750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.013926 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013926 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2238244 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238244 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 350933 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 350933 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75882571250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75882571250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887311 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887311 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 609516444 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 609516444 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29257.308743 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 599988575 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 599988575 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 278759805000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278759805000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.015632 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015632 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 9527869 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9527869 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 401732 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401732 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237878536750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 237878536750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014973 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 9126137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126137 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 609516444 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 609516444 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29257.308743 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29257.308743 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26065.632890 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26065.632890 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 599988575 # number of overall hits -system.cpu.dcache.overall_hits::total 599988575 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 278759805000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278759805000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.015632 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015632 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 9527869 # number of overall misses -system.cpu.dcache.overall_misses::total 9527869 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 401732 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401732 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237878536750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 237878536750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014973 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014973 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 9126137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126137 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2338 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 65.743981 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 1228159025 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 4080.562725 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.996231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996231 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 9122041 # number of replacements -system.cpu.dcache.tags.sampled_refs 9126137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 1228159025 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 4080.562725 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 599988575 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16716397000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 3700613 # number of writebacks -system.cpu.dcache.writebacks::total 3700613 # number of writebacks -system.cpu.discardedOps 50078248 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 620722700 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 614030991 # DTB hits -system.cpu.dtb.data_misses 6691709 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 457660877 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 452677890 # DTB read hits -system.cpu.dtb.read_misses 4982987 # DTB read misses -system.cpu.dtb.write_accesses 163061823 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 161353101 # DTB write hits -system.cpu.dtb.write_misses 1708722 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 592077907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 592077907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74367.693111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74367.693111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71956.941545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71956.941545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 592076949 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 592076949 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71244250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71244250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68934750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68934750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # 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number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 71244250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71244250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68934750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68934750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 958 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 592077907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 592077907 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74367.693111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74367.693111 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71956.941545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71956.941545 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 592076949 # number of overall hits -system.cpu.icache.overall_hits::total 592076949 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 71244250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71244250 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68934750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68934750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 958 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 618034.393528 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 1184156772 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 750.687488 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.366547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.366547 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 1184156772 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 750.687488 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 592076949 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 321001841 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.771737 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 592077926 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 592077907 # ITB hits -system.cpu.itb.fetch_misses 19 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1887311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80641.484731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80641.484731 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68018.096944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68018.096944 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 1107870 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107870 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 62855279500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 62855279500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 779441 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 779441 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 53016093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53016093500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 779441 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779441 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7239784 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7239784 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79744.744851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79744.744851 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67168.011379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67168.011379 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 6058181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 94226629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94226629750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 1181603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1181603 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 79365923750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79365923750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163210 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1181603 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181603 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700613 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 3700613 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700613 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 9127095 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127095 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80101.165119 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 7166051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7166051 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 157081909250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 157081909250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.214860 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214860 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 1961044 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1961044 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132382017250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132382017250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214860 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1961044 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961044 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 9127095 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127095 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80101.165119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80101.165119 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67505.888318 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 7166051 # number of overall hits -system.cpu.l2cache.overall_hits::total 7166051 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 157081909250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157081909250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.214860 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214860 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 1961044 # number of overall misses -system.cpu.l2cache.overall_misses::total 1961044 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132382017250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132382017250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214860 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1961044 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961044 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1231 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12870 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15515 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 4.586945 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 106467088 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 14930.905733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15810.667479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.455655 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.482503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938158 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 1928309 # number of replacements -system.cpu.l2cache.tags.sampled_refs 1958113 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 106467088 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 30741.573213 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981756 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 88668325250 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::writebacks 1018252 # number of writebacks -system.cpu.l2cache.writebacks::total 1018252 # number of writebacks -system.cpu.numCycles 2366582369 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 2045580528 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 820973312 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1916 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952887 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954803 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 10114467000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1633750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14012915250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 693804976 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820912000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 820973312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 7239784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887311 # Transaction distribution -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 190674944 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940340 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940340 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 11933306500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18491731750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 161139495 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190674944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 190674944 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 1181603 # Transaction distribution -system.membus.trans_dist::ReadResp 1181603 # Transaction distribution -system.membus.trans_dist::Writeback 1018252 # Transaction distribution -system.membus.trans_dist::ReadExReq 779441 # Transaction distribution -system.membus.trans_dist::ReadExResp 779441 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 397171.37 # Average gap between requests -system.physmem.avgMemAccLat 37373.81 # Average memory access latency per DRAM burst -system.physmem.avgQLat 18623.81 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 106.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.07 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrBW 55.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 55.07 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 25.40 # Average write queue length when enqueuing -system.physmem.busUtil 1.26 # Data bus utilization in percentage -system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 51815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 106065876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106065876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55073619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106065876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 161139495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_write::writebacks 55073619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55073619 # Write bandwidth from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 1832587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 104.000528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.206567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.424181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1451916 79.23% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 263842 14.40% 93.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49021 2.67% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20912 1.14% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12920 0.71% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7284 0.40% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5395 0.29% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4101 0.22% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17196 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1832587 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 125427328 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 125506816 # Total read bytes from the system interface side -system.physmem.bytesReadWrQ 79488 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166528 # Total number of bytes written to DRAM -system.physmem.bytesWrittenSys 65168128 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 125506816 # Number of bytes read from this memory -system.physmem.bytes_read::total 125506816 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 65168128 # Number of bytes written to this memory -system.physmem.bytes_written::total 65168128 # Number of bytes written to this memory -system.physmem.memoryStateTime::IDLE 388135850750 # Time in different power states -system.physmem.memoryStateTime::REF 39512460000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 755636161750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.bytes_read::cpu.inst 125507328 # Number of bytes read from this memory +system.physmem.bytes_read::total 125507328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65168512 # Number of bytes written to this memory +system.physmem.bytes_written::total 65168512 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1961052 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018258 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018258 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 106197622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106197622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 51825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 51825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55142127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55142127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55142127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 106197622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 161339749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961052 # Number of read requests accepted +system.physmem.writeReqs 1018258 # Number of write requests accepted +system.physmem.readBursts 1961052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018258 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125425344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81984 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125507328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65168512 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1281 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 1961044 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961044 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018252 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018252 # Number of write requests responded to by this memory -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 118755 # Per bank write bursts +system.physmem.perBankRdBursts::0 118745 # Per bank write bursts system.physmem.perBankRdBursts::1 114099 # Per bank write bursts -system.physmem.perBankRdBursts::2 116230 # Per bank write bursts -system.physmem.perBankRdBursts::3 117769 # Per bank write bursts -system.physmem.perBankRdBursts::4 117839 # Per bank write bursts -system.physmem.perBankRdBursts::5 117521 # Per bank write bursts -system.physmem.perBankRdBursts::6 119889 # Per bank write bursts -system.physmem.perBankRdBursts::7 124535 # Per bank write bursts -system.physmem.perBankRdBursts::8 126979 # Per bank write bursts -system.physmem.perBankRdBursts::9 130093 # Per bank write bursts -system.physmem.perBankRdBursts::10 128642 # Per bank write bursts +system.physmem.perBankRdBursts::2 116228 # Per bank write bursts +system.physmem.perBankRdBursts::3 117773 # Per bank write bursts +system.physmem.perBankRdBursts::4 117823 # Per bank write bursts +system.physmem.perBankRdBursts::5 117515 # Per bank write bursts +system.physmem.perBankRdBursts::6 119886 # Per bank write bursts +system.physmem.perBankRdBursts::7 124512 # Per bank write bursts +system.physmem.perBankRdBursts::8 126980 # Per bank write bursts +system.physmem.perBankRdBursts::9 130096 # Per bank write bursts +system.physmem.perBankRdBursts::10 128651 # Per bank write bursts system.physmem.perBankRdBursts::11 130358 # Per bank write bursts -system.physmem.perBankRdBursts::12 126048 # Per bank write bursts -system.physmem.perBankRdBursts::13 125260 # Per bank write bursts -system.physmem.perBankRdBursts::14 122592 # Per bank write bursts -system.physmem.perBankRdBursts::15 123193 # Per bank write bursts -system.physmem.perBankWrBursts::0 61221 # Per bank write bursts -system.physmem.perBankWrBursts::1 61486 # Per bank write bursts -system.physmem.perBankWrBursts::2 60571 # Per bank write bursts -system.physmem.perBankWrBursts::3 61239 # Per bank write bursts +system.physmem.perBankRdBursts::12 126070 # Per bank write bursts +system.physmem.perBankRdBursts::13 125261 # Per bank write bursts +system.physmem.perBankRdBursts::14 122591 # Per bank write bursts +system.physmem.perBankRdBursts::15 123183 # Per bank write bursts +system.physmem.perBankWrBursts::0 61220 # Per bank write bursts +system.physmem.perBankWrBursts::1 61482 # Per bank write bursts +system.physmem.perBankWrBursts::2 60570 # Per bank write bursts +system.physmem.perBankWrBursts::3 61238 # Per bank write bursts system.physmem.perBankWrBursts::4 61663 # Per bank write bursts -system.physmem.perBankWrBursts::5 63103 # Per bank write bursts -system.physmem.perBankWrBursts::6 64150 # Per bank write bursts -system.physmem.perBankWrBursts::7 65615 # Per bank write bursts -system.physmem.perBankWrBursts::8 65333 # Per bank write bursts -system.physmem.perBankWrBursts::9 65778 # Per bank write bursts -system.physmem.perBankWrBursts::10 65294 # Per bank write bursts -system.physmem.perBankWrBursts::11 65644 # Per bank write bursts -system.physmem.perBankWrBursts::12 64163 # Per bank write bursts -system.physmem.perBankWrBursts::13 64209 # Per bank write bursts -system.physmem.perBankWrBursts::14 64571 # Per bank write bursts -system.physmem.perBankWrBursts::15 64187 # Per bank write bursts -system.physmem.rdPerTurnAround::samples 59249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.075495 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 165.201868 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59213 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 8 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59249 # Reads before turning the bus around for writes -system.physmem.rdQLenPdf::0 1833824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125960 # What read queue length does an incoming req see +system.physmem.perBankWrBursts::5 63102 # Per bank write bursts +system.physmem.perBankWrBursts::6 64153 # Per bank write bursts +system.physmem.perBankWrBursts::7 65613 # Per bank write bursts +system.physmem.perBankWrBursts::8 65334 # Per bank write bursts +system.physmem.perBankWrBursts::9 65779 # Per bank write bursts +system.physmem.perBankWrBursts::10 65298 # Per bank write bursts +system.physmem.perBankWrBursts::11 65646 # Per bank write bursts +system.physmem.perBankWrBursts::12 64168 # Per bank write bursts +system.physmem.perBankWrBursts::13 64213 # Per bank write bursts +system.physmem.perBankWrBursts::14 64569 # Per bank write bursts +system.physmem.perBankWrBursts::15 64185 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 1181827934500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1961052 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 1018258 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1833401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 126352 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -558,37 +125,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 1961044 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961044 # Read request sizes (log2) -system.physmem.readReqs 1961044 # Number of read requests accepted -system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads -system.physmem.readRowHits 729960 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 1242 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 9799010000 # Total ticks spent in databus transfers -system.physmem.totGap 1183291074500 # Total gap between requests -system.physmem.totMemAccLat 73245258000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 36498970500 # Total ticks spent queuing -system.physmem.wrPerTurnAround::samples 59249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.185556 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.149947 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.108422 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 25999 43.88% 43.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1383 2.33% 46.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 27359 46.18% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4006 6.76% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 414 0.70% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 70 0.12% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59249 # Writes before turning the bus around for reads system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -604,31 +140,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 59784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59740 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 59781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 59768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59810 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 59797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 60664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 60699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -653,17 +189,482 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 1018252 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018252 # Write request sizes (log2) -system.physmem.writeReqs 1018252 # Number of write requests accepted -system.physmem.writeRowHitRate 40.80 # Row buffer hit rate for writes -system.physmem.writeRowHits 415473 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.bytesPerActivate::samples 1832736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.991479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.204587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.379474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1452314 79.24% 79.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 263429 14.37% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49355 2.69% 96.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20877 1.14% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12925 0.71% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7130 0.39% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5386 0.29% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4144 0.23% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17176 0.94% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1832736 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59244 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.077763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.502392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59205 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 59244 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59244 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.187108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.151334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.111623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26003 43.89% 43.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1351 2.28% 46.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 27334 46.14% 92.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4039 6.82% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 439 0.74% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 54 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 3 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59244 # Writes before turning the bus around for reads +system.physmem.totQLat 36544904000 # Total ticks spent queuing +system.physmem.totMemAccLat 73290610250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18647.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 37397.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 55.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 55.14 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 1.26 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.43 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing +system.physmem.readRowHits 730029 # Number of row buffer hits during reads +system.physmem.writeRowHits 415229 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.78 # Row buffer hit rate for writes +system.physmem.avgGap 396678.40 # Average gap between requests +system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 386610550250 # Time in different power states +system.physmem.memoryStateTime::REF 39463580000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 755746527250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 161339749 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1181614 # Transaction distribution +system.membus.trans_dist::ReadResp 1181614 # Transaction distribution +system.membus.trans_dist::Writeback 1018258 # Transaction distribution +system.membus.trans_dist::ReadExReq 779438 # Transaction distribution +system.membus.trans_dist::ReadExResp 779438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940362 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940362 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190675840 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190675840 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190675840 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11933572000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 18494807500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 244429252 # Number of BP lookups +system.cpu.branchPred.condPredicted 184894637 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15662499 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 166226175 # Number of BTB lookups +system.cpu.branchPred.BTBHits 163968290 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 98.641679 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18313425 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 99980 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 452571491 # DTB read hits +system.cpu.dtb.read_misses 4982965 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 457554456 # DTB read accesses +system.cpu.dtb.write_hits 161354418 # DTB write hits +system.cpu.dtb.write_misses 1708765 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 163063183 # DTB write accesses +system.cpu.dtb.data_hits 613925909 # DTB hits +system.cpu.dtb.data_misses 6691730 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 620617639 # DTB accesses +system.cpu.itb.fetch_hits 591482700 # ITB hits +system.cpu.itb.fetch_misses 19 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 591482719 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 29 # Number of system calls +system.cpu.numCycles 2363656089 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1826378509 # Number of instructions committed +system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed +system.cpu.discardedOps 49661954 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.294176 # CPI: cycles per instruction +system.cpu.ipc 0.772692 # IPC: instructions per cycle +system.cpu.tickCycles 2043068356 # Number of cycles that the object actually ticked +system.cpu.idleCycles 320587733 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 3 # number of replacements +system.cpu.icache.tags.tagsinuse 750.459785 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 591481743 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 618058.247649 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 750.459785 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366435 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1182966357 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1182966357 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 591481743 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 591481743 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 591481743 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 591481743 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 591481743 # number of overall hits +system.cpu.icache.overall_hits::total 591481743 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70550250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70550250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70550250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70550250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70550250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70550250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 591482700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 591482700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 591482700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 591482700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 591482700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 591482700 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73720.219436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73720.219436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73720.219436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73720.219436 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68248750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 68248750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68248750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 68248750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68248750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 68248750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71315.308255 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71315.308255 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71315.308255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71315.308255 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71315.308255 # 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number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1887325 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887325 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 9126055 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126055 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 9126055 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126055 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 162033829750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 162033829750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 75893768500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 75893768500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 237927598250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 237927598250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 237927598250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.016133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016133 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014975 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014975 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014975 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22384.289751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22384.289751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40212.347370 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40212.347370 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26071.243078 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26071.243078 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index 98d3f1024..2c6817645 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,479 +1,43 @@ ---------- Begin Simulation Statistics ---------- -final_tick 51810521500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -host_inst_rate 191326 # Simulator instruction rate (inst/s) -host_mem_usage 251752 # Number of bytes of host memory used -host_op_rate 191326 # Simulator op (including micro ops) rate (op/s) -host_seconds 480.35 # Real time elapsed on the host -host_tick_rate 107860315 # Simulator tick rate (ticks/s) +sim_seconds 0.051523 # Number of seconds simulated +sim_ticks 51522973500 # Number of ticks simulated +final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 192794 # Simulator instruction rate (inst/s) +host_op_rate 192794 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108084557 # Simulator tick rate (ticks/s) +host_mem_usage 244692 # Number of bytes of host memory used +host_seconds 476.69 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated -sim_seconds 0.051811 # Number of seconds simulated -sim_ticks 51810521500 # Number of ticks simulated +system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.960972 # BTB Hit Percentage -system.cpu.branchPred.BTBHits 5346983 # Number of BTB hits -system.cpu.branchPred.BTBLookups 6686991 # Number of BTB lookups -system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. -system.cpu.branchPred.condIncorrect 788623 # Number of conditional branches incorrect -system.cpu.branchPred.condPredicted 8172556 # Number of conditional branches predicted -system.cpu.branchPred.lookups 11403069 # Number of BP lookups -system.cpu.branchPred.usedRAS 1173096 # Number of times the RAS was used to get a target. -system.cpu.committedInsts 91903089 # Number of instructions committed -system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.cpi 1.127503 # CPI: cycles per instruction -system.cpu.dcache.ReadReq_accesses::cpu.inst 20044127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20044127 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 69928.365385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69928.365385 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 68014.432990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68014.432990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits::cpu.inst 20043607 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20043607 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36362750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36362750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::cpu.inst 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 32987000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32987000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 67476.975945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67476.975945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68165.329513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68165.329513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits::cpu.inst 6498193 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 196358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 196358000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::cpu.inst 2910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 118948500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 118948500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::cpu.inst 26545230 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26545230 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67848.615160 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency -system.cpu.dcache.demand_hits::cpu.inst 26541800 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26541800 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::cpu.inst 232720750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232720750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 151935500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151935500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses::cpu.inst 26545230 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26545230 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 67848.615160 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67848.615160 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68132.511211 # average overall mshr miss latency -system.cpu.dcache.overall_hits::cpu.inst 26541800 # number of overall hits -system.cpu.dcache.overall_hits::total 26541800 # number of overall hits -system.cpu.dcache.overall_miss_latency::cpu.inst 232720750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232720750 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 151935500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151935500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id -system.cpu.dcache.tags.avg_refs 11902.152466 # Average number of references to valid blocks. -system.cpu.dcache.tags.data_accesses 53092690 # Number of data accesses -system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.584633 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.353658 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353658 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.tag_accesses 53092690 # Number of tag accesses -system.cpu.dcache.tags.tagsinuse 1448.584633 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26541800 # Total number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.discardedOps 2238069 # Number of ops (including micro ops) which were discarded before commit -system.cpu.dtb.data_accesses 27017530 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 26970236 # DTB hits -system.cpu.dtb.data_misses 47294 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 20437728 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 20390711 # DTB read hits -system.cpu.dtb.read_misses 47017 # DTB read misses -system.cpu.dtb.write_accesses 6579802 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 6579525 # DTB write hits -system.cpu.dtb.write_misses 277 # DTB write misses -system.cpu.icache.ReadReq_accesses::cpu.inst 22978908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22978908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24673.484027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24673.484027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22586.223937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22586.223937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::cpu.inst 22963225 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22963225 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386954250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386954250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::cpu.inst 15683 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15683 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 354219750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 354219750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15683 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15683 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::cpu.inst 22978908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22978908 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24673.484027 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency -system.cpu.icache.demand_hits::cpu.inst 22963225 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22963225 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::cpu.inst 386954250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386954250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses -system.cpu.icache.demand_misses::cpu.inst 15683 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15683 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 354219750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 354219750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::cpu.inst 15683 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15683 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses::cpu.inst 22978908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22978908 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24673.484027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24673.484027 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22586.223937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22586.223937 # average overall mshr miss latency -system.cpu.icache.overall_hits::cpu.inst 22963225 # number of overall hits -system.cpu.icache.overall_hits::total 22963225 # number of overall hits -system.cpu.icache.overall_miss_latency::cpu.inst 386954250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386954250 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses -system.cpu.icache.overall_misses::cpu.inst 15683 # number of overall misses -system.cpu.icache.overall_misses::total 15683 # number of overall misses -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 354219750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 354219750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::cpu.inst 15683 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15683 # number of overall MSHR misses -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id -system.cpu.icache.tags.avg_refs 1464.211248 # Average number of references to valid blocks. -system.cpu.icache.tags.data_accesses 45973499 # Number of data accesses -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.514711 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.replacements 13718 # number of replacements -system.cpu.icache.tags.sampled_refs 15683 # Sample count of references to valid blocks. -system.cpu.icache.tags.tag_accesses 45973499 # Number of tag accesses -system.cpu.icache.tags.tagsinuse 1641.514711 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22963225 # Total number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.idleCycles 2226173 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.ipc 0.886915 # IPC: instructions per cycle -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 22978996 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 22978908 # ITB hits -system.cpu.itb.fetch_misses 88 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68029.959279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68029.959279 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55498.836533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55498.836533 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 116943500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 116943500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95402500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95402500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 16168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68200.931332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68200.931332 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55638.518210 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55638.518210 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits::cpu.inst 12571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 12571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245318750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245318750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.222476 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses::cpu.inst 3597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 200131750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200131750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222476 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3597 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses::cpu.inst 17913 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17913 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68145.645222 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.demand_hits::cpu.inst 12597 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12597 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::cpu.inst 362262250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 362262250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.296768 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.296768 # miss rate for demand accesses -system.cpu.l2cache.demand_misses::cpu.inst 5316 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5316 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295534250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 295534250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.296768 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5316 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses::cpu.inst 17913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17913 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68145.645222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68145.645222 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55593.350263 # average overall mshr miss latency -system.cpu.l2cache.overall_hits::cpu.inst 12597 # number of overall hits -system.cpu.l2cache.overall_hits::total 12597 # number of overall hits -system.cpu.l2cache.overall_miss_latency::cpu.inst 362262250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 362262250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.296768 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.296768 # miss rate for overall accesses -system.cpu.l2cache.overall_misses::cpu.inst 5316 # number of overall misses -system.cpu.l2cache.overall_misses::total 5316 # number of overall misses -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295534250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 295534250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.296768 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5316 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5316 # number of overall MSHR misses -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2506 # Occupied blocks per task id -system.cpu.l2cache.tags.avg_refs 3.435708 # Average number of references to valid blocks. -system.cpu.l2cache.tags.data_accesses 149568 # Number of data accesses -system.cpu.l2cache.tags.occ_blocks::writebacks 17.784221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2462.008081 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075677 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3663 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.sampled_refs 3663 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.tag_accesses 149568 # Number of tag accesses -system.cpu.l2cache.tags.tagsinuse 2479.792302 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12585 # Total number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.numCycles 103621043 # number of cpu cycles simulated -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.tickCycles 101394870 # Number of cycles that the CPU actually ticked -system.cpu.toL2Bus.data_through_bus 1153280 # Total data (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 9117000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24208750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3732500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.throughput 22259571 # Throughput (bytes/s) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1003712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 1153280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.trans_dist::ReadReq 16168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 16168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.membus.data_through_bus 340224 # Total data (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10632 # Packet count per connected master and slave (bytes) -system.membus.reqLayer0.occupancy 6066000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 49708250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.throughput 6566697 # Throughput (bytes/s) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 340224 # Cumulative packet size per connected master and slave (bytes) -system.membus.trans_dist::ReadReq 3597 # Transaction distribution -system.membus.trans_dist::ReadResp 3597 # Transaction distribution -system.membus.trans_dist::ReadExReq 1719 # Transaction distribution -system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgGap 9746132.43 # Average gap between requests -system.physmem.avgMemAccLat 25349.60 # Average memory access latency per DRAM burst -system.physmem.avgQLat 6599.60 # Average queueing delay per DRAM burst -system.physmem.avgRdBW 6.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.57 # Average system read bandwidth in MiByte/s -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.bw_inst_read::cpu.inst 3909631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3909631 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 6566697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6566697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6566697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6566697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytesPerActivate::samples 980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 346.710204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.810529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.902824 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 318 32.45% 32.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 196 20.00% 52.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 101 10.31% 62.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 95 9.69% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 76 7.76% 80.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 37 3.78% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 22 2.24% 86.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21 2.14% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 114 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 980 # Bytes accessed per row activation -system.physmem.bytesReadDRAM 340224 # Total number of bytes read from DRAM -system.physmem.bytesReadSys 340224 # Total read bytes from the system interface side +system.physmem.bytes_read::cpu.inst 340096 # Number of bytes read from this memory +system.physmem.bytes_read::total 340096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202432 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202432 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 5314 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5314 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 6600861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6600861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3928966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3928966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6600861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6600861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5314 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 5314 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 340096 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 340096 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.bytes_inst_read::cpu.inst 202560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202560 # Number of instructions bytes read from this memory -system.physmem.bytes_read::cpu.inst 340224 # Number of bytes read from this memory -system.physmem.bytes_read::total 340224 # Number of bytes read from this memory -system.physmem.memoryStateTime::IDLE 48729835000 # Time in different power states -system.physmem.memoryStateTime::REF 1730040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 1350106250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.num_reads::cpu.inst 5316 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5316 # Number of read requests responded to by this memory -system.physmem.pageHitRate 81.55 # Row buffer hit rate, read and write combined -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.perBankRdBursts::0 469 # Per bank write bursts +system.physmem.perBankRdBursts::0 468 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts system.physmem.perBankRdBursts::2 307 # Per bank write bursts system.physmem.perBankRdBursts::3 523 # Per bank write bursts @@ -485,7 +49,7 @@ system.physmem.perBankRdBursts::8 251 # Pe system.physmem.perBankRdBursts::9 282 # Per bank write bursts system.physmem.perBankRdBursts::10 255 # Per bank write bursts system.physmem.perBankRdBursts::11 260 # Per bank write bursts -system.physmem.perBankRdBursts::12 409 # Per bank write bursts +system.physmem.perBankRdBursts::12 408 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts system.physmem.perBankRdBursts::14 500 # Per bank write bursts system.physmem.perBankRdBursts::15 448 # Per bank write bursts @@ -505,9 +69,26 @@ system.physmem.perBankWrBursts::12 0 # Pe system.physmem.perBankWrBursts::13 0 # Per bank write bursts system.physmem.perBankWrBursts::14 0 # Per bank write bursts system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.rdQLenPdf::0 4911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 51522892000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 5314 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 4908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -537,22 +118,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.readBursts 5316 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5316 # Read request sizes (log2) -system.physmem.readReqs 5316 # Number of read requests accepted -system.physmem.readRowHitRate 81.55 # Row buffer hit rate for reads -system.physmem.readRowHits 4335 # Number of row buffer hits during reads -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.totBusLat 26580000 # Total ticks spent in databus transfers -system.physmem.totGap 51810440000 # Total gap between requests -system.physmem.totMemAccLat 134758500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totQLat 35083500 # Total ticks spent queuing system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -617,17 +182,452 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.bytesPerActivate::samples 970 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.690722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.310004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.842695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 314 32.37% 32.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 200 20.62% 52.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 99 10.21% 63.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 77 7.94% 71.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 82 8.45% 79.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 28 2.89% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation +system.physmem.totQLat 35128750 # Total ticks spent queuing +system.physmem.totMemAccLat 134766250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6610.60 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 25360.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.05 # Data bus utilization in percentage +system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 4339 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.voltage_domain.voltage 1 # Voltage in Volts +system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 9695689.12 # Average gap between requests +system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 48460398500 # Time in different power states +system.physmem.memoryStateTime::REF 1720420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 1341071500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 6600861 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3595 # Transaction distribution +system.membus.trans_dist::ReadResp 3595 # Transaction distribution +system.membus.trans_dist::ReadExReq 1719 # Transaction distribution +system.membus.trans_dist::ReadExResp 1719 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10628 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 340096 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 6106000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 49717250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 11407310 # Number of BP lookups +system.cpu.branchPred.condPredicted 8177170 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 788660 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6672659 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5348436 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 80.154493 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1172954 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 20390002 # DTB read hits +system.cpu.dtb.read_misses 46972 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 20436974 # DTB read accesses +system.cpu.dtb.write_hits 6579989 # DTB write hits +system.cpu.dtb.write_misses 273 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 6580262 # DTB write accesses +system.cpu.dtb.data_hits 26969991 # DTB hits +system.cpu.dtb.data_misses 47245 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 27017236 # DTB accesses +system.cpu.itb.fetch_hits 22956123 # ITB hits +system.cpu.itb.fetch_misses 88 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 22956211 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.numCycles 103045947 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 91903089 # Number of instructions committed +system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2250201 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 1.121246 # CPI: cycles per instruction +system.cpu.ipc 0.891865 # IPC: instructions per cycle +system.cpu.tickCycles 100852498 # Number of cycles that the object actually ticked +system.cpu.idleCycles 2193449 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 13697 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.300459 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22940462 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1464.814635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300459 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45927907 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45927907 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22940462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22940462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22940462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22940462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22940462 # number of overall hits +system.cpu.icache.overall_hits::total 22940462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses +system.cpu.icache.overall_misses::total 15661 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 385817000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 385817000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 385817000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 385817000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 385817000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 385817000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22956123 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22956123 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22956123 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22956123 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22956123 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22956123 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24635.527744 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15661 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15661 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15661 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353131000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 353131000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353131000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 353131000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353131000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 353131000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16146 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 31322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4567 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1002304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 1151872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1151872 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 9106000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 24173500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 2477.580709 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 17.790278 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790431 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2504 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.111725 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 149390 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149390 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 12551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 12551 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 26 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12577 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 12577 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12577 # number of overall hits +system.cpu.l2cache.overall_hits::total 12577 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3595 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3595 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 1719 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1719 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses +system.cpu.l2cache.overall_misses::total 5314 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245039250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 245039250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117228000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 117228000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362267250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 362267250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362267250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 362267250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1745 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 17891 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17891 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 17891 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17891 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.222656 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.222656 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985100 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3595 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1719 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95675500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95675500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295536750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 295536750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 295536750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1448.553123 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26545427 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11903.778924 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553123 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 53099944 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53099944 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 20047235 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20047235 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.inst 26545427 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26545427 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 26545427 # number of overall hits +system.cpu.dcache.overall_hits::total 26545427 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2911 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 3430 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 3430 # number of overall misses +system.cpu.dcache.overall_misses::total 3430 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198662500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 198662500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 235539250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235539250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 235539250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235539250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20047754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.inst 26548857 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26548857 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 26548857 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26548857 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000448 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.000129 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68670.335277 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 34 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 1166 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1166 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 1200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1745 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1745 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 2230 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 119233500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152805750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 152805750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 152805750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |